CN110164394A - Sequence controller and timing control panel - Google Patents
Sequence controller and timing control panel Download PDFInfo
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- CN110164394A CN110164394A CN201910483112.XA CN201910483112A CN110164394A CN 110164394 A CN110164394 A CN 110164394A CN 201910483112 A CN201910483112 A CN 201910483112A CN 110164394 A CN110164394 A CN 110164394A
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- integrated circuit
- spi
- serial peripheral
- peripheral interface
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
This announcement provides a kind of sequence controller and timing control panel.The sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit.The micro-control unit is to control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit, and to be connected to the interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from the write instruction of unit when, first to the Serial Peripheral Interface (SPI) from unit send sector erasing instruction, write it is enabled after just send write instruction, and data check is carried out after the completion of write-in.
Description
[technical field]
This announcement is related to field of display technology, in particular to a kind of sequence controller and timing control panel.
[background technique]
In liquid crystal television panel display industry, due to partial power managing chip (Power Manage Integral
Chip, PMIC) in nonvolatile semiconductor memory member is not present, but the data of configuration register in PMIC are stored in external sudden strain of a muscle
It deposits in (Flash Memory) and turns serial outer through interior integrated circuit (Inter-Integrated Circuit, I2C) bus
If interface (Serial Peripheral Interface, SPI) bus is accessed.
General general I2C bus turns spi bus interface at present, in specific operating process, needs according to flash memory
Read write attribute is adapted to.When executing the write-in data manipulation of a sector (sector) to flash memory, need to send respectively specific
Flash memory write enable (write enable), sector erasing (sector erasing), busy bit (busy bit) detection, comprising dodge
The write instruction etc. of address information to be deposited, and is generally needed to be added specific flash memory physical address information, operating process is complex,
It is easy error.
Therefore it is in need a kind of sequence controller and timing control panel be provided, it is of the existing technology to solve the problems, such as.
[summary of the invention]
In order to solve the above technical problems, the one of this announcement is designed to provide a kind of sequence controller and timing control panel,
Can have certain flexibility and scalability, simplify the instruction operation of interior integrated circuit unit.
To reach above-mentioned purpose, this announcement provides a kind of sequence controller, including micro-control unit, interior integrated circuit are from list
Member and Serial Peripheral Interface (SPI) master unit.The micro-control unit is to execute following effect:
The interior integrated circuit is controlled to be communicated from unit and external interior integrated circuit master unit；
The Serial Peripheral Interface (SPI) master unit is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit.
Wherein, the micro-control unit is to be connected to the interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from list
When the write instruction of member, first to the Serial Peripheral Interface (SPI) from unit send sector erasing instruction, write it is enabled after just send and be written
Instruction, and data check is carried out after the completion of write-in.
In this announcement embodiment therein, the interior integrated circuit master unit is located among power management chip.
In this announcement embodiment therein, the Serial Peripheral Interface (SPI) is located among flash cell from unit.Institute
Stating flash cell includes multiple storage sectors.The storage sector has respective physical address.
In this announcement embodiment therein, the power management chip is to penetrate the interior main list of integrated circuit
First and the sequence controller the interior integrated circuit is from unit communications, to read the number being stored in the flash cell
According to.
In this announcement embodiment therein, the micro-control unit is in being connected to the interior integrated circuit master unit pair
The Serial Peripheral Interface (SPI) sends sector erasing instruction from unit after the write instruction of unit, to the Serial Peripheral Interface (SPI)
Before, busy bit message is sent, and send after the completion of data check and exit busy bit message.
This announcement also provides a kind of timing control plate, including sequence controller, power management chip and flash cell.
The sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit.The micro-control
Unit processed is to execute following effect:
The interior integrated circuit is controlled to be communicated from the interior integrated circuit master unit of unit and the power management chip；
The Serial Peripheral Interface (SPI) for controlling the Serial Peripheral Interface (SPI) master unit and the flash cell is communicated from unit；
And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit.
Wherein, the micro-control unit is to be connected to the interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from list
When the write instruction of member, first to the Serial Peripheral Interface (SPI) from unit send sector erasing instruction, write it is enabled after just send and be written
Instruction, and data check is carried out after the completion of write-in.
In this announcement embodiment therein, the timing control plate, wherein the interior integrated circuit master unit position
Among power management chip.
In this announcement embodiment therein, the timing control plate, wherein the Serial Peripheral Interface (SPI) is from unit
Among flash cell.The flash cell includes multiple storage sectors.The storage sector has respective physical address.
In this announcement embodiment therein, the timing control plate, wherein the power management chip is to saturating
The interior integrated circuit of the interior integrated circuit master unit and the sequence controller is crossed from unit communications, is stored in reading
Data in the flash cell.
In this announcement embodiment therein, the timing control plate, wherein the micro-control unit is in being connected to
Interior integrated circuit master unit is stated to the Serial Peripheral Interface (SPI) after the write instruction of unit, to the Serial Peripheral Interface (SPI) from list
Before member sends sector erasing instruction, busy bit message is sent, and send after the completion of data check and exit busy bit message.
Since in the sequence controller and timing control panel of this revealed embodiment, the micro-control unit is to be connected to
State interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from the write instruction of unit when, first to the Serial Peripheral Interface (SPI) from
Unit send sector erasing instruction, write it is enabled after just send write instruction, and data check is carried out after the completion of write-in.Therefore,
The instruction of the interior integrated circuit unit can be made to simplify, user can effectively be hidden and write enabled, busy bit detection, sector wiping
It removes, the operation such as data check, is easy to use.
For the above content of this announcement can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows:
[Detailed description of the invention]
Fig. 1 shows the structural schematic diagram of the timing control plate of the embodiment according to this announcement；
Fig. 2 shows the instruction format schematic diagram of the interior integrated circuit unit of the embodiment according to this announcement；
Fig. 3 shows that the write instruction of the interior integrated circuit unit of the embodiment according to this announcement executes flow diagram；
Fig. 4 is shown according to the interior integrated circuit of an embodiment of this announcement from the online of unit and interior integrated circuit master unit
Schematic diagram；
Fig. 5 is shown according to the Serial Peripheral Interface (SPI) master unit of an embodiment of this announcement and Serial Peripheral Interface (SPI) from unit
On-line mode schematic diagram；And
Fig. 6 shows the reading instruction execution flow schematic diagram of the interior integrated circuit unit of the embodiment according to this announcement.
[specific embodiment]
In order to which the above-mentioned and other purposes of this announcement, feature, advantage can be clearer and more comprehensible, it is excellent that spy is hereafter lifted into this announcement
Embodiment is selected, and cooperates institute's accompanying drawings, is described in detail below.Furthermore the direction term that this announcement is previously mentioned, such as above and below,
Top, bottom, front, rear, left and right, inside and outside, side layer, around, center, it is horizontal, laterally, vertically, longitudinally, axial direction, radial direction, top layer or
Lowest level etc. is only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand this announcement, and
It is non-to limit this announcement.
The similar unit of structure is to be given the same reference numerals in the figure.
Referring to Fig.1 and Fig. 3, this announcement provide a kind of sequence controller 100, including micro-control unit 110, interior integrated electricity
Road is from unit 120 and Serial Peripheral Interface (SPI) master unit 130.The micro-control unit 110 is to execute following effect:
The interior integrated circuit is controlled to be communicated from unit 120 and external interior integrated circuit master unit 220；
The Serial Peripheral Interface (SPI) master unit 130 is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit 330；With
And
Control data conversion of the interior integrated circuit between unit 120 and the Serial Peripheral Interface (SPI) master unit 130.
Wherein, the micro-control unit 110 connects the serial peripheral to be connected to the interior integrated circuit master unit 220
When mouthful from the write instruction of unit 330, first to the Serial Peripheral Interface (SPI) from unit 330 send sector erasing instruction, write it is enabled
Write instruction is just sent afterwards, and data check is carried out after the completion of write-in.
In this announcement embodiment therein, the interior integrated circuit master unit 220 is located at power management chip 200
Among.
In this announcement embodiment therein, the Serial Peripheral Interface (SPI) from unit 330 be located at flash cell 300 it
In.The flash cell 300 include multiple storage sector 3S1,3S2,3S3 ... 3Sn.The storage sector 3S1,3S2,
3S3 ... 3Sn has respective physical address.
Referring to Fig.1, in this announcement embodiment therein, the power management chip 200 is to through described interior
The interior integrated circuit of integrated circuit master unit 220 and the sequence controller 100 is communicated from unit 120, to read storage
Data in the flash cell 300.
In this announcement embodiment therein, the micro-control unit 110 is in being connected to the main list of interior integrated circuit
First 220 pairs of Serial Peripheral Interface (SPI)s are sent after the write instruction of unit 120, to the Serial Peripheral Interface (SPI) from unit 330
Before sector erasing instruction, busy bit message is sent, and send after the completion of data check and exit busy bit message.
Specifically, the instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 2.Interior integrated circuit master unit is sent
Initial signal Start communicates to open.All interior integrated circuits can enter after receiving initial signal Start from unit to be received
Data pattern.Then, interior integrated circuit master unit sends the address address of communication target device totally 7 and one readings
Or write R/W information.1 indicates to read, and 0 indicates to write.Come again, after interior integrated circuit receives address address from unit, meets the address
The interior integrated circuit of address can send the response Ack an of position from unit.Interior integrated circuit master unit receives response Ack meeting
The R/W information that reads or writes depending on its script enters reception or output mode.Then in the data of transmission, interior integrated circuit can from unit
To issue a response Ack at the end of the transmission of each byte.Finally, interior integrated circuit master unit issues at the end of transmission
Stop signal Stop.
Specifically, the write instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 2 and Fig. 3.The interior integrated electricity
Road master unit 220 sends initial signal Start to open communication.The interior integrated circuit receives initial signal from unit 120
It can enter after Start and receive data pattern.Then, the interior integrated circuit master unit 220 sends the address of communication target device
Address totally 7 and one writes W information 0.Come again, after the interior integrated circuit receives address address from unit 120,
The interior integrated circuit for meeting address address can send the response Ack an of position from unit 120 and trigger interruption.Institute
It states after interior integrated circuit master unit 220 receives response Ack, then transmits the instruction code Cmd that flash cell 300 is written.It writes
Entering instruction code Cmd is, for example, 02H, this announcement is without being limited thereto.And after the micro-control unit 110 detects interruption, it waits simultaneously
Receive instruction code 02h.After instruction code transmits, the interior integrated circuit sends a response Ack from unit 120 and triggers
It interrupts.After the interior integrated circuit master unit 220 receives response Ack, the address details of the flash cell 300 are then transmitted
Flash add.And after the micro-control unit 110 detects interruption, wait and receive the address details of the flash cell 300
Flash add.After address details have transmitted, the interior integrated circuit issues response Ack from unit 120 and triggers interruption.It is described
After interior integrated circuit master unit 220 receives response Ack, then transmission be intended to be written the flash cell 300 data data 0,
data 1,…data n.For Fig. 3 only lifts data 0, this announcement is without being limited thereto.And during the micro-control unit 110 detects
It has no progeny, wait and receives the data data0 for being intended to be written the flash cell 300.It is described interior after the data for often receiving a byte
Integrated circuit just issues response Ack from unit 120 and triggers interruption.The interior integrated circuit master unit 220 receives response Ack
Afterwards, next data that the flash cell 300 is written then are transmitted.And after the micro-control unit 110 detects interruption,
It waits and reads data and deposit data into caching.Cache such as dynamic random access memory.It is finished in total data transmission
Later, the interior integrated circuit master unit 220, which issues, stops Stop signal.The micro-control unit 110 then pull-up busy bit signal
Busy, into busy condition.After the interior integrated circuit master unit 220 detects busy bit signal busy, flash cell to be written is waited
Movement complete.
Specifically, the micro-control unit 110 connects the serial peripheral through the Serial Peripheral Interface (SPI) master unit 130
Mouthful from unit 330 send sector erasing instruction, write it is enabled after just send write instruction Cmd.After data are written, the micro-control
Unit 110 processed through the Serial Peripheral Interface (SPI) master unit 130 by data readback, compare whether just to verify the data of write-in
Really.Then, the micro-control unit 110 falls busy bit signal busy, exits busy condition.
Specifically, referring to Fig. 4, the interior integrated circuit is online from unit 120 and the interior integrated circuit master unit 220
Mode is as shown, interior integrated circuit unit bus is communicated using serial data line SDA and serial time clock line SCL.
Specifically, referring to Fig. 5, the Serial Peripheral Interface (SPI) master unit 130 and the Serial Peripheral Interface (SPI) are from unit 330
On-line mode is as shown, Serial Peripheral Interface (SPI) unit bus uses four interfaces: serial time clock line SCLK, it is main go out from entering line
MOSI, master enter from outlet MISO and slave selection line SS.
Specifically, the reading instruction format of interior integrated circuit unit is as shown in Figure 2 referring to Fig. 2 and Fig. 6.It is described interior integrated
Circuit master unit 220 sends initial signal Start to open communication.The interior integrated circuit receives starting letter from unit 120
It can enter after number Start and receive data pattern.Then, the interior integrated circuit master unit 220 sends the ground of communication target device
Location address totally 7 and one reading R information 1.Come again, the interior integrated circuit receives address address from unit 120
Afterwards, the interior integrated circuit for meeting address address can send the response Ack an of position from unit 120 and trigger interruption.
After the interior integrated circuit master unit 220 receives response Ack, the instruction code Cmd read to flash cell 300 is then transmitted.
Reading instruction code Cmd is, for example, 0BH, this announcement is without being limited thereto.And after the micro-control unit 110 detects interruption, it waits
And receive instruction code 0BH.After instruction code transmits, the interior integrated circuit sends a response Ack from unit 120 and touches
Hair interrupts.After the interior integrated circuit master unit 220 receives response Ack, the address details of the flash cell 300 are then transmitted
Flash add.After the micro-control unit 110 detects interruption, waits and receive address details Flash add.Address details
After transmission, the interior integrated circuit sends a response Ack from unit 120 and triggers interruption.The micro-control unit 110 will
Instruction code Cmd and address details Flash add is read through the Serial Peripheral Interface (SPI) master unit 130 to the serial peripheral
Interface is sent from unit 330.The flash cell 300 reads data data 0, data 1 in the address etc. and returns, and originally takes off
Show only two data instances of act, but this announcement is without being limited thereto.
After data data 0, data 1 pass back to the micro-control unit 110, the micro-control unit 110 can control institute
It states interior integrated circuit and issues an initial signal Start from unit 120.The interior integrated circuit master unit 220 receives starting letter
Read mode can be entered after number Start.The interior integrated circuit then issues oneself address address totally 7 from unit 120
Position, one reading R information 1 and response Ack simultaneously trigger interruption.After the micro-control unit 110 detects interruption, just start
Data data 0 is transmitted from unit 120 to the interior integrated circuit master unit 220 through the interior integrated circuit.It is described interior integrated
After circuit master unit 220 receives response Ack, waits and read data data 0.It is described interior after the data for often receiving a byte
Integrated circuit master unit 220 can send a response Ack.After the micro-control unit 110 detects response Ack, through described
Interior integrated circuit transmits next data from unit 120 to the interior integrated circuit master unit 220.After data receiver is complete,
The interior integrated circuit master unit 220 can send unresponsive nAck and stop signal Stop.The micro-control unit 110 is received
To after unresponsive nAck, stop reading data from flash cell 300 immediately.
Referring to Fig.1, this announcement also provides a kind of timing control plate 1000, including sequence controller 100, power management chip
200 and flash cell 300.The sequence controller 100 include micro-control unit 110, interior integrated circuit from unit 120 with
And Serial Peripheral Interface (SPI) master unit 130.The micro-control unit 100 is to execute following effect:
Control interior integrated circuit master unit 220 of the interior integrated circuit from unit 120 and the power management chip 200
It is communicated；
The Serial Peripheral Interface (SPI) of the Serial Peripheral Interface (SPI) master unit 130 and the flash cell 300 is controlled from unit 330
It is communicated；And
Control data conversion of the interior integrated circuit between unit 120 and the Serial Peripheral Interface (SPI) master unit 130.
Wherein, the micro-control unit 110 connects the serial peripheral to be connected to the interior integrated circuit master unit 220
When mouthful from the write instruction of unit 330, first to the Serial Peripheral Interface (SPI) from unit 330 send sector erasing instruction, write it is enabled
Write instruction is just sent afterwards, and data check is carried out after the completion of write-in.
In this announcement embodiment therein, the timing control plate 1000, wherein the interior main list of integrated circuit
Member 120 is located among power management chip 200.
In this announcement embodiment therein, the timing control plate 1000, wherein the Serial Peripheral Interface (SPI) from
Unit 330 is located among flash cell 300.The flash cell 300 include multiple storage sector 3S1,3S2,3S3 ... 3Sn.
The storage sector 3S1,3S2,3S3 ... 3Sn have respective physical address.
In this announcement embodiment therein, the timing control plate 1000, wherein the power management chip
200 to the interior integrated circuit through the interior integrated circuit master unit 220 and the sequence controller 100 from unit
120 communications, to read the data being stored in the flash cell 300.
In this announcement embodiment therein, the timing control plate 1000, wherein the micro-control unit 110
In being connected to the interior integrated circuit master unit 220 to the Serial Peripheral Interface (SPI) after the write instruction of unit 330, to the string
Row Peripheral Interface sends busy bit message, and send and exit after the completion of data check before the transmission sector erasing instruction of unit 330
Busy bit message.
Specifically, the instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 2.Interior integrated circuit master unit is sent
Initial signal Start communicates to open.All interior integrated circuits can enter after receiving initial signal Start from unit to be received
Data pattern.Then, interior integrated circuit master unit sends the address address of communication target device totally 7 and one readings
Or write R/W information.1 indicates to read, and 0 indicates to write.Come again, after interior integrated circuit receives address address from unit, meets the address
The interior integrated circuit of address can send the response Ack an of position from unit.Interior integrated circuit master unit receives response Ack meeting
The R/W information that reads or writes depending on its script enters reception or output mode.Then in the data of transmission, interior integrated circuit can from unit
To issue a response Ack at the end of the transmission of each byte.Finally, interior integrated circuit master unit issues at the end of transmission
Stop signal Stop.
Specifically, the write instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 2 and Fig. 3.The interior integrated electricity
Road master unit 220 sends initial signal Start to open communication.The interior integrated circuit receives initial signal from unit 120
It can enter after Start and receive data pattern.Then, the interior integrated circuit master unit 220 sends the address of communication target device
Address totally 7 and one writes W information 0.Come again, after the interior integrated circuit receives address address from unit 120,
The interior integrated circuit for meeting address address can send the response Ack an of position from unit 120 and trigger interruption.Institute
It states after interior integrated circuit master unit 220 receives response Ack, then transmits the instruction code Cmd that flash cell 300 is written.It writes
Entering instruction code Cmd is, for example, 02H, this announcement is without being limited thereto.And after the micro-control unit 110 detects interruption, it waits simultaneously
Receive instruction code 02h.After instruction code transmits, the interior integrated circuit sends a response Ack from unit 120 and triggers
It interrupts.After the interior integrated circuit master unit 220 receives response Ack, the address details of the flash cell 300 are then transmitted
Flash add.And after the micro-control unit 110 detects interruption, wait and receive the address details of the flash cell 300
Flash add.After address details have transmitted, the interior integrated circuit issues response Ack from unit 120 and triggers interruption.It is described
After interior integrated circuit master unit 220 receives response Ack, then transmission be intended to be written the flash cell 300 data data 0,
data 1,…data n.For Fig. 3 only lifts data 0, this announcement is without being limited thereto.And during the micro-control unit 110 detects
It has no progeny, wait and receives the data data 0 for being intended to be written the flash cell 300.It is described after the data for often receiving a byte
Interior integrated circuit just issues response Ack from unit 120 and triggers interruption.The interior integrated circuit master unit 220 receives response Ack
Afterwards, next data that the flash cell 300 is written then are transmitted.And after the micro-control unit 110 detects interruption,
It waits and reads data and deposit data into caching.Cache such as dynamic random access memory.It is finished in total data transmission
Later, the interior integrated circuit master unit 220, which issues, stops Stop signal.The micro-control unit 110 then pull-up busy bit signal
Busy, into busy condition.After the interior integrated circuit master unit 220 detects busy bit signal busy, flash cell to be written is waited
Movement complete.
Specifically, the micro-control unit 110 connects the serial peripheral through the Serial Peripheral Interface (SPI) master unit 130
Mouthful from unit 330 send sector erasing instruction, write it is enabled after just send write instruction Cmd.After data are written, the micro-control
Unit 110 processed through the Serial Peripheral Interface (SPI) master unit 130 by data readback, compare whether just to verify the data of write-in
Really.Then, the micro-control unit 110 falls busy bit signal busy, exits busy condition.
Specifically, referring to Fig. 4, the interior integrated circuit is online from unit 120 and the interior integrated circuit master unit 220
Mode is as shown, interior integrated circuit unit bus is communicated using serial data line SDA and serial time clock line SCL.
Specifically, referring to Fig. 5, the Serial Peripheral Interface (SPI) master unit 130 and the Serial Peripheral Interface (SPI) are from unit 330
On-line mode is as shown, Serial Peripheral Interface (SPI) unit bus uses four interfaces: serial time clock line SCLK, it is main go out from entering line
MOSI, master enter from outlet MISO and slave selection line SS.
Specifically, the reading instruction format of interior integrated circuit unit is as shown in Figure 2 referring to Fig. 2 and Fig. 6.It is described interior integrated
Circuit master unit 220 sends initial signal Start to open communication.The interior integrated circuit receives starting letter from unit 120
It can enter after number Start and receive data pattern.Then, the interior integrated circuit master unit 220 sends the ground of communication target device
Location address totally 7 and one reading R information 1.Come again, the interior integrated circuit receives address address from unit 120
Afterwards, the interior integrated circuit for meeting address address can send the response Ack an of position from unit 120 and trigger interruption.
After the interior integrated circuit master unit 220 receives response Ack, the instruction code Cmd read to flash cell 300 is then transmitted.
Reading instruction code Cmd is, for example, 0BH, this announcement is without being limited thereto.And after the micro-control unit 110 detects interruption, it waits
And receive instruction code 0BH.After instruction code transmits, the interior integrated circuit sends a response Ack from unit 120 and touches
Hair interrupts.After the interior integrated circuit master unit 220 receives response Ack, the address details of the flash cell 300 are then transmitted
Flash add.After the micro-control unit 110 detects interruption, waits and receive address details Flash add.Address details
After transmission, the interior integrated circuit sends a response Ack from unit 120 and triggers interruption.The micro-control unit 110 will
Instruction code Cmd and address details Flash add is read through the Serial Peripheral Interface (SPI) master unit 130 to the serial peripheral
Interface is sent from unit 330.The flash cell 300 reads data data 0, data 1 in the address etc. and returns, and originally takes off
Show only two data instances of act, but this announcement is without being limited thereto.
After data data 0, data 1 pass back to the micro-control unit 110, the micro-control unit 110 can control institute
It states interior integrated circuit and issues an initial signal Start from unit 120.The interior integrated circuit master unit 220 receives starting letter
Read mode can be entered after number Start.The interior integrated circuit then issues oneself address address totally 7 from unit 120
Position, one reading R information 1 and response Ack simultaneously trigger interruption.After the micro-control unit 110 detects interruption, just start
Data data 0 is transmitted from unit 120 to the interior integrated circuit master unit 220 through the interior integrated circuit.It is described interior integrated
After circuit master unit 220 receives response Ack, waits and read data data 0.It is described interior after the data for often receiving a byte
Integrated circuit master unit 220 can send a response Ack.After the micro-control unit 110 detects response Ack, through described
Interior integrated circuit transmits next data from unit 120 to the interior integrated circuit master unit 220.After data receiver is complete,
The interior integrated circuit master unit 220 can send unresponsive nAck and stop signal Stop.The micro-control unit 110 is received
To after unresponsive nAck, stop reading data from flash cell 300 immediately.
Since in the sequence controller and timing control panel of this revealed embodiment, the micro-control unit is to be connected to
State interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from the write instruction of unit when, first to the Serial Peripheral Interface (SPI) from
Unit send sector erasing instruction, write it is enabled after just send write instruction, and data check is carried out after the completion of write-in.Therefore,
The instruction of the interior integrated circuit unit can be made to simplify, user can effectively be hidden and write enabled, busy bit detection, sector wiping
It removes, the operation such as data check, is easy to use.
Although this announcement, those skilled in the art have shown and described relative to one or more implementations
It will be appreciated that equivalent variations and modification based on the reading and understanding to the specification and drawings.This announcement includes all such repairs
Change and modification, and is limited only by the scope of the following claims.In particular, to various functions executed by the above components, use
It is intended to correspond in the term for describing such component and executes the specified function of the component (such as it is functionally of equal value
) random component (unless otherwise instructed), even if in structure with execute the exemplary of this specification shown in this article and realize
The open structure of function in mode is not equivalent.In addition, although the special characteristic of this specification is relative to several realization sides
Only one in formula is disclosed, but this feature can with such as can be for a given or particular application expectation and it is advantageous
One or more other features combinations of other implementations.Moreover, with regard to term " includes ", " having ", " containing " or its deformation
For being used in specific embodiments or claims, such term is intended to wrap in a manner similar to the term " comprising "
It includes.
The above is only the preferred embodiments of this announcement, it is noted that for those of ordinary skill in the art, is not departing from
Under the premise of this announcement principle, several improvements and modifications can also be made, these improvements and modifications also should be regarded as the guarantor of this announcement
Protect range.
Claims (10)
1. a kind of sequence controller, which is characterized in that connect including micro-control unit, interior integrated circuit from unit and serial peripheral
Mouth master unit, the micro-control unit is to execute following effect:
The interior integrated circuit is controlled to be communicated from unit and external interior integrated circuit master unit；
The Serial Peripheral Interface (SPI) master unit is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit；
Wherein, the micro-control unit is to be connected to the interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from unit
When write instruction, first to the Serial Peripheral Interface (SPI) from unit send sector erasing instruction, write it is enabled after just send write instruction,
And data check is carried out after the completion of write-in.
2. sequence controller as described in claim 1, which is characterized in that the interior integrated circuit master unit is located at power management
Among chip.
3. sequence controller as claimed in claim 2, which is characterized in that the Serial Peripheral Interface (SPI) is located at flash memory list from unit
Among member, the flash cell includes multiple storage sectors, and the storage sector has respective physical address.
4. sequence controller as claimed in claim 3, which is characterized in that the power management chip is to penetrate the interior collection
At the interior integrated circuit of circuit master unit and the sequence controller from unit communications, the flash memory list is stored in read
Data in member.
5. sequence controller as described in claim 1, which is characterized in that the micro-control unit is in being connected to the interior integrated electricity
Road master unit after the write instruction of unit, sends sector from unit to the Serial Peripheral Interface (SPI) to the Serial Peripheral Interface (SPI)
Before erasing instruction, busy bit message is sent, and send after the completion of data check and exit busy bit message.
6. a kind of timing control plate, which is characterized in that described including sequence controller, power management chip and flash cell
Sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit, the microcontroller list
Member is to execute following effect:
The interior integrated circuit is controlled to be communicated from the interior integrated circuit master unit of unit and the power management chip；
The Serial Peripheral Interface (SPI) for controlling the Serial Peripheral Interface (SPI) master unit and the flash cell is communicated from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit；
Wherein, the micro-control unit is to be connected to the interior integrated circuit master unit to the Serial Peripheral Interface (SPI) from unit
When write instruction, first to the Serial Peripheral Interface (SPI) from unit send sector erasing instruction, write it is enabled after just send write instruction,
And data check is carried out after the completion of write-in.
7. timing control plate as claimed in claim 6, which is characterized in that the interior integrated circuit master unit is located at power management
Among chip.
8. timing control plate as claimed in claim 7, which is characterized in that the Serial Peripheral Interface (SPI) is located at flash memory list from unit
Among member, the flash cell includes multiple storage sectors, and the storage sector has respective physical address.
9. timing control plate as claimed in claim 8, which is characterized in that the power management chip is to penetrate the interior collection
At the interior integrated circuit of circuit master unit and the sequence controller from unit communications, the flash memory list is stored in read
Data in member.
10. timing control plate as claimed in claim 6, which is characterized in that the micro-control unit is described interior integrated in being connected to
Circuit master unit after the write instruction of unit, the Serial Peripheral Interface (SPI) is sent from unit and is fanned to the Serial Peripheral Interface (SPI)
Before area's erasing instruction, busy bit message is sent, and send after the completion of data check and exit busy bit message.
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