CN110164394B - Time sequence controller and time sequence control board - Google Patents
Time sequence controller and time sequence control board Download PDFInfo
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- CN110164394B CN110164394B CN201910483112.XA CN201910483112A CN110164394B CN 110164394 B CN110164394 B CN 110164394B CN 201910483112 A CN201910483112 A CN 201910483112A CN 110164394 B CN110164394 B CN 110164394B
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The present disclosure provides a timing controller and a timing control board. The time schedule controller comprises a micro control unit, an inner integrated circuit slave unit and a serial peripheral interface master unit. The micro control unit is used for controlling data conversion between the internal integrated circuit slave unit and the serial peripheral interface master unit, and is used for sending a sector erasing instruction and a writing enabling instruction to the serial peripheral interface slave unit when receiving a writing instruction of the internal integrated circuit master unit to the serial peripheral interface slave unit, then sending the writing instruction, and carrying out data verification after the writing is finished.
Description
[ technical field ] A method for producing a semiconductor device
The present disclosure relates to display technologies, and in particular, to a timing controller and a timing control board.
[ background of the invention ]
In the lcd panel display industry, since a non-volatile Memory device does not exist in part of Power Management Integrated Chips (PMICs), data of a configuration register in the PMIC is stored in an external Flash Memory (Flash Memory) and is accessed through an Inter-Integrated Circuit (I2C) bus to Serial Peripheral Interface (SPI) bus.
At present, a general I2C bus-to-SPI bus interface needs to be adapted according to the read-write characteristics of a flash memory in a specific operation process. When a write data operation of a sector (sector) is executed on a flash memory, specific flash memory write enable (write enable), sector erase (sector erase), busy bit (busy bit) detection, a write instruction including flash memory address information, and the like need to be sent respectively, and specific flash memory physical address information generally needs to be added, so that the operation flow is complex and errors are prone to occur.
Therefore, there is a need to provide a timing controller and a timing control board to solve the problems of the prior art.
[ summary of the invention ]
In order to solve the above-mentioned problems, an object of the present disclosure is to provide a timing controller and a timing control board, which have certain flexibility and expandability and simplify the instruction operations of the inter-integrated circuit units.
To achieve the above objective, the present disclosure provides a timing controller, which includes a micro control unit, an inter-integrated circuit slave unit, and a serial peripheral interface master unit. The micro control unit is used for executing the following functions:
controlling the inter-integrated circuit slave unit to communicate with an external inter-integrated circuit master unit;
controlling the serial peripheral interface main unit to communicate with an external serial peripheral interface slave unit; and
controlling data conversion between the inter-integrated circuit slave unit and the serial peripheral interface master unit.
When the micro control unit receives a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit firstly sends a sector erasing instruction to the serial peripheral interface slave unit, sends a write-in instruction after write enabling, and performs data verification after the write-in is completed.
In one embodiment of the present disclosure, the inter-integrated circuit main unit is located in the power management chip.
In one embodiment of the present disclosure, the serial peripheral interface slave unit is located in the flash memory unit. The flash memory unit comprises a plurality of storage sectors. The storage sectors have respective physical addresses.
In one embodiment of the present disclosure, the power management chip is configured to communicate with the inter-integrated circuit slave unit of the timing controller through the inter-integrated circuit master unit to read data stored in the flash memory unit.
In one embodiment of the present disclosure, the mcu sends a busy bit message after receiving a write command from the ic master unit to the slave unit, and sends an exit busy bit message after data verification is completed before sending a sector erase command to the slave unit.
The disclosure also provides a timing control board, which comprises a timing controller, a power management chip and a flash memory unit. The time schedule controller comprises a micro control unit, an inner integrated circuit slave unit and a serial peripheral interface master unit. The micro control unit is used for executing the following functions:
controlling the inter-integrated circuit slave unit to communicate with the inter-integrated circuit master unit of the power management chip;
controlling the serial peripheral interface main unit to communicate with the serial peripheral interface slave unit of the flash memory unit; and
controlling data conversion between the inter-integrated circuit slave unit and the serial peripheral interface master unit.
When the micro control unit receives a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit firstly sends a sector erasing instruction to the serial peripheral interface slave unit, sends a write-in instruction after write enabling, and performs data verification after the write-in is completed.
In one embodiment of the present disclosure, the timing control board is located in a power management chip of the ic main unit.
In one embodiment of the present disclosure, the timing control board is disposed in the flash memory unit. The flash memory unit comprises a plurality of storage sectors. The storage sectors have respective physical addresses.
In one embodiment of the present disclosure, the timing control board is configured to read data stored in the flash memory unit by the power management chip communicating with the inter-integrated circuit slave unit of the timing controller through the inter-integrated circuit master unit.
In an embodiment of the disclosure, in the timing control board, the micro control unit sends a busy bit message after receiving a write command from the inter-integrated circuit master unit to the serial peripheral interface slave unit and before sending a sector erase command to the serial peripheral interface slave unit, and sends an exit busy bit message after completing data verification.
In the timing controller and the timing control board of the embodiment of the disclosure, when the micro control unit is used for receiving a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit firstly sends a sector erasing instruction to the serial peripheral interface slave unit, sends the write-in instruction after write enabling, and performs data verification after the write-in is completed. Therefore, the instruction of the inner integrated circuit unit can be simplified, the operations of write enabling, busy bit detection, sector erasing, data verification and the like can be effectively hidden for users, and the use is convenient.
In order to make the aforementioned and other aspects of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below:
[ description of the drawings ]
FIG. 1 is a schematic diagram of a timing control board according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram illustrating an instruction format of an inter-integrated circuit unit according to an embodiment of the present disclosure;
FIG. 3 is a flow chart illustrating a write command execution of an inter-IC cell according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating a connection between an inter-integrated circuit slave unit and an inter-integrated circuit master unit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating an example of a connection between a SPI master unit and a SPI slave unit according to an embodiment of the present disclosure; and
FIG. 6 is a flowchart illustrating a read instruction execution flow of an inter-integrated circuit cell according to an embodiment of the disclosure.
[ detailed description ] embodiments
In order to make the aforementioned and other objects, features and advantages of the present disclosure comprehensible, preferred embodiments accompanied with figures are described in detail below. Furthermore, directional phrases used in this disclosure, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure.
In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 1 and 3, the present disclosure provides a timing controller 100 including a micro control unit 110, an inter-integrated circuit slave unit 120, and a serial peripheral interface master unit 130. The micro control unit 110 is configured to perform the following functions:
controlling the inter-integrated circuit slave unit 120 to communicate with an external inter-integrated circuit master unit 220;
controlling the serial peripheral interface master unit 130 to communicate with an external serial peripheral interface slave unit 330; and
controls the data transfer between the inter-integrated circuit slave unit 120 and the serial peripheral interface master unit 130.
When the micro control unit 110 receives a write command from the inter-integrated circuit main unit 220 to the serial peripheral interface slave unit 330, it first sends a sector erase command to the serial peripheral interface slave unit 330, and sends a write command after write enable, and performs data verification after the write is completed.
In one embodiment of the present disclosure, the inter-integrated circuit main unit 220 is located in the power management chip 200.
In one embodiment of the present disclosure, the SPI slave unit 330 is located in the flash memory unit 300. The flash memory cell 300 includes a plurality of storage sectors 3S1, 3S2, 3S3, … 3 Sn. The storage sectors 3S1, 3S2, 3S3, … 3Sn have respective physical addresses.
Referring to fig. 1, in an embodiment of the present disclosure, the power management chip 200 is configured to communicate with the inter-integrated circuit slave unit 120 of the timing controller 100 through the inter-integrated circuit master unit 220 to read data stored in the flash memory unit 300.
In one embodiment of the present disclosure, the mcu 110 sends busy bit message after receiving the write command from the inter-ic master 220 to the spi slave 120 and before sending sector erase command to the spi slave 330, and sends quit busy bit message after data verification is completed.
In particular, referring to FIG. 2, the instruction format of the inter-IC unit is shown. The inter-integrated circuit main unit transmits a Start signal Start to Start communication. All of the ICs enter a data receiving mode after receiving the Start signal Start from the unit. Then, the inter-integrated circuit main unit transmits 7 bits in total of address of the communication target device and one bit of read or write R/W information. 1 denotes read and 0 denotes write. After the inter-integrated circuit slave unit receives the address, the inter-integrated circuit slave unit conforming to the address sends a bit of response Ack. The inter-integrated circuit main unit receiving the acknowledge Ack enters a receiving or outputting mode depending on its original read or write R/W information. The inter-IC slave unit may then issue an acknowledge Ack at the end of each byte transmission when transmitting data. Finally, the IC master sends out a Stop signal Stop when the transmission is finished.
Specifically, referring to FIGS. 2 and 3, the write command format for the inter-IC unit is shown. The inter-integrated circuit main unit 220 transmits a Start signal Start to Start communication. The inter-integrated circuit enters the receive data mode upon receiving the Start signal Start from the unit 120. Then, the inter-integrated circuit main unit 220 transmits 7 bits of address of the communication target device and one bit of write W information 0. After the inter-integrated circuit slave unit 120 receives the address, the inter-integrated circuit slave unit 120 conforming to the address sends a bit acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transmits the command code Cmd written to the flash memory unit 300. The write command code Cmd is, for example, 02H, to which the present disclosure is not limited. After detecting the interrupt, the mcu 110 waits for and receives the instruction code 02 h. After the instruction code is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 then transmits the address data Flash add of the Flash memory unit 300. After detecting the interrupt, the micro control unit 110 waits for and receives the address data Flash add of the Flash memory unit 300. After the address data is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transfers the data0, data 1, … data n to be written into the flash memory unit 300. Fig. 3 only illustrates data0 as an example, and the disclosure is not limited thereto. After detecting the interrupt, the mcu 110 waits for and receives the data0 to be written into the flash memory unit 300. Upon each byte of data received, the inter-integrated circuit slave unit 120 issues an acknowledge Ack and triggers an interrupt. The inter-integrated circuit master unit 220 receives the acknowledge Ack and then transmits the next data to be written into the flash memory unit 300. After detecting the interrupt, the mcu 110 waits for and reads the data and stores the data in the buffer. Such as dynamic random access memory. After all data transfer is completed, the inter-integrated circuit main unit 220 issues a Stop signal. The mcu 110 pulls up the busy signal busy to enter the busy state. The inter-integrated circuit main unit 220 waits for the completion of writing to the flash memory unit after detecting the busy signal busy.
Specifically, the mcu 110 sends a sector erase command and a write enable command Cmd to the spi slave unit 330 through the spi master unit 130. After the data is written, the mcu 110 reads back and compares the data through the spi master unit 130 to verify whether the written data is correct. Then, the mcu 110 lowers the busy signal busy to exit the busy state.
Specifically, referring to fig. 4, the inter-integrated circuit slave unit 120 is connected to the inter-integrated circuit master unit 220 in a manner shown in the figure, and the inter-integrated circuit bus communicates using a serial data line SDA and a serial clock line SCL.
Specifically, referring to fig. 5, the connection between the spi master 130 and the spi slave 330 is shown in the figure, and the spi bus uses four interfaces: serial clock line SCLK, master-to-slave incoming line MOSI, master-to-slave outgoing line MISO, and slave select line SS.
Specifically, referring to fig. 2 and 6, the read command format of the inter-integrated circuit unit is shown in fig. 2. The inter-integrated circuit main unit 220 transmits a Start signal Start to Start communication. The inter-integrated circuit enters the receive data mode upon receiving the Start signal Start from the unit 120. Then, the inter-integrated circuit main unit 220 transmits 7 bits of address of the communication target device and one bit of read R information 1. After the inter-integrated circuit slave unit 120 receives the address, the inter-integrated circuit slave unit 120 conforming to the address sends a bit acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transmits the command code Cmd read from the flash memory unit 300. The fetch command code Cmd is, for example, 0BH, but the disclosure is not limited thereto. After detecting the interrupt, the mcu 110 waits for and receives the command code 0 BH. After the instruction code is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 then transmits the address data Flash add of the Flash memory unit 300. After detecting the interrupt, the micro control unit 110 waits for and receives the address data Flash add. After the address data is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. The micro control unit 110 sends the read command code Cmd and the address data Flash add to the spi slave unit 330 through the spi master unit 130. The flash memory unit 300 reads and returns the data0, data 1, etc. in the address, which is only taken as an example in the present disclosure, but the present disclosure is not limited thereto.
After the data0 and data 1 are transmitted back to the mcu 110, the mcu 110 controls the asic to send a Start signal Start from the unit 120. The inter-integrated circuit main unit 220 enters the read mode after receiving the Start signal Start. The inter-integrated circuit slave unit 120 then issues its own address of 7 bits, one bit of read R information 1, and a acknowledge Ack and triggers an interrupt. When the mcu 110 detects an interrupt, it starts to transmit data0 from the slave 120 to the master 220 via the inter-ic. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 waits for and reads the data 0. The inter-integrated circuit main unit 220 transmits an acknowledge Ack every time a byte of data is received. After the mcu 110 detects the Ack, it transmits the next data to the asic main unit 220 via the asic slave unit 120. When the data is received, the inter-integrated circuit master unit 220 transmits an unacknowledged nAck and Stop signal Stop. The micro control unit 110 immediately stops reading data from the flash memory unit 300 after receiving the non-acknowledge nAck.
Referring to fig. 1, the present disclosure further provides a timing control board 1000 including a timing controller 100, a power management chip 200, and a flash memory unit 300. The timing controller 100 includes a micro control unit 110, an inter-integrated circuit slave unit 120, and a serial peripheral interface master unit 130. The micro control unit 100 is configured to perform the following functions:
controlling the inter-integrated circuit slave unit 120 to communicate with the inter-integrated circuit master unit 220 of the power management chip 200;
controlling the serial peripheral interface master unit 130 to communicate with the serial peripheral interface slave unit 330 of the flash memory unit 300; and
controls the data transfer between the inter-integrated circuit slave unit 120 and the serial peripheral interface master unit 130.
When the micro control unit 110 receives a write command from the inter-integrated circuit main unit 220 to the serial peripheral interface slave unit 330, it first sends a sector erase command to the serial peripheral interface slave unit 330, and sends a write command after write enable, and performs data verification after the write is completed.
In one embodiment of the present disclosure, the timing control board 1000 is provided, wherein the inter-integrated circuit main unit 120 is located in the power management chip 200.
In one embodiment of the present disclosure, the timing control board 1000 is provided, wherein the spi slave unit 330 is located in the flash memory unit 300. The flash memory cell 300 includes a plurality of storage sectors 3S1, 3S2, 3S3, … 3 Sn. The storage sectors 3S1, 3S2, 3S3, … 3Sn have respective physical addresses.
In one embodiment of the present disclosure, the timing control board 1000 is configured such that the power management chip 200 is configured to communicate with the inter-integrated circuit slave unit 120 of the timing controller 100 through the inter-integrated circuit master unit 220 to read data stored in the flash memory unit 300.
In one embodiment of the present disclosure, the timing control board 1000 is configured such that the mcu 110 sends a busy bit message after receiving a write command from the inter-ic master unit 220 to the slave unit 330, and sends an exit busy bit message after data verification is completed before sending a sector erase command to the slave unit 330.
In particular, referring to FIG. 2, the instruction format of the inter-IC unit is shown. The inter-integrated circuit main unit transmits a Start signal Start to Start communication. All of the ICs enter a data receiving mode after receiving the Start signal Start from the unit. Then, the inter-integrated circuit main unit transmits 7 bits in total of address of the communication target device and one bit of read or write R/W information. 1 denotes read and 0 denotes write. After the inter-integrated circuit slave unit receives the address, the inter-integrated circuit slave unit conforming to the address sends a bit of response Ack. The inter-integrated circuit main unit receiving the acknowledge Ack enters a receiving or outputting mode depending on its original read or write R/W information. The inter-IC slave unit may then issue an acknowledge Ack at the end of each byte transmission when transmitting data. Finally, the IC master sends out a Stop signal Stop when the transmission is finished.
Specifically, referring to FIGS. 2 and 3, the write command format for the inter-IC unit is shown. The inter-integrated circuit main unit 220 transmits a Start signal Start to Start communication. The inter-integrated circuit enters the receive data mode upon receiving the Start signal Start from the unit 120. Then, the inter-integrated circuit main unit 220 transmits 7 bits of address of the communication target device and one bit of write W information 0. After the inter-integrated circuit slave unit 120 receives the address, the inter-integrated circuit slave unit 120 conforming to the address sends a bit acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transmits the command code Cmd written to the flash memory unit 300. The write command code Cmd is, for example, 02H, to which the present disclosure is not limited. After detecting the interrupt, the mcu 110 waits for and receives the instruction code 02 h. After the instruction code is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 then transmits the address data Flash add of the Flash memory unit 300. After detecting the interrupt, the micro control unit 110 waits for and receives the address data Flash add of the Flash memory unit 300. After the address data is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transfers the data0, data 1, … data n to be written into the flash memory unit 300. Fig. 3 only illustrates data0 as an example, and the disclosure is not limited thereto. After detecting the interrupt, the mcu 110 waits for and receives the data0 to be written into the flash memory unit 300. Upon each byte of data received, the inter-integrated circuit slave unit 120 issues an acknowledge Ack and triggers an interrupt. The inter-integrated circuit master unit 220 receives the acknowledge Ack and then transmits the next data to be written into the flash memory unit 300. After detecting the interrupt, the mcu 110 waits for and reads the data and stores the data in the buffer. Such as dynamic random access memory. After all data transfer is completed, the inter-integrated circuit main unit 220 issues a Stop signal. The mcu 110 pulls up the busy signal busy to enter the busy state. The inter-integrated circuit main unit 220 waits for the completion of writing to the flash memory unit after detecting the busy signal busy.
Specifically, the mcu 110 sends a sector erase command and a write enable command Cmd to the spi slave unit 330 through the spi master unit 130. After the data is written, the mcu 110 reads back and compares the data through the spi master unit 130 to verify whether the written data is correct. Then, the mcu 110 lowers the busy signal busy to exit the busy state.
Specifically, referring to fig. 4, the inter-integrated circuit slave unit 120 is connected to the inter-integrated circuit master unit 220 in a manner shown in the figure, and the inter-integrated circuit bus communicates using a serial data line SDA and a serial clock line SCL.
Specifically, referring to fig. 5, the connection between the spi master 130 and the spi slave 330 is shown in the figure, and the spi bus uses four interfaces: serial clock line SCLK, master-to-slave incoming line MOSI, master-to-slave outgoing line MISO, and slave select line SS.
Specifically, referring to fig. 2 and 6, the read command format of the inter-integrated circuit unit is shown in fig. 2. The inter-integrated circuit main unit 220 transmits a Start signal Start to Start communication. The inter-integrated circuit enters the receive data mode upon receiving the Start signal Start from the unit 120. Then, the inter-integrated circuit main unit 220 transmits 7 bits of address of the communication target device and one bit of read R information 1. After the inter-integrated circuit slave unit 120 receives the address, the inter-integrated circuit slave unit 120 conforming to the address sends a bit acknowledge Ack and triggers an interrupt. The inter-integrated circuit main unit 220 receives the acknowledge Ack and then transmits the command code Cmd read from the flash memory unit 300. The fetch command code Cmd is, for example, 0BH, but the disclosure is not limited thereto. After detecting the interrupt, the mcu 110 waits for and receives the command code 0 BH. After the instruction code is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 then transmits the address data Flash add of the Flash memory unit 300. After detecting the interrupt, the micro control unit 110 waits for and receives the address data Flash add. After the address data is transferred, the inter-IC slave unit 120 sends an acknowledge Ack and triggers an interrupt. The micro control unit 110 sends the read command code Cmd and the address data Flash add to the spi slave unit 330 through the spi master unit 130. The flash memory unit 300 reads and returns the data0, data 1, etc. in the address, which is only taken as an example in the present disclosure, but the present disclosure is not limited thereto.
After the data0 and data 1 are transmitted back to the mcu 110, the mcu 110 controls the asic to send a Start signal Start from the unit 120. The inter-integrated circuit main unit 220 enters the read mode after receiving the Start signal Start. The inter-integrated circuit slave unit 120 then issues its own address of 7 bits, one bit of read R information 1, and a acknowledge Ack and triggers an interrupt. When the mcu 110 detects an interrupt, it starts to transmit data0 from the slave 120 to the master 220 via the inter-ic. After receiving the acknowledge Ack, the inter-integrated circuit main unit 220 waits for and reads the data 0. The inter-integrated circuit main unit 220 transmits an acknowledge Ack every time a byte of data is received. After the mcu 110 detects the Ack, it transmits the next data to the asic main unit 220 via the asic slave unit 120. When the data is received, the inter-integrated circuit master unit 220 transmits an unacknowledged nAck and Stop signal Stop. The micro control unit 110 immediately stops reading data from the flash memory unit 300 after receiving the non-acknowledge nAck.
In the timing controller and the timing control board of the embodiment of the disclosure, when the micro control unit is used for receiving a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit firstly sends a sector erasing instruction to the serial peripheral interface slave unit, sends the write-in instruction after write enabling, and performs data verification after the write-in is completed. Therefore, the instruction of the inner integrated circuit unit can be simplified, the operations of write enabling, busy bit detection, sector erasing, data verification and the like can be effectively hidden for users, and the use is convenient.
Although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification. In addition, while a particular feature of the specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.
The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and refinements may be made by those skilled in the art without departing from the principle of the present disclosure, and these modifications and refinements should also be construed as the protection scope of the present disclosure.
Claims (10)
1. A timing controller, comprising a micro control unit, an inter-integrated circuit slave unit, and a serial peripheral interface master unit, wherein the micro control unit is configured to:
controlling the inter-integrated circuit slave unit to communicate with an external inter-integrated circuit master unit;
controlling the serial peripheral interface main unit to communicate with an external serial peripheral interface slave unit; and
controlling data conversion between the inter-integrated circuit slave unit and the serial peripheral interface master unit;
when the micro control unit receives a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit is used for sending a sector erasing instruction and a write enable to the serial peripheral interface slave unit, then the micro control unit sends the write-in instruction, and after the write-in is completed, the micro control unit performs data verification.
2. The timing controller of claim 1, wherein the inter-integrated circuit master unit is located in a power management chip.
3. The timing controller of claim 2, wherein the serial peripheral interface slave unit is located in a flash memory unit, the flash memory unit comprising a plurality of storage sectors, the storage sectors having respective physical addresses.
4. The timing controller of claim 3, wherein the power management chip is configured to communicate with the inter-integrated circuit slave unit of the timing controller via the inter-integrated circuit master unit to read data stored in the flash memory unit.
5. The timing controller of claim 1, wherein the mcu sends busy bit messages after receiving a write command from the ic master to the spi slave and before sending a sector erase command to the spi slave, and sends exit busy bit messages after data verification is complete.
6. The time sequence control board is characterized by comprising a time sequence controller, a power management chip and a flash memory unit, wherein the time sequence controller comprises a micro control unit, an internal integrated circuit slave unit and a serial peripheral interface main unit, and the micro control unit is used for executing the following functions:
controlling the inter-integrated circuit slave unit to communicate with the inter-integrated circuit master unit of the power management chip;
controlling the serial peripheral interface main unit to communicate with the serial peripheral interface slave unit of the flash memory unit; and
controlling data conversion between the inter-integrated circuit slave unit and the serial peripheral interface master unit;
when the micro control unit receives a write-in instruction of the internal integrated circuit main unit to the serial peripheral interface slave unit, the micro control unit is used for sending a sector erasing instruction and a write enable to the serial peripheral interface slave unit, then the micro control unit sends the write-in instruction, and after the write-in is completed, the micro control unit performs data verification.
7. The timing control board of claim 6, wherein the inter-integrated circuit master unit is located within a power management chip.
8. The timing control board of claim 7, wherein the serial peripheral interface slave unit is located in a flash memory unit, the flash memory unit comprising a plurality of storage sectors, the storage sectors having respective physical addresses.
9. The timing control board of claim 8, wherein the power management chip is configured to communicate with the inter-integrated circuit slave unit of the timing controller via the inter-integrated circuit master unit to read data stored in the flash memory unit.
10. The timing control board of claim 6, wherein the micro control unit sends a busy bit message after receiving a write command from the inter-integrated circuit master unit to the serial peripheral interface slave unit, before sending a sector erase command to the serial peripheral interface slave unit, and sends an exit busy bit message after data verification is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910483112.XA CN110164394B (en) | 2019-06-04 | 2019-06-04 | Time sequence controller and time sequence control board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910483112.XA CN110164394B (en) | 2019-06-04 | 2019-06-04 | Time sequence controller and time sequence control board |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090014774A (en) * | 2007-08-07 | 2009-02-11 | (주) 라모스테크놀러지 | Apparatus for controlling nand flash memory |
| CN103035294A (en) * | 2011-09-28 | 2013-04-10 | 三星电子株式会社 | Method of reading data from a non-volatile memory and devices and systems to implement same |
| CN103729143A (en) * | 2012-10-12 | 2014-04-16 | 苏州工业园区新宏博通讯科技有限公司 | Data safety method for electric energy data storage of multi-path electricity meter |
| CN104951412A (en) * | 2015-06-06 | 2015-09-30 | 华为技术有限公司 | Storage device capable of being accessed through memory bus |
| CN105975240A (en) * | 2016-07-01 | 2016-09-28 | 深圳市华星光电技术有限公司 | Data storage device, method for preventing data failure thereof and time schedule controller |
| CN106406962A (en) * | 2016-09-29 | 2017-02-15 | 四川东方电气自动控制工程有限公司 | Wind power generation controller failed remote upgrade recovery method based on ARM |
| CN108198536A (en) * | 2017-12-29 | 2018-06-22 | 深圳市华星光电技术有限公司 | Voltage calibration method and calibration system based on sequence controller |
| CN109669888A (en) * | 2018-11-06 | 2019-04-23 | 电子科技大学 | A kind of configurable and efficient embedded Nor-Flash controller and control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102023956B (en) * | 2009-09-23 | 2012-07-25 | 上海摩波彼克半导体有限公司 | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method |
| JP5820830B2 (en) * | 2013-01-31 | 2015-11-24 | 京セラドキュメントソリューションズ株式会社 | Storage control device, electronic apparatus, storage control program, and storage control method |
-
2019
- 2019-06-04 CN CN201910483112.XA patent/CN110164394B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090014774A (en) * | 2007-08-07 | 2009-02-11 | (주) 라모스테크놀러지 | Apparatus for controlling nand flash memory |
| CN103035294A (en) * | 2011-09-28 | 2013-04-10 | 三星电子株式会社 | Method of reading data from a non-volatile memory and devices and systems to implement same |
| CN103729143A (en) * | 2012-10-12 | 2014-04-16 | 苏州工业园区新宏博通讯科技有限公司 | Data safety method for electric energy data storage of multi-path electricity meter |
| CN104951412A (en) * | 2015-06-06 | 2015-09-30 | 华为技术有限公司 | Storage device capable of being accessed through memory bus |
| CN105975240A (en) * | 2016-07-01 | 2016-09-28 | 深圳市华星光电技术有限公司 | Data storage device, method for preventing data failure thereof and time schedule controller |
| CN106406962A (en) * | 2016-09-29 | 2017-02-15 | 四川东方电气自动控制工程有限公司 | Wind power generation controller failed remote upgrade recovery method based on ARM |
| CN108198536A (en) * | 2017-12-29 | 2018-06-22 | 深圳市华星光电技术有限公司 | Voltage calibration method and calibration system based on sequence controller |
| CN109669888A (en) * | 2018-11-06 | 2019-04-23 | 电子科技大学 | A kind of configurable and efficient embedded Nor-Flash controller and control method |
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