CN106713808A - Digital image data format conversion circuit and realization method thereof - Google Patents
Digital image data format conversion circuit and realization method thereof Download PDFInfo
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- CN106713808A CN106713808A CN201611069674.2A CN201611069674A CN106713808A CN 106713808 A CN106713808 A CN 106713808A CN 201611069674 A CN201611069674 A CN 201611069674A CN 106713808 A CN106713808 A CN 106713808A
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- address decoding
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 title abstract description 9
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000003139 buffering effect Effects 0.000 claims description 6
- 235000018734 Sambucus australis Nutrition 0.000 claims description 2
- 244000180577 Sambucus australis Species 0.000 claims description 2
- OGFXBIXJCWAUCH-UHFFFAOYSA-N meso-secoisolariciresinol Natural products C1=2C=C(O)C(OC)=CC=2CC(CO)C(CO)C1C1=CC=C(O)C(OC)=C1 OGFXBIXJCWAUCH-UHFFFAOYSA-N 0.000 claims description 2
- 238000004321 preservation Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 28
- 238000003331 infrared imaging Methods 0.000 description 4
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 2
- 101150046378 RAM1 gene Proteins 0.000 description 2
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 208000026097 Factitious disease Diseases 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a digital image data format conversion circuit and a realization method thereof. The digital image data format conversion circuit comprises a dual-port RAM, a sequential control circuit and an address decoding circuit which are sequentially connected, wherein the address decoding circuit is further connected with the dual-port RAM, the other end of the dual-port RAM is used for connecting with a data source, and the sequential control circuit is used for connecting with a film resistor array driving system. The digital image data format conversion circuit is advantaged in that real-time demands for driving a film resistor array to work can be satisfied, and high flexibility is realized.
Description
Technical field
The invention belongs to Digital image technology field, and in particular to a kind of digital image data format change-over circuit and realization
Method.
Background technology
Film resistor battle array is the special electronic device of a kind of high accuracy that can produce thermal image, large-scale integrated.It one
As together constitute with a kind of IR Scene with optical system, Electric Drive System, image computer generation system and mechanical system etc.
Generation system.The system is an important composition subsystem of Hardware-in-the-loop simu- lation system, is mainly used in infrared imaging system
In the test of system and emulation, such as guided missile position marker, infrared imaging alarm device and infrared imaging observer.At present, foreign countries are to this
The design of device, production and using in depth being studied, there are Related product in Honeywell the and SBIR companies in such as U.S.
It is seen in open report.US military has successfully been built several IR Scenes with film resistor battle array as core component and has been produced
Raw system, and put into test, emulation and the assessment of polytype infrared imaging guidance armament systems.
The view data for driving film resistor battle array work is provided by image generation computer, usual computer display card life
Into view data be sequential storage carried out with the driving form of general purpose display and to use, i.e. the lower-left angular data of image is
The initial data for storing and using, then by point by point scanning mode is arranged line by line from left to right, from bottom to top.China designs and raw
The view data order that the film resistor battle array of product is used when driving is inconsistent with general purpose display view data scanning sequency, is
Mode is scanned by column by a kind of film resistor battle array customized Multipoint synchronous interlacing of designer, that is, when driving film resistor battle array work
By column scan, in each driving timeticks, while being spaced the multiple film resistor pixels for driving a row, each column scan is driven
It is dynamic to be completed using several driving timeticks.Therefore, in order that film resistor can correctly work according to the view data of generation,
Show desired thermal image, it is necessary to corresponding data are carried out to the view data that image generation computer is generated when driving and is used
Order is changed, that is, carry out the conversion of digital image data format.
Current existing format conversion method is that output data is completed in image generation computer using software engineering is suitable
The conversion of sequence, its main thought is to pass through software computational methods to each frame image data of computer picture adapter generation
Data storing order is rearranged, so as to meet the call format that film resistor battle array drives.Software format conversion method
Shortcoming be to expend the substantial amounts of calculating time, it is impossible to meet drive film resistor battle array work real-time demand.
The content of the invention
The technical problems to be solved by the invention are for above-mentioned the deficiencies in the prior art, there is provided it is thin that one kind meets driving
The real-time demand and flexibility digital image data format change-over circuit high and implementation method of film resistance battle array work.
In order to solve the above technical problems, the technical solution adopted by the present invention is, including be sequentially connected connect two-port RAM,
Sequential control circuit and address decoding circuitry, address decoding circuitry are also connected with two-port RAM；The other end of two-port RAM
For being connected with data source, sequential control circuit is used to be connected with film resistor battle array drive system.
The digital image data format change-over circuit receives the data of data source by two-port RAM, enters row buffering preservation,
And under the control of sequential control circuit and address decoding circuitry, finally to film resistor battle array drive system output driving thin-film electro
Resistance battle array normally shows the data of required distributing order；Above-mentioned two-port RAM is used to receive the data of data source, enters row buffering guarantor
Deposit, and receive the signal that address decoding circuitry and sequential control circuit send.Above-mentioned sequential control circuit is used for address decoding
Circuit transmission allocation index signal, is additionally operable to transmission data read-out control signal in two-port RAM, and according to required arrangement
Mode reads the data in two-port RAM.Address above mentioned decoding circuit is used to receive the allocation index of sequential control circuit transmission
Signal, produces the address signal needed for driving the normal display of film resistor battle array, and address signal is transferred into two-port RAM.
Further, the sequential control circuit and address decoding circuitry collaboration respectively to sent in two-port RAM data read
Go out control signal and address signal is：Continuous by column to read between multi-column data, in each column data, spaced rows read.”
Further, in each column data, interval line number is 8n, and wherein n is 1 or 2.
Further, the sequential control circuit and address decoding circuitry are made up of a fpga chip.
The invention discloses a kind of above-mentioned implementation method of digital image data format change-over circuit, the method is as follows：Should
To address decoding circuitry OPADD index signal, address decoding circuitry receives allocation index signal to sequential control circuit, and produces
It is raw to drive film resistor battle array address signal normally needed for display, it is transferred to two-port RAM；The sequential control circuit is to both-end
Transmitted in mouth RAM and read data controlling signal, the data in two-port RAM are read according to required arrangement mode, and will reading
Data be transferred to film resistor battle array drive system.
A kind of digital image data format change-over circuit of the present invention and implementation method have the following advantages that：1. SECO is electric
Road, address decoding circuitry and two-port RAM cooperate so that the data writing process of data source and film resistor battle array drivetrain
The data read-out process coordinating work of system, ensure that the reliability and real-time of image data format conversion well.2. use
Address decoding circuitry combines decoding and produces by the signal that combinational logic is produced to sequential control circuit, with reliability very high
And real-time；Meanwhile, for different film resistors battle array, only need to change sequential control circuit and address decoding circuitry can just realize
Image data format translation function, with flexibility very high.
Brief description of the drawings
Fig. 1 is a kind of structural representation of digital image data format change-over circuit in the present invention；
Wherein：1. two-port RAM；2. address decoding circuitry；3. sequential control circuit；4. data source；5. film resistor battle array
Drive system.
Specific embodiment
A kind of digital image data format change-over circuit of the present invention, as shown in figure 1, including being sequentially connected the dual-port for connecing
RAM1, sequential control circuit 3 and address decoding circuitry 2, the address decoding circuitry 2 are also connected with two-port RAM 1；The both-end
The other end of mouth RAM1 is used to be connected with data source 4, and the sequential control circuit 3 is used for and the film resistor battle array phase of drive system 5
Connection.Sequential control circuit 3 and address decoding circuitry 2 are made up of a fpga chip.
The digital image data format change-over circuit receives the data of data source 4 by two-port RAM 1, enters row buffering guarantor
Deposit, and under the control of sequential control circuit 3 and address decoding circuitry 2, finally to the film resistor battle array output driving of drive system 5
The data of distributing order needed for the normal display of film resistor battle array；Above-mentioned two-port RAM 1 is used to receive the data of data source 4, enters
Row buffering is preserved, and receives the signal that address decoding circuitry 2 and sequential control circuit 3 send.
Above-mentioned sequential control circuit 3 is used to transmit allocation index signal to address decoding circuitry 2, is additionally operable to dual-port
Data read-out control signal is transmitted in RAM 1, and the data in two-port RAM 1 are read according to required arrangement mode.It is above-mentioned
Address decoding circuitry 2 is used to receive the allocation index signal of the transmission of sequential control circuit 3, produces and drives film resistor battle array normal aobvious
Show required address signal, and address signal is transferred to two-port RAM 1.
A kind of above-mentioned digital image data format change-over circuit, sequential control circuit 3 and the collaboration difference of address decoding circuitry 2
To sending data read-out control signal in two-port RAM 1 and address signal is：It is continuous by column to read between multi-column data, often
In one column data, spaced rows read.In each column data, interval line number is 8n, and wherein n is 1 or 2.
The invention discloses a kind of implementation method of above-mentioned digital image data format change-over circuit, the method is as follows：
The sequential control circuit 3 receives allocation index signal to the OPADD index signal of address decoding circuitry 2, address decoding circuitry 2,
And the address signal for driving the normal display of film resistor battle array required is produced, it is transferred to two-port RAM 1；The sequential control circuit 3
Data controlling signal is read to being transmitted in two-port RAM 1, the number in two-port RAM 1 is read according to required arrangement mode
According to, and the data of reading are transferred to film resistor battle array drive system 5.
The present invention is, as medium, turning for digital image data format to be completed by time series stereodata with two-port RAM 1
Change.It is of the invention to be realized by hardware completely, is not limited by software systems, the characteristics of with simple, reliability, stabilization.
Embodiment
The present embodiment specifically describes the process that explanation address above mentioned signal is produced by taking 128 × 128 film resistors battle array as an example.
128 × 128 film resistors battle array is continuous per the control of D/A signals all the way by 16 road D/A signal parallel drive controls
8 rows.Driving the view data order of 128 × 128 film resistors battle array is：Be first the 1st arrange the 1st row, the 1st arrange the 9th row, the 1st row
17th row ..., the 1st arrange the 120th row, the 1st arrange the 2nd row, the 1st arrange the 10th row ..., the 1st arrange the 121st row ..., the 1st arrange the 128th
Row, secondly the row ... of secondary series the 1st, is finally the 128th to arrange the 128th row.Sequential control circuit 3 is according to reference clock signal, control
One 14 digit counter, counter sequential counting since 0, counter gives address decoding circuitry 2.Address decoding
Circuit 2, according to Boolean logic algebraic method, is input with counter, is produced for the extraction figure from two-port RAM 1
As the address signal of data, the address signal is met between multi-column data, continuous by column to read, in each column data, spaced rows
Read.
Claims (5)
1. a kind of digital image data format change-over circuit, it is characterised in that including be sequentially connected the two-port RAM for connecing (1), when
Sequence control circuit (3) and address decoding circuitry (2), the address decoding circuitry (2) are also connected with two-port RAM (1)；It is described
The other end of two-port RAM (1) be used for be connected with data source (4), the sequential control circuit (3) for film resistor battle array
Drive system (5) is connected；
The digital image data format change-over circuit receives the data of data source (4) by two-port RAM (1), enters row buffering guarantor
Deposit, and under the control of sequential control circuit (3) and address decoding circuitry (2), it is finally defeated to film resistor battle array drive system (5)
Go out to drive the data of distributing order needed for the normal display of film resistor battle array；
The two-port RAM (1) enters row buffering preservation, and receive address decoding circuitry for receiving the data of data source (4)
And sequential control circuit (3 signals for sending (2)；
The sequential control circuit (3) is additionally operable to dual-port for transmitting allocation index signal to address decoding circuitry (2)
Transmission data read-out control signal in RAM (1), and read the data in two-port RAM (1) according to required arrangement mode；
The address decoding circuitry (2) produces and drives film for receiving the allocation index signal that sequential control circuit (3) sends
Resistor Array Projector address signal normally needed for display, and address signal is transferred to two-port RAM (1).
2. according to a kind of digital image data format change-over circuit described in claim 1, it is characterised in that the SECO
Circuit (3) and address decoding circuitry (2) collaboration are believed to sending data read-out control signal and address in two-port RAM (1) respectively
Number it is：Continuous by column to read between multi-column data, in each column data, spaced rows read.
3. according to a kind of digital image data format change-over circuit described in claim 2, it is characterised in that each column data
In, interval line number is 8n, and wherein n is 1 or 2.
4. according to a kind of digital image data format change-over circuit described in claim 1,2 or 3, it is characterised in that when described
Sequence control circuit (3) and address decoding circuitry (2) are made up of a fpga chip.
5. according to a kind of implementation method of the digital image data format change-over circuit any one of Claims 1 to 4, its
It is characterised by, the method is as follows：The sequential control circuit (3) is to address decoding circuitry (2) OPADD index signal, address
Decoding circuit (2) receives allocation index signal, and produces the address signal needed for driving the normal display of film resistor battle array, is transferred to
Two-port RAM (1)；The sequential control circuit (3) reads data controlling signal to transmission in two-port RAM (1), according to required
Arrangement mode read data in two-port RAM (1), and the data of reading are transferred to film resistor battle array drive system (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611069674.2A CN106713808A (en) | 2016-11-29 | 2016-11-29 | Digital image data format conversion circuit and realization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611069674.2A CN106713808A (en) | 2016-11-29 | 2016-11-29 | Digital image data format conversion circuit and realization method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN106713808A true CN106713808A (en) | 2017-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611069674.2A Pending CN106713808A (en) | 2016-11-29 | 2016-11-29 | Digital image data format conversion circuit and realization method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110136666A (en) * | 2019-05-05 | 2019-08-16 | 深圳市华星光电技术有限公司 | Sequence controller and timing control panel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN206542515U (en) * | 2016-11-29 | 2017-10-03 | 西安天圆光电科技有限公司 | A kind of digital image data format change-over circuit |
-
2016
- 2016-11-29 CN CN201611069674.2A patent/CN106713808A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN206542515U (en) * | 2016-11-29 | 2017-10-03 | 西安天圆光电科技有限公司 | A kind of digital image data format change-over circuit |
Non-Patent Citations (3)
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|---|
| 李睿等: "高帧频MOS电阻阵红外成像目标模拟器实时控制研究", 《航空兵器》 * |
| 黄勇等: "256×256元MOS电阻阵驱动方法研究", 《航空兵器》 * |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110136666A (en) * | 2019-05-05 | 2019-08-16 | 深圳市华星光电技术有限公司 | Sequence controller and timing control panel |
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Application publication date: 20170524 |
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| RJ01 | Rejection of invention patent application after publication |