CN110121237B

CN110121237B - Circuit board structure and manufacturing method thereof

Info

Publication number: CN110121237B
Application number: CN201810121300.3A
Authority: CN
Inventors: 谢育忠; 林纬廸; 简俊贤; 陈裕华
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2018-02-07
Filing date: 2018-02-07
Publication date: 2020-05-26
Anticipated expiration: 2038-02-07
Also published as: CN110121237A

Abstract

A circuit board structure and a manufacturing method thereof. The circuit board structure comprises an insulating substrate, a first circuit layer, a capacitor dielectric layer, a first dielectric layer and a second circuit layer. The insulating substrate is provided with a plurality of first through holes and second through holes. The first circuit layer comprises a first capacitor electrode, an inductance circuit, a plurality of first conductive through holes and a second conductive through hole. The inductance circuit and the first conductive via penetrate through the insulating substrate in a spiral manner to define a three-dimensional inductance. The third via of the first dielectric layer penetrates through the first dielectric layer and is located in the second conductive via. The second conductive via and the third conductive via define a coaxial via. The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode of the second circuit layer define a capacitor.

Description

Circuit board structure and manufacturing method thereof

Technical Field

The present invention relates to circuit board structures and methods for manufacturing the same, and particularly to a circuit board structure with diversified applications and a method for manufacturing the same.

Background

Today, multi-layer circuit boards having at least two circuit layers usually have conductive via structures to electrically connect the circuit layers. Most of the existing methods for forming the conductive through hole structure firstly adopt mechanical drilling or laser drilling to form the through hole, and then complete the conductive through hole structure through a through hole electroplating process. However, the space in the through holes is an invalid area, which not only easily results in space waste, but also cannot increase the wiring density and provide better design flexibility.

Disclosure of Invention

The invention provides a circuit board structure which has better design flexibility, thinner overall thickness and diversified application.

The invention also provides a manufacturing method of the circuit board structure, which is used for manufacturing the circuit board structure.

The invention relates to a circuit board structure, which comprises an insulating substrate, a first circuit layer, a capacitance dielectric layer, a first dielectric layer and a second circuit layer. The insulating substrate is provided with a first surface and a second surface which are opposite to each other, and a plurality of first through holes and second through holes which connect the first surface and the second surface. The first circuit layer is arranged on the insulating base material and exposes part of the first surface and the second surface. The first circuit layer comprises a first capacitor electrode, an inductance circuit, a plurality of first conductive through holes and a plurality of second conductive through holes. The first capacitor electrode is located on the first surface. The inductance circuit is located on the first surface and the second surface. The first conductive via covers an inner wall of the first via. The second conductive via covers an inner wall of the second via. The inductance circuit and the first conductive via penetrate through the insulating substrate in a spiral manner to define a three-dimensional inductance. The capacitor dielectric layer is configured on the part of the first capacitor electrode. The first dielectric layer covers the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and fills the first conductive through hole and the second conductive through hole. The first dielectric layer is provided with a third through hole, a first blind hole and a first opening. The third via penetrates through the first dielectric layer and is located in the second conductive via. The first opening exposes the capacitor dielectric layer. The first blind via exposes a portion of the first circuit layer. The second circuit layer is configured on the first dielectric layer and comprises a second circuit, a third conductive through hole, a first conductive blind hole and a second capacitor electrode. The second circuit is disposed on a portion of the first dielectric layer. The third conductive via covers an inner wall of the third via. The first conductive blind hole is filled in the first blind hole and is connected with the first circuit layer and the second circuit layer. The second capacitor electrode fills the first opening. The second conductive via and the third conductive via define a coaxial via. The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor.

In an embodiment of the invention, the circuit board structure further includes a second dielectric layer and a third circuit layer. The second dielectric layer is configured on the second circuit layer, covers the second circuit layer and fills the third conductive through hole. The second dielectric layer is provided with a plurality of second blind holes, and part of the second circuit layer is exposed out of the second blind holes. The third circuit layer is disposed on a portion of the second dielectric layer and fills the second blind holes, wherein the third circuit layer is electrically connected to the second circuit layer.

In an embodiment of the invention, the circuit board structure further includes a solder mask layer disposed on the second dielectric layer, covering the second dielectric layer, and exposing a portion of the third circuit layer to define at least one pad.

In an embodiment of the invention, the circuit board structure further includes a seed layer disposed between the third circuit layer and the second dielectric layer.

In an embodiment of the invention, the circuit board structure further includes a seed layer disposed between the second circuit layer and the first dielectric layer.

The manufacturing method of the circuit board structure comprises the following steps. An insulating substrate is provided. The insulating substrate is provided with a first surface and a second surface which are opposite to each other, and a plurality of first through holes and second through holes which connect the first surface and the second surface. A first circuit layer is formed on the insulating substrate. The first circuit layer exposes a part of the first surface and the second surface, and includes a first capacitor electrode, an inductor circuit, a plurality of first conductive through holes and a plurality of second conductive through holes. The first capacitor electrode is located on the first surface. The inductance circuit is located on the first surface and the second surface. The first conductive via covers an inner wall of the first via. The second conductive via covers an inner wall of the second via. The inductance circuit and the first conductive via penetrate through the insulating substrate in a spiral manner to define a three-dimensional inductance. A capacitor dielectric layer is formed on a portion of the first capacitor electrode. The first dielectric layer is pressed on the first circuit layer. The first dielectric layer covers the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and fills the first through hole and the second through hole. A third via, a first blind via and a first opening are formed in the first dielectric layer. The third via penetrates through the first dielectric layer and is located in the second conductive via. The first opening exposes the capacitor dielectric layer. The first blind via exposes a portion of the first circuit layer. Forming a second circuit layer on the first dielectric layer. The second circuit layer covers part of the inner walls of the first dielectric layer and the third through hole and fills the first blind hole and the first opening. The second circuit layer comprises a second circuit, a third conductive through hole, a first conductive blind hole and a second capacitor electrode. The second circuit is disposed on a portion of the first dielectric layer. The third conductive via covers an inner wall of the third via. The first conductive blind hole is filled in the first blind hole and is connected with the first circuit layer and the second circuit layer. The second capacitor electrode fills the first opening. The second conductive via and the third conductive via define a coaxial via. The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor.

In an embodiment of the invention, the method for manufacturing the circuit board structure further includes: forming a second dielectric layer on the second circuit layer. The second dielectric layer covers the second circuit layer and fills the third through hole. And forming a plurality of second blind holes on the second dielectric layer, wherein the second blind holes expose part of the second circuit layer. And forming a third circuit layer on part of the second dielectric layer and filling the second blind holes, wherein the third circuit layer is electrically connected with the second circuit layer.

In an embodiment of the invention, the method for manufacturing the circuit board structure further includes forming a solder mask layer on the second dielectric layer. The solder mask layer covers the second dielectric layer and exposes the third circuit layer to define at least one pad.

In an embodiment of the invention, the method for manufacturing the circuit board structure further includes forming a seed layer between the third circuit layer and the second dielectric layer.

In an embodiment of the invention, the method for manufacturing a circuit board structure further includes forming a seed layer between the second circuit layer and the first dielectric layer.

Based on the above, in the design of the circuit board structure of the invention, the second conductive through hole covers the inner wall of the second through hole, the third through hole penetrates through the first dielectric layer and is located in the second conductive through hole, and the third conductive through hole covers the inner wall of the third through hole, wherein the second conductive through hole and the third conductive through hole define a coaxial through hole. That is, the circuit board structure of the present invention can effectively utilize the space in the second through hole to manufacture the coaxial through hole suitable for high frequency communication, and has better design flexibility. Moreover, the circuit board structure of the invention simultaneously has three structural elements with different characteristics, such as a three-dimensional inductor, a coaxial through hole, a capacitor and the like, can be applied in a diversified way, and has thinner integral thickness. In addition, in the manufacturing method of the circuit board structure, when the second circuit layer is formed, the coaxial through hole and the capacitor are defined at the same time. That is, in the same process step, the coaxial via and the capacitor are simultaneously fabricated, thereby effectively reducing the process time and the production cost.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1J are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention.

Fig. 2A is a schematic top view of the three-dimensional inductor of the circuit board structure of fig. 1B.

Fig. 2B is a schematic perspective view of the solid inductor of fig. 2A.

Description of the symbols:

10: a three-dimensional inductor;

20: a coaxial through hole;

30: a capacitor;

100: a circuit board structure;

110: an insulating base material;

112: a first surface;

114: a second surface;

116: a first through hole;

118: a second through hole;

120: a first circuit layer;

122: a first capacitance electrode;

124: an inductive circuit;

126: a first conductive via;

128: a second conductive via;

130: a capacitor dielectric layer;

140: a first dielectric layer;

142: a third through hole;

144: a first opening;

146: a first blind hole;

150: a second circuit layer;

152: a second line;

154: a third conductive via;

156: a first conductive blind hole;

158: a second capacitance electrode;

160: a second dielectric layer;

162: a second blind hole;

170: a third circuit layer;

172: a third line;

174: a second conductive post;

180: a solder mask layer;

s1, S2: a seed layer;

p: and a pad.

Detailed Description

Fig. 1A to fig. 1J are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention. Fig. 2A is a schematic top view of the three-dimensional inductor of the circuit board structure of fig. 1B. Fig. 2B is a schematic perspective view of the solid inductor of fig. 2A. Referring to fig. 1A and fig. 2A, firstly, an insulating substrate 110 is provided, wherein the insulating substrate 110 is, for example, a glass substrate, a ceramic substrate, a polymer glass fiber composite substrate, a Polyimide (PI) glass fiber composite substrate, a dielectric layer with a single layer or multiple layers of dielectric materials, and a single layer or multiple layers of circuit board with an outer layer having a dielectric material and an inner layer embedded with a circuit, but the invention is not limited thereto. Here, the insulating substrate 110 has a first surface 112 and a second surface 114 opposite to each other, and a plurality of first through holes 116 and second through holes 118 connecting the first surface 112 and the second surface 114.

Next, referring to fig. 1B, fig. 2A and fig. 2B, a first circuit layer 120 is formed on the insulating substrate 110. The first circuit layer 120 exposes a portion of the first surface 112 and a portion of the second surface 114 of the insulating substrate 110, and includes a first capacitor electrode 122, an inductor circuit 124, a plurality of first conductive vias 126, and a second conductive via 128. That is, the first circuit layer 120 is a patterned circuit layer. The first capacitor electrode 122 is disposed on the first surface 112, and the inductor 124 is disposed on the first surface 112 and the second surface 114. The first conductive via 126 covers the inner wall of the first via 116 and the second conductive via 128 covers the inner wall of the second via 118. In particular, the inductance circuit 124 and the first conductive via 126 are spirally formed through the insulating substrate 110 to define the three-dimensional inductor 10. Here, the use of the insulating substrate 110 can preferably maintain the three-dimensional inductor 10.

Next, referring to fig. 1C, a capacitor dielectric layer 130 is formed on a portion of the first capacitor electrode 122. Here, the capacitor dielectric layer 130 covers only a portion of the first circuit layer 120, wherein the material of the capacitor dielectric layer 130 includes aluminum oxide (Al)₂O₃) Aluminum nitride (aluminum nitride; AlN), Silicon oxide (Silicon oxide; SiO 2₂) Silicon nitride (Silicon nitride; si₃N₄) Hafnium oxide (Hafnium dioxide; HfO₂) Zirconium oxide (Zirconium dioxide; ZrO (ZrO)₂) Lanthanum oxide (Lanthanum oxide; la₂O₃) Other similar metal oxide materials, metal nitride materials, or other suitable high-K materials.

Next, referring to fig. 1D, the first dielectric layer 140 is pressed on the first circuit layer 120 by a top-down thermal pressing method. Here, the first dielectric layer 140 covers the first circuit layer 120 and the first surface 112 and the second surface 114 of the insulating substrate 110 exposed by the first circuit layer 120, and fills the first via 116 and the second via 118.

Referring to fig. 1D, a third via 142, a first opening 144 and a first blind via 146 are formed on the first dielectric layer 140 by laser drilling. The third via 142 penetrates the first dielectric layer 140 and is located in the second conductive via 128, the first opening 144 exposes the capacitor dielectric layer 130, and the first blind via 146 exposes a portion of the first circuit layer 120. Here, as shown in fig. 1D, the aperture of the third through hole 142 gradually decreases from the first surface 112 to the second surface 114 of the insulating substrate 110, but not limited thereto. In other embodiments, not shown, the aperture of the third through hole 142 may also gradually decrease from the second surface 114 to the first surface 112 of the insulating substrate 110; alternatively, the first surface 112 and the second surface 114 of the insulating substrate 110 may be constant, which is within the scope of the present invention.

Next, referring to fig. 1E, a seed layer S1 is formed on the first dielectric layer 140 by electroless plating or other methods, wherein the seed layer S1 is made of copper, for example. Here, the seed layer S1 completely covers the first dielectric layer 140, the inner wall of the third via 142, the inner wall of the first opening 144, and the inner wall of the first via hole 146, and directly contacts the capacitor dielectric layer 130 exposed by the first opening 144 and another portion of the first circuit layer 120 exposed by the first via hole 146.

Next, referring to fig. 1F, a second circuit layer 150 is formed on the first dielectric layer 140 by, for example, Semi-additive Process (SAP), wherein the seed layer S1 can be used as a plating seed layer. The second circuit layer 150 covers a portion of the inner walls of the first dielectric layer 140 and the third via 142 and fills the first opening 144 and the first blind via 146. More specifically, the second circuit layer 150 includes a second circuit 152, a third conductive via 154, a first conductive via 156, and a second capacitor electrode 158. The second circuit 152 is disposed on a portion of the first dielectric layer 140, and the third conductive via 154 covers an inner wall of the third via 142. The first conductive via 156 fills the first via 146 and connects the first circuit layer 120 and the second circuit layer 150. The second capacitor electrode 158 fills the first opening 144. In particular, the second conductive via 128 and the third conductive via 154 define the coaxial via 20, and the first capacitor electrode 122, the capacitor dielectric layer 130 and the second capacitor electrode 158 define the capacitor 30.

Since the second conductive via 128 of the present embodiment covers the inner wall of the second via 118, the third via 142 penetrates the first dielectric layer 140 and is located in the second conductive via 128, and the third conductive via 154 covers the inner wall of the third via 142, the second conductive via 128 and the third conductive via 154 define the coaxial via 20. That is, the present embodiment can effectively utilize the space in the second through hole 118 to manufacture the coaxial through hole 20 suitable for high frequency (e.g., at least greater than or equal to 90GHz) communication, and has better design flexibility. In addition, when the second circuit layer 150 is formed, the coaxial via 20 and the capacitor 30 are simultaneously defined. That is, the coaxial via 20 and the capacitor 30 are simultaneously fabricated in the same process step, thereby effectively reducing the process time and the production cost.

Next, referring to fig. 1G, a second dielectric layer 160 is formed on the second circuit layer 150 by a top-down thermal compression method. Here, the second dielectric layer 160 covers the second line 152 of the second line layer 150 and the first dielectric layer 140 and fills the third via 142.

Next, referring to fig. 1H, a plurality of second blind vias 162 are formed on the second dielectric layer 160 by laser drilling, wherein the second blind vias 162 expose a portion of the second circuit layer 150, i.e., expose a portion of the second circuit 152 of the second circuit layer 150.

Thereafter, referring to fig. 1I, a seed layer S2 is formed on the second dielectric layer 160, and then, the third circuit layer 170 is formed on the second dielectric layer 160 and fills the second blind via 162, for example, by a semi-additive method. Here, the third circuit layer 170 includes a third circuit 172 and a plurality of second conductive pillars 174, wherein the third circuit 172 is disposed on the second dielectric layer 160, the second conductive pillars 174 fill the second blind holes 162, and the third circuit 172 of the third circuit layer 170 is electrically connected to the second circuit 152 of the second circuit layer 150 exposed by the second blind holes 162 of the second dielectric layer 160 through the second conductive pillars 174. The seed layer S2 is located between the third line 172 of the third circuit layer and the second dielectric layer 160 and between the second conductive pillar and the second dielectric layer 160.

Finally, referring to fig. 1J, a solder mask layer 180 is formed on the second dielectric layer 160. The solder mask layer 180 covers the second dielectric layer 160 and exposes a portion of the third wires 172 of the third wire layer 170 to define at least one pad P (two pads are schematically shown in fig. 1J). Thus, the circuit board structure 100 is completed.

In structure, referring to fig. 1J, the circuit board structure 100 includes an insulating substrate 110, a first circuit layer 120, a capacitor dielectric layer 130, a first dielectric layer 140, and a second circuit layer 150. The insulating substrate 110 has a first surface 112 and a second surface 114 opposite to each other, and a first via 116 and a second via 118 connecting the first surface 112 and the second surface 114. The first circuit layer 120 is disposed on the insulating substrate 110, and exposes a portion of the first surface 112 and the second surface 114. The first circuit layer 120 includes a first capacitor electrode 122, an inductor circuit 124, a first conductive via 126, and a second conductive via 128. The first capacitor electrode 122 is disposed on the first surface 112, and the inductor 124 is disposed on the first surface 112 and the second surface 114. The first conductive via 126 covers the inner wall of the first via 116 and the second conductive via 128 covers the inner wall of the second via 118. The inductor circuit 124 and the first conductive via 126 extend through the insulating substrate 110 in a spiral manner to define the three-dimensional inductor 10. The capacitor dielectric layer 130 is disposed on a portion of the first capacitor electrode 122. The first dielectric layer 140 covers the first circuit layer 120 and the first surface 112 and the second surface 114 of the insulating substrate 110 exposed by the first circuit layer 120, and fills the first conductive via 126 and the second conductive via 128. The first dielectric layer 140 has a third via 142, a first opening 144 and a first blind via 146. The third via 142 extends through the first dielectric layer 140 and is located within the second conductive via 128. The first opening 144 exposes the capacitor dielectric layer 130. The first blind via 146 exposes a portion of the first wiring layer 120. The second circuit layer 150 is disposed on the first dielectric layer 140 and includes a second circuit 152, a third conductive via 154, a first conductive via 156, and a second capacitor electrode 158. The second circuit 152 is disposed on a portion of the first dielectric layer 140. The third conductive via 154 covers an inner wall of the third via 142. The first conductive via 156 fills the first via 146 and connects the first circuit layer 120 and the second circuit layer 150. The second capacitor electrode 158 fills the first opening 144. The second conductive via 128 and the third conductive via 154 define a coaxial via 20. The first capacitor electrode 122, the capacitor dielectric layer 130 and the second capacitor electrode 158 define a capacitor 30. That is, the circuit board structure 100 of the present embodiment can effectively utilize the space in the second through hole 118 to manufacture the coaxial through hole 20 suitable for high frequency communication, and has better design flexibility. In addition, the circuit board structure 100 of the present embodiment has three structural elements with different characteristics, such as the three-dimensional inductor 10, the coaxial via 20, and the capacitor 30, and can be applied in a diversified manner and have a small overall thickness.

In addition, the circuit board structure 100 of the present embodiment further includes a second dielectric layer 160 and a third circuit layer 170. The second dielectric layer 160 is disposed on the second circuit layer 150, covers the second circuit layer 150, and fills the third conductive via 154. The second dielectric layer 160 has a plurality of second blind holes 162, and the second blind holes 162 expose a portion of the second circuit layer 150. The third circuit layer 170 is disposed on a portion of the second dielectric layer 160 and fills the second blind via 162, wherein the third circuit layer 170 is electrically connected to the second circuit layer 150.

In addition, the circuit board structure 100 of the present embodiment further includes a solder mask layer 180 disposed on the second dielectric layer 160, covering the second dielectric layer 160, and exposing a portion of the third circuit layer 170 to define a pad P for electrically connecting with an external circuit (not shown). Referring to fig. 1J again, in order to increase the structural reliability of the circuit board structure 100, the circuit board structure 100 of the present embodiment further includes seed layers S1 and S2, wherein the seed layer S1 is disposed between the second circuit layer 150 and the first dielectric layer 140 to increase the adhesion of the second circuit layer 150, and the seed layer S2 is disposed between the third circuit layer 170 and the second dielectric layer 160 to increase the adhesion of the third circuit layer 170.

In short, the circuit board structure 100 of the present embodiment has three structural elements with different characteristics, such as the three-dimensional inductor 10, the coaxial via 20, and the capacitor 30, and can be applied in a diversified manner and have a thinner overall thickness. When the circuit board structure 100 is used as a package carrier, the package thickness can be thinner, which can meet the current demand for thinning and lightening the package structure. In addition, the circuit board structure 100 can also be regarded as an interposer, which can be electrically connected to an external circuit (not shown).

In summary, in the design of the circuit board structure of the invention, the second conductive via covers an inner wall of the second via, the third via penetrates through the first dielectric layer and is located in the second conductive via, and the third conductive via covers an inner wall of the third via, wherein the second conductive via and the third conductive via define a coaxial via. That is, the circuit board structure of the present invention can effectively utilize the space in the second through hole to manufacture the coaxial through hole suitable for high frequency communication, and has better design flexibility. Moreover, the circuit board structure of the invention simultaneously has three structural elements with different characteristics, such as a three-dimensional inductor, a coaxial through hole, a capacitor and the like, can be applied in a diversified way, and has thinner integral thickness. In addition, in the manufacturing method of the circuit board structure, when the second circuit layer is formed, the coaxial through hole and the capacitor are defined at the same time. That is, in the same process step, the coaxial via and the capacitor are simultaneously fabricated, thereby effectively reducing the process time and the production cost.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A circuit board structure, comprising:

an insulating substrate having a first surface and a second surface opposite to each other, a plurality of first through holes connecting the first surface and the second surface, and a second through hole connecting the first surface and the second surface;

a first circuit layer disposed on the insulating substrate and exposing a portion of the first surface and the second surface, the first circuit layer including a first capacitor electrode, an inductor circuit, and a plurality of first conductive vias, the first capacitor electrode being disposed on the first surface, the inductor circuit being disposed on the first surface and the second surface, the plurality of first conductive vias covering inner walls of the plurality of first vias, the first circuit layer further including a second conductive via covering an inner wall of the second via, wherein the inductor circuit and the plurality of first conductive vias penetrate the insulating substrate in a spiral manner to define a three-dimensional inductor;

a capacitor dielectric layer disposed on a portion of the first capacitor electrode;

a first dielectric layer covering the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and filling the plurality of first conductive through holes and the plurality of second conductive through holes, wherein the first dielectric layer has a third through hole, a first blind hole and a first opening, the third through hole penetrates through the first dielectric layer and is located in the second conductive through hole, the first opening exposes the capacitor dielectric layer, and the first blind hole exposes a part of the first circuit layer; and

the second circuit layer is configured on the first dielectric layer and comprises a second circuit, a third conductive through hole, a first conductive blind hole and a second capacitor electrode, the second circuit is configured on part of the first dielectric layer, the third conductive through hole covers the inner wall of the third through hole, the first blind hole is filled with the first conductive blind hole and is connected with the first circuit layer and the second circuit layer, the second capacitor electrode is filled with the first opening, coaxial through holes are defined by the second conductive through hole and the third conductive through hole, and capacitors are defined by the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode.

2. The wiring board structure of claim 1, further comprising:

a second dielectric layer disposed on the second circuit layer, covering the second circuit layer and filling the third conductive through holes, wherein the second dielectric layer has a plurality of second blind holes exposing a portion of the second circuit layer; and

and a third circuit layer disposed on a portion of the second dielectric layer and filling the plurality of second blind holes, wherein the third circuit layer is electrically connected to the second circuit layer.

3. The wiring board structure of claim 2, further comprising:

and the solder mask layer is arranged on the second dielectric layer, covers the second dielectric layer, exposes part of the third circuit layer and defines at least one connecting pad.

4. The wiring board structure of claim 2, further comprising:

the seed layer is configured between the third circuit layer and the second dielectric layer.

5. The wiring board structure of claim 1, further comprising:

the seed layer is configured between the second circuit layer and the first dielectric layer.

6. A manufacturing method of a circuit board structure is characterized by comprising the following steps:

providing an insulating substrate having a first surface and a second surface opposite to each other, a plurality of first through holes connecting the first surface and the second surface, and a second through hole connecting the first surface and the second surface;

forming a first circuit layer on the insulating substrate, wherein the first circuit layer exposes a portion of the first surface and the second surface, and includes a first capacitor electrode, an inductor circuit, and a plurality of first conductive vias, the first capacitor electrode is located on the first surface, the inductor circuit is located on the first surface and the second surface, the plurality of first conductive vias cover inner walls of the plurality of first vias, the first circuit layer further includes a second conductive via covering an inner wall of the second via, and the inductor circuit and the plurality of first conductive vias penetrate through the insulating substrate in a spiral manner to define a three-dimensional inductor;

forming a capacitive dielectric layer on a portion of the first capacitive electrode;

pressing a first dielectric layer on the first circuit layer, wherein the first dielectric layer covers the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and fills the plurality of first through holes and the plurality of second through holes;

forming a third via, a first blind via, and a first opening in the first dielectric layer, wherein the third via penetrates the first dielectric layer and is located in the second conductive via, the first opening exposes the capacitor dielectric layer, and the first blind via exposes a portion of the first circuit layer; and

forming a second circuit layer on the first dielectric layer, wherein the second circuit layer covers a part of the inner walls of the first dielectric layer and the third through hole and fills the first blind hole and the first opening, the second circuit layer comprises a second circuit, a third conductive through hole, a first conductive blind hole and a second capacitor electrode, the second circuit is arranged on a part of the first dielectric layer, the third conductive through hole covers the inner wall of the third through hole, the first conductive blind hole fills the first blind hole and is connected with the first circuit layer and the second circuit layer, the second capacitor electrode fills the first opening, wherein the second conductive through hole and the third conductive through hole define a coaxial through hole, and the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor.

7. The method of making a circuit board structure of claim 6, further comprising:

forming a second dielectric layer on the second circuit layer, wherein the second dielectric layer covers the second circuit layer and fills the third through hole;

forming a plurality of second blind vias on the second dielectric layer, wherein the plurality of second blind vias expose a portion of the second circuit layer; and

and forming a third circuit layer on part of the second dielectric layer and filling the plurality of second blind holes, wherein the third circuit layer is electrically connected with the second circuit layer.

8. The method of making a circuit board structure of claim 7, further comprising:

and forming a solder mask layer on the second dielectric layer, wherein the solder mask layer covers the second dielectric layer and exposes the third circuit layer to define at least one pad.

9. The method of making a circuit board structure of claim 7, further comprising:

forming a seed layer between the third circuit layer and the second dielectric layer.

10. The method of making a circuit board structure of claim 6, further comprising:

forming a seed layer between the second circuit layer and the first dielectric layer.