CN110098115A - The cutting method of wafer - Google Patents
The cutting method of wafer Download PDFInfo
- Publication number
- CN110098115A CN110098115A CN201810094214.8A CN201810094214A CN110098115A CN 110098115 A CN110098115 A CN 110098115A CN 201810094214 A CN201810094214 A CN 201810094214A CN 110098115 A CN110098115 A CN 110098115A
- Authority
- CN
- China
- Prior art keywords
- wafer
- cutting
- cut
- depth
- groove body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005520 cutting process Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000003292 glue Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000005457 optimization Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The cutting method of wafer of the invention, comprising: the wafer with opposite first surface and second surface is provided；Protective glue is attached on the second surface of the wafer；Cutting for the first time is carried out to the direction of the second surface on the predetermined position of the first surface and forms the first groove body, and depth of cut is less than the overall depth of the wafer；And carry out cutting for the first time to the direction of the second surface on the predetermined position of the first surface and form the first groove body, depth of cut is less than the overall depth of the wafer.The present invention can reduce the deformation that wafer is generated in cutting, the service life for improving semiconductor yields and improving cutting blade.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of cutting methods of wafer.
Background technique
With the development of microelectric technique, the requirement for semiconductor components and devices is also higher and higher, and not only volume will be
It reduces, to be also continuously improved in precision.
Therefore, semiconductor fine-processing technique to also be constantly improve, especially in the process of cutting, for example, to subtract
The risk burst apart when cutting less for edge semiconductor, so that waste material is reduced.This requires cutting blades to want more and more thinner, to knife
The requirement of the rigidity and hardness of piece is also higher and higher.Currently, in order to make that more semiconductor element devices can be obtained on unit wafer
Part, highdensity wafer are constantly developed.Therefore operating condition is increasingly stringenter, due to the material hardness of bottom
It is very high, it is difficult to cut with general blade, it is necessary to which diamond blade is used in consideration.And blade meeting when using diamond blade cutting
It waves, shake, so that it is huge to generate internal stress, and cause deformation, the service life of blade is not high.Moreover, existing cutting
In process, often using disposably cutting is penetrated, the edge of semiconductor crystal wafer is be easy to cause to burst apart, the yields drop of product
It is low.
It would therefore be highly desirable to provide a kind of method for cutting wafer of optimization to overcome disadvantages described above.
Summary of the invention
The purpose of the present invention is to provide a kind of method for cutting wafer of optimization, to reduce the change that wafer is generated in cutting
Shape improves semiconductor yields and improves the service life of cutting blade.
To achieve the above object, the cutting method of wafer of the invention, comprising:
The wafer for having opposite first surface and second surface is provided；
Protective glue is attached on the second surface of the wafer；
Cutting for the first time, which is carried out, to the direction of the second surface on the predetermined position of the first surface forms first
Groove body, depth of cut are less than the overall depth of the wafer；And
Cutting for the first time, which is carried out, to the direction of the second surface on the predetermined position of the first surface forms the first slot
Body, depth of cut are less than the overall depth of the wafer.
Compared with traditional penetrability cutting, the present invention, can by carrying out secondary cut from the different surfaces of wafer
It bursts apart to avoid the cut edge of semiconductor crystal wafer, improves yields；Moreover, protective glue is attached on the surface of the wafer,
The internal stress that wafer generates in cutting process can be reduced, to reduce the deformation of wafer；And, secondary cut generates blade again
Internal stress, which is also reduced, thus prevents blade to deform, and improves blade service life.
Preferably, the first surface of the wafer is pasted with the protective glue.
Preferably, the protective glue is UV glue.
Preferably, the depth of cut of the first time cutting is the half of the overall depth of the wafer.
Specific embodiment
Method for cutting wafer of the invention is described further below with reference to embodiment, but is not so limited the present invention.
As one embodiment, the cutting method of wafer of the invention the following steps are included:
Wafer with protection step: providing a wafer, which has opposite first surface and second surface, the of wafer
Protective glue is attached on two surfaces；
First time cutting step: it is carried out for the first time on the predetermined position of the first surface to the direction of the second surface
Cutting forms the first groove body, and depth of cut is less than the overall depth of the wafer；
Second of cutting step: it is carried out for the first time on the predetermined position of the first surface to the direction of the second surface
Cutting forms the first groove body, and depth of cut is less than the overall depth of the wafer.
The benefit of such cutting method includes: compared with traditional penetrability cutting, and the present invention is by from wafer
Different surfaces carry out secondary cut, can burst apart to avoid the cut edge of semiconductor crystal wafer, raising yields；Moreover,
Protective glue is attached on the surface of the wafer, can reduce the internal stress that wafer generates in cutting process, to reduce the change of wafer
Shape；And, secondary cut can prevent blade from deforming again, improve blade service life.
Preferably, protective glue may be formed at second surface and/or first surface, which is preferably UV glue.In wafer
Cutting surfaces on form the effect of protective glue and be that wafer is protected to be shaken and damage by excessive cutting.Specifically,
Cutting blade of the invention is diamond blade.
In first time cutting step, the direction from first surface perpendicular to second surface is cut, and forms the first groove body, does not have
Have and completely cut through wafer, preferably depth of cut be wafer overall depth half.Compare the technique that wafer is disposably cut off and
Speech, the internal stress which generates on wafer in the process are smaller.Then, from second surface perpendicular to the first table
The direction in face carries out secondary cut, forms the second groove body, second groove body and the first groove body are mutually together with to complete cutting for wafer
It is disconnected.Preferably, the depth of cut of the secondary cut is the half of wafer overall depth.After secondary cut, protective glue is removed.
Preferably, further including carrying out cleaning to the product of well cutting.
In another example of the invention, the cut direction that should be cut for the second time can also be such as the cutting of first time cutting
Direction is consistent, that is, continues to be cut to second surface along the first groove body, to complete the wafer cutting of remaining depth.Together
Sample can reduce internal stress and improve wafer yields.
Above disclosed is only presently preferred embodiments of the present invention, cannot limit the right of the present invention with this certainly
Range, therefore according to equivalent variations made by scope of the present invention patent, it is still within the scope of the present invention.
Claims (4)
1. a kind of cutting method of wafer, characterized by comprising:
The wafer for having opposite first surface and second surface is provided；
Protective glue is attached on the second surface of the wafer；
Cutting for the first time, which is carried out, to the direction of the second surface on the predetermined position of the first surface forms the first groove body,
Depth of cut is less than the overall depth of the wafer；
Cutting for the first time is carried out to the direction of the second surface on the predetermined position of the first surface and forms the first groove body, is cut
Cut the overall depth that depth is less than the wafer.
2. the cutting method of wafer as described in claim 1, it is characterised in that: the first surface of the wafer is pasted with
The protective glue.
3. the cutting method of wafer as described in claim 1, it is characterised in that: the protective glue is UV glue.
4. the cutting method of wafer as described in claim 1, it is characterised in that: the depth of cut of the first time cutting is institute
State the half of the overall depth of wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810094214.8A CN110098115A (en) | 2018-01-31 | 2018-01-31 | The cutting method of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810094214.8A CN110098115A (en) | 2018-01-31 | 2018-01-31 | The cutting method of wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110098115A true CN110098115A (en) | 2019-08-06 |
Family
ID=67442349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810094214.8A Pending CN110098115A (en) | 2018-01-31 | 2018-01-31 | The cutting method of wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110098115A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110739216A (en) * | 2019-10-28 | 2020-01-31 | 东莞记忆存储科技有限公司 | Processing method for single-shaft step-by-step cutting wafers |
| CN111900082A (en) * | 2020-06-30 | 2020-11-06 | 联立(徐州)半导体有限公司 | Cutting method suitable for wafer cutting |
| CN112349582A (en) * | 2019-08-08 | 2021-02-09 | 东莞新科技术研究开发有限公司 | Wafer cutting method for reducing internal stress |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009294081A (en) * | 2008-06-05 | 2009-12-17 | Yamaha Corp | Manufacturing method of mems |
| CN102347275A (en) * | 2010-08-02 | 2012-02-08 | 北京中电科电子装备有限公司 | Method for sharpening blade of scribing machine |
| CN105226143A (en) * | 2015-09-29 | 2016-01-06 | 山东浪潮华光光电子股份有限公司 | A kind of cutting method of GaAs base LED chip |
-
2018
- 2018-01-31 CN CN201810094214.8A patent/CN110098115A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009294081A (en) * | 2008-06-05 | 2009-12-17 | Yamaha Corp | Manufacturing method of mems |
| CN102347275A (en) * | 2010-08-02 | 2012-02-08 | 北京中电科电子装备有限公司 | Method for sharpening blade of scribing machine |
| CN105226143A (en) * | 2015-09-29 | 2016-01-06 | 山东浪潮华光光电子股份有限公司 | A kind of cutting method of GaAs base LED chip |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112349582A (en) * | 2019-08-08 | 2021-02-09 | 东莞新科技术研究开发有限公司 | Wafer cutting method for reducing internal stress |
| CN110739216A (en) * | 2019-10-28 | 2020-01-31 | 东莞记忆存储科技有限公司 | Processing method for single-shaft step-by-step cutting wafers |
| CN110739216B (en) * | 2019-10-28 | 2022-03-29 | 东莞记忆存储科技有限公司 | Processing method for single-shaft step-by-step wafer cutting |
| CN111900082A (en) * | 2020-06-30 | 2020-11-06 | 联立(徐州)半导体有限公司 | Cutting method suitable for wafer cutting |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190806 |