CN110085676B - 具有半导体鳍结构的隧穿场效应晶体管 - Google Patents

具有半导体鳍结构的隧穿场效应晶体管 Download PDF

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CN110085676B
CN110085676B CN201910255948.4A CN201910255948A CN110085676B CN 110085676 B CN110085676 B CN 110085676B CN 201910255948 A CN201910255948 A CN 201910255948A CN 110085676 B CN110085676 B CN 110085676B
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柳青
S·M·塞利克
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Abstract

本发明涉及具有半导体鳍结构的隧穿场效应晶体管。在支撑衬底上由半导体材料鳍形成一种隧穿场效应晶体管。该半导体材料鳍包括源极区、漏极区和介于该源极区与该漏极区之间的沟道区。栅极电极在该沟道区处跨坐于鳍之上。在该栅极电极的每一侧上提供多个侧壁间隔物。该晶体管的源极由从该鳍的源极区生长出来并且掺杂有第一导电类型的外延含锗源极区制成。该晶体管的漏极由从该鳍的漏极区生长出来并且掺杂有第二导电类型的外延含硅漏极区制成。

Description

具有半导体鳍结构的隧穿场效应晶体管
本申请是申请日为2015年12月25日、申请号为201510997295.9、发明名称为“具有半导体鳍结构的隧穿场效应晶体管”的中国发明专利申请的分案申请。
技术领域
本发明涉及集成电路，并且具体涉及一种隧穿场效应晶体管(TFET)型半导体晶体管器件。
背景技术
现在参照示出了常规隧穿场效应晶体管(TFET)10器件的配置的图1。半导体衬底12轻掺杂有第一导电类型(在本示例中是n型)掺杂物。该半导体衬底可以例如由硅材料制成，并且可以是或者体衬底或者绝缘体上硅(SOI)衬底。源极区14和漏极区16在衬底12中提供在沟道区18的每一侧上，其中，沟道区由轻掺杂的第一导电类型半导体材料制成。与源极和漏极掺杂有与沟道所使用的掺杂物相反的同一导电类型掺杂物(例如，p型)的常规MOSFET器件不同，TFET被构造成使得源极区14重掺杂有第二导电类型(在本示例中是p型)掺杂物，并且漏极区16重掺杂有第一导电类型掺杂物。栅极氧化物层20提供在沟道区18之上，而栅极电极22提供在栅极氧化物层20之上。
图2A示出了曲线图，展示了TFET器件在截止(OFF)状态下的工作，其中所施加的栅极电压产生不足以允许隧穿的能带弯曲。在这种状态下，晶体管的泄漏电流非常低，因为任何这种泄漏仅是由于少数载流子漂移引起的。图2B示出了曲线图，展示了TFET器件在导通(ON)状态下的工作，其中所施加的栅极电压引起足以产生隧穿势垒宽度减小的能带弯曲。这引起电子(参考号24)从源极区14的价带带间隧穿(BTBT)至漏极区16的导带。
本领域的技术人员进一步认识到，锗(Ge)的提供、或者较少程度上硅锗(SiGe)(如p++型掺杂源极区14中所使用的半导体材料)改进了隧穿电流和导通电流(Ion)与截止电流(Ioff)的比率。图2A和图2B中以用于锗的导带和价带的实线与示出了使用p++型掺杂硅(Si)源极区的工作的点划线相比较示出了这一内容。锗源极区14的使用引起的价带带隙(Ev)增加进一步使隧穿势垒宽度减小/变窄。
虽然前述性能得到改进，但本领域中仍旧需要提供一种展现出改进的驱动电流能力的TFET器件。
发明内容
在实施例中，一种隧穿场效应晶体管包括：支撑衬底。半导体材料鳍，该鳍包括源极区、漏极区和介于该源极区与该漏极区之间的沟道区；在该沟道区处跨坐于该鳍之上的栅极电极；位于该栅极电极的每一侧上的多个侧壁间隔物；从该鳍的该源极区生长出来并且掺杂有第一导电类型的外延含锗源极区；以及从该鳍的该漏极区生长出来并且掺杂有第二导电类型的外延含硅漏极区。
在实施例中，一种方法包括：在支撑衬底上限定半导体材料鳍，该半导体材料鳍包括源极区、漏极区和介于该源极区与该漏极区之间的沟道区；形成在该沟道区处跨坐于该鳍之上的栅叠层；形成位于该栅叠层的每一侧上的多个侧壁间隔物；从该鳍的该源极区以外延方式生长出含锗源极区，该含锗源极区掺杂有第一导电类型；并且从该鳍的该漏极区以外延方式生长出含硅漏极区，所述含硅漏极区掺杂有第二导电类型。
附图说明
为了更好地理解实施例，现在将仅以示例方式参考附图，在附图中：
图1展示了现有技术隧穿场效应晶体管(TFET)器件的配置；
图2A和图2B展示了图1的TFET器件的工作；
图3至图17展示了形成TFET器件的工艺步骤；并且
图18至图30展示了形成TFET器件的工艺步骤。
具体实施方式
现在参照图3至图17，这些图展示了形成隧穿场效应晶体管(TFET)器件的工艺步骤。将理解的是，附图不一定示出按比例绘制的特征。
图3示出了在叠层中包括半导体衬底112、绝缘层114和硅半导体层116的绝缘体上硅(SOI)半导体衬底110。硅半导体层116可以根据应用而掺杂，或者可替代地在SOI衬底110是“全耗尽”型的情况下可以不掺杂。半导体层116可以例如具有4-16nm的厚度。绝缘层114在本领域中常被称为掩埋氧化物(BOX)层。
本领域中已知的外延生长工艺于是用于在半导体层116的顶部生长出由硅锗(SiGe)或锗(Ge)制成的半导体层118。层118可以例如具有20-40nm的厚度。外延生长工艺基于本领域的技术人员已知的SiH4或DTS。图4中示出了结果。
于是，执行凝聚技术来将锗原子从层118驱动到层116中。凝聚工艺可以例如包括氧化工艺，在该氧化工艺中，沉积SiO2层并且接着将晶片与氧气一起置于熔炉中，从而引起SiGe顶部区氧化并且驱动锗进入硅层116。图5中示出了本操作的结果，从而在绝缘层114的顶部产生具有超过80％的高锗含量并且例如20-40nm厚度的半导体层120。
作为替代方案，体硅半导体晶片110’可以被用作该工艺的起点。本领域中已知的外延生长工艺于是用于在体晶片110’的顶部生长出由硅锗(SiGe)或锗(Ge)制成的半导体层120’。层120’可以例如具有20-40nm的厚度。外延生长工艺基于本领域的技术人员已知的SiH4或DTS。图6中示出了结果，其中层120’优选地具有超过80％的高锗含量。
现在参照图7。在本图中，参考号130泛指可以例如包括半导体衬底112和与SOI衬底110(见图3至图5)绝缘的层114的支撑衬底。可替代地，具有参考号130的支撑衬底反而可以包括体硅半导体晶片110’(见图6)。此外，参考号132泛指高锗含量半导体层120或120’之一。因而，将理解的是，下述制造TFET器件的其余工艺步骤可以或者将衬底用作起点。
使用本领域的技术人员已知的常规平版印刷图案化技术，形成掩模来暴露区134。第一导电类型(例如，p型)的掺杂物注入区134内的含锗半导体层132中通过掩模来进行。P型掺杂物可以例如包括以1×1020至5×1020at/cm3的掺杂浓度注入的硼、二氟化硼(BF2)或铟。
使用本领域的技术人员已知的常规平版印刷图案化技术，形成掩模来暴露区136。第二导电类型(例如，n型)的掺杂物注入区136内的含锗半导体层132中于是通过该掩模来进行。n型掺杂物可以例如包括以5×1019至1×1020at/cm3的掺杂浓度注入的砷或磷。
接着执行低温退火来活化区134和136中注入的掺杂物并且使高锗含量半导体层132重结晶以提供p型掺杂区140和n型掺杂区142。退火可以例如使用<650℃的温度持续30-60秒时间和/或使用<700℃的尖峰持续1-100毫秒时间。区140和142由高锗含量半导体层132的掺杂有第二导电类型(n型)掺杂物的部分144分开。图8中示出了结果。
包括二氧化硅(SiO2)层232和氮化硅(SiN)层234的硬掩模230于是沉积在高锗含量半导体层132(以及区140、142和144)上。二氧化硅层232可以例如使用化学气相沉积(CVD)工艺以例如大致3-10nm的厚度沉积。氮化硅层234可以例如使用化学气相沉积(CVD)工艺以例如大致20-40nm的厚度沉积。图9中示出了结果。
然后使用本领域已知的平版印刷工艺来从含锗半导体层132中限定多个鳍300。图案化硬掩模230，以在这些鳍300的期望位置留下掩模材料236。接着执行蚀刻操作，穿透该掩模以在每个鳍300的每一侧上开出多个孔302。在SOI衬底的优选实施例中，例如，限定了鳍300的蚀刻延伸至到达绝缘层114的深度。这些鳍300可以具有6-12nm的宽度和24-50nm的间距(其中相邻鳍之间间隔10-40nm)。正交横截面图10A和图10B中示出了用于形成鳍的蚀刻工艺的结果。每个鳍300包括由p型掺杂区140形成的源极区150、由n型掺杂区142形成的漏极区152以及由区144形成的沟道区154。然后去除掩模材料236。
该工艺接下来移至TFET器件的栅叠层材料的沉积。栅叠层材料包括高介电常数电介质层160、可选势垒层162、金属层164、铁电材料层166、多晶硅层168和硬掩模层170。图11中示出了结果。高介电常数电介质层160可以例如包括使用原子层沉积技术沉积至1-3nm厚度以便用作栅极氧化物层的氧化铪(HfO2)。可选势垒层162可以例如包括使用原子层沉积技术沉积至1-3nm厚度的氧化镧(La2O3)。金属层164可以例如包括使用化学气相沉积技术沉积至3-8nm厚度以便作为栅极电极的功函数金属使用的氮化钛(TiN)。铁电材料层166可以例如包括使用化学气相沉积技术沉积至10-20nm厚度以便用于针对栅极电极引起负容量效应的锆钛酸铅(PbZrTiO3)、被称为“PZT”的压电材料。多晶硅层168例如使用化学气相沉积技术沉积至20-60nm厚度并且可以根据应用需要来掺杂。硬掩模层170可以例如包括使用化学气相沉积技术沉积至20-40nm厚度的氮化硅(SiN)。
然后使用本领域已知的平版印刷工艺来从栅叠层材料中限定栅叠层304。图案化硬掩模170，以在栅叠层304的期望位置留下掩模材料172。接着执行蚀刻操作，穿透该掩模以由这些层160-170形成栅叠层304。栅叠层304可以具有20-50nm的宽度。图12A中示出了用于形成栅叠层的蚀刻工艺的结果。图12B和图12C分别示出了鳍300的源极区和漏极区的横截面。尽管没有在图12B和图12C中明确示出，但将理解的是，栅叠层304相对于鳍式FET晶体管并且如图12D中概括所示以本领域已知的配置垂直于鳍300延伸并且跨坐于其之上。图12A中应注意的是，在配置中，栅叠层从沟道区偏移，其中该栅叠层还部分地覆盖在源极区上，从而使得该栅极能够控制位于p++型掺杂源极区与n型沟道区之间的界面处的沟道区。
使用原子层沉积技术进行氮化硅(SiN)层180的保形沉积。层180可以具有6-12nm的厚度。然后，形成遮蔽掩模182来保护鳍300的漏极侧。然后，执行诸如反应离子刻蚀(RIE)等定向蚀刻在栅叠层304的源极侧限定侧壁间隔物184。图13中示出了结果。
然后，使用本领域已知的外延生长工艺从鳍300的源极区150的暴露表面生长出硅锗源极区190。硅锗源极区190可以例如使用1×1020至5×1020at/cm3的掺杂浓度的硼掺杂物在原位掺杂有第一导电类型(p型)。图14A和图14B中示出了结果。源极区190连同源极区150的存在是优选的，因为区190能够提供对减小接触电阻有益的更高的活性掺杂浓度并且可以进一步提高结锐度以实现更好的隧穿。
然后，使用原子层沉积技术进行氮化硅(SiN)层186的保形沉积以保护硅锗区190。层182可以具有3-6nm的厚度。去除遮蔽掩模182。然后，执行诸如反应离子刻蚀(RIE)等定向蚀刻在栅叠层304的漏极侧限定侧壁间隔物188。图15中示出了结果。
然后，使用干法蚀刻工艺使鳍300的漏极区152凹陷至约5-10nm的厚度以提供凹陷含锗漏极区152’。然后，使用本领域已知的外延生长工艺从鳍300的凹陷式漏极区152’的暴露表面生长出硅漏极区192。硅漏极区192可以例如用1×1020至5×1020at/cm3的掺杂浓度在原位掺杂有第二导电类型(n型)掺杂物(例如，磷掺杂物)。图16A和图16B中示出了结果。使用外延硅用于漏极区192的优点是降低TFET结构的带间隧穿的栅极导致漏极泄漏(GIDL)，外延硅有效地将漏极区材料从锗含量(Ge或SiGe)变化成硅含量(Si)。另外，区192能够提供对减小接触电阻有益的更高的活性掺杂浓度。
然后，执行常规中段制程(MOL)和后段制程(BEOL)工艺来使预金属化电介质(PMD)层220沉积和平坦化并且分别形成与TFET结构的源极、漏极和栅极的金属接触222、224和226。图17中示出了结果。硅化区可以提供在每个金属接触222、224和226的底部。一个或多个金属化层(未明确示出)可以提供在PMD层220上方来帮助形成到接触222、224和226的电路互连。
所产生的TFET结构相应地包括p型掺杂高锗含量(Ge或SiGe)源极区150/190和n型掺杂高锗含量(Ge或SiGe)沟道区154以及n型掺杂硅漏极区192。TFET的栅极电极由功函数金属(层164)、铁电材料区(层166)和多晶硅区(层168)形成，并且此栅极电极通过高介电常数电介质区(层160)与沟道区154绝缘。响应于向栅极电极施加适当的电压，在源极区150的位于栅叠层304下面的那部分中发生带间隧穿(BTBT)。
现在参照图18至图30，这些图展示了形成隧穿场效应晶体管(TFET)器件的工艺步骤。将理解的是，附图不一定示出按比例绘制的特征。
图18示出了在叠层中包括半导体衬底412、绝缘层414和拉伸应变硅半导体层416的绝缘体上硅(SOI)半导体衬底410。半导体层416可以根据应用而掺杂，或者可替代地在SOI衬底110是“全耗尽”型的情况下可以不掺杂。半导体层416可以例如具有35-50nm的厚度。绝缘层414在本领域中常被称为掩埋氧化物(BOX)层。
作为替代方案，体硅半导体晶片410’可以被用作该工艺的起点。本领域中已知的外延生长工艺于是用于在体晶片410’的顶部生长出由硅锗(SiGe)制成的厚半导体层418。层120’可以例如具有>500nm的厚度。此SiGe层418起初受到压缩应力，但随着该层生长，应力松懈直至材料成为完全弛豫的SiGe。本领域中已知的外延生长工艺于是用于在SiGe层418的顶部生长出由硅(Si)制成的半导体层416’。半导体层416’可以根据应用而掺杂。因为硅层416’的晶格必须与SiGe层418的晶格匹配，硅层416’被拉伸应变。图19中示出了结果，其中层416”具有例如35-50nm的厚度
现在参照图20。在本图中，参考号430泛指可以例如包括半导体衬底412和与拉伸应变SOI衬底410(见图18)绝缘的层414的支撑衬底。可替代地，具有参考号430的支撑衬底包括SiGe层418和体硅半导体晶片410’(见图19)。此外，参考号432泛指拉伸应变硅半导体层416或416’之一。因而，将理解的是，下述制造TFET器件的其余工艺步骤可以或者将衬底用作起点。
包括二氧化硅(SiO2)层232和氮化硅(SiN)层234的硬掩模230于是沉积在受拉伸应力的半导体层432上。二氧化硅层232可以例如使用化学气相沉积(CVD)工艺以例如大致3-10nm的厚度沉积。氮化硅层234可以例如使用化学气相沉积(CVD)工艺以例如大致20-40nm的厚度沉积。图21中示出了结果。
然后使用本领域已知的平版印刷工艺来从受拉伸应力的半导体层432中限定多个鳍500。图案化硬掩模230，以在这些鳍500的期望位置留下掩模材料236。接着执行蚀刻操作，穿透该掩模以在每个鳍500的每一侧上开出多个孔502。在SOI衬底的优选实施例中，例如，限定了鳍500的蚀刻延伸至到达绝缘层414的深度。这些鳍500可以具有6-12nm的宽度和24-50nm的间距(其中相邻鳍之间间隔10-40nm)。图22A和图22B中示出了用于形成鳍的蚀刻工艺的结果。然后去除掩模材料236。
该工艺接下来移至本领域的技术人员已知的假栅叠层材料的沉积以便结合替换金属栅极(RMG)制造使用。假栅叠层材料包括多晶硅层510和硬掩模层512。多晶硅层510例如使用化学气相沉积技术沉积至20-60nm厚度并且可以根据应用需要来掺杂。硬掩模层512可以例如包括使用化学气相沉积技术沉积至20-40nm厚度的氮化硅(SiN)。
然后使用本领域已知的平版印刷工艺来从假栅叠层材料中限定假栅叠层520。图案化硬掩模512，以在栅叠层304的期望位置留下掩模材料514。接着执行蚀刻操作，穿透该掩模以由这些层510-512形成假栅叠层520。假栅叠层520可以具有20-50nm的宽度。图23A和图23B中示出了用于形成假栅叠层的蚀刻工艺的结果。将理解的是，栅叠层520相对于鳍FET晶体管和图23B概括所示以本领域已知的配置垂直于鳍500延伸并且跨坐于其之上。
然后，使用原子层沉积技术进行低介电常数材料(例如，SiBCN)层530的保形沉积。层530可以具有6-12nm的厚度。然后，执行诸如反应离子刻蚀(RIE)等定向蚀刻在假栅叠层520的每一侧上限定多个侧壁间隔物534。图24中示出了结果。
然后，使用干法蚀刻工艺使鳍500的受拉伸应力的硅半导体材料在假栅叠层520的将假栅叠层和侧壁间隔物534用作掩模的每一侧凹陷至约5-10nm的厚度。图25A至图25C中示出了这种凹陷工艺的结果。受拉伸应力的半导体材料沟道区600保持在假栅叠层和侧壁间隔物534下面。这个区600可以例如掺杂n型掺杂物结合着形成层432。厚度减小、受拉伸应力的半导体材料源极区602保持在沟道区600的一侧，而厚度减小、受拉伸应力的漏极区604保持在沟道区600的另一侧。
使用原子层沉积技术进行氮化硅(SiN)层610的保形沉积。层610可以具有3-5nm的厚度。本领域已知的平版印刷工艺于是用于假栅叠层和侧壁间隔物534的一侧上(例如，在源极侧上)的层。图26中示出了结果。
然后，使用本领域已知的外延生长工艺从鳍500的厚度减小、受拉伸应力的半导体材料源极区602的暴露表面生长出硅锗源极区190。硅锗源极区190可以例如使用1×1020至5×1020at/cm3的掺杂浓度的硼掺杂物在原位掺杂有第一导电类型(p型)。图27A和图27B中示出了结果。源极区602上存在源极区190能够提供对减小接触电阻有益的更高的活性掺杂浓度。
然后，使用原子层沉积技术进行氮化硅(SiN)层612的保形沉积以保护硅锗源极区190和受拉伸应力的源极区602。层612可以具有3-5nm的厚度。本领域已知的平版印刷工艺于是用于假栅叠层和侧壁间隔物534的一侧上(例如，在源极侧上)的层。图28中示出了结果。
然后，使用本领域已知的外延生长工艺从鳍500的厚度减小、受拉伸应力的半导体材料漏极区604的暴露表面生长出硅漏极区192。硅漏极区192可以例如使用1×1020至5×1020at/cm3掺杂浓度的磷掺杂物在原位掺杂有第二导电类型(n型)。图29A和图29B中示出了结果。使用外延硅用于漏极区192的优点是降低TFET器件的带间隧穿的栅致漏极泄漏(GIDL)。漏极区604上存在漏极区192能够提供对减小接触电阻有益的更高的活性掺杂浓度。
使用众所周知的加工技术，于是用包括高介电常数电介质层650、功函数金属层652和金属(例如，钨)填充物654的替换金属栅极(RMG)替换假栅极。将进一步理解的是，填充物654可以包括铁电材料区(见上述参考号166)连同上面覆盖的钨(或其他接触金属)沉积物。然后，执行常规中段制程(MOL)和后段制程(BEOL)工艺来使预金属化电介质(PMD)层220沉积和平坦化并且分别形成与TFET结构的源极、漏极和栅极的金属接触222、224和226。图30中示出了结果。硅化区可以提供在每个金属接触222、224和226的底部。一个或多个金属化层(未明确示出)可以提供在PMD层220上方来帮助形成到接触222、224和226的电路互连。
所产生的TFET结构相应地包括p型掺杂含锗(SiGe)源极区(由鳍应变硅区602上的硅锗源极区190提供)、应变硅(n型)沟道区600和n型掺杂硅漏极区(由应变硅区604上的硅漏极区192提供)。TFET的栅极电极由功函数金属(层652)和和金属填充物654(也许还包括铁电材料以供用于针对栅极电极引起负电容效应)形成，并且通过高电介质常数电介质区(层650)与沟道区154绝缘。响应于向栅极电极施加适当的电压，在源极区的位于替换金属栅极下面的那部分中发生带间隧穿(BTBT)。
已经通过示例性且非限制性的示例提供了前面的描述，是对本发明示例性实施例的完整且信息性描述。然而，对于相关领域的技术人员而言，鉴于前面的描述，当结合附图和所附权利要求书来阅读本说明书时，各种修改和适配会变得明显。然而，对本发明教导的所有这样和类似的修改将仍然落入如所附权利要求书所限定的本发明的范围之内。

Claims (20)

1.一种隧穿场效应晶体管，包括：
支撑衬底；
半导体材料鳍，所述半导体材料鳍包括源极区、漏极区和介于所述源极区与所述漏极区之间的沟道区，其中，所述半导体材料鳍的所述沟道区具有第一厚度，并且其中，所述半导体材料鳍的所述源极区和所述漏极区具有小于所述第一厚度的第二厚度；
在所述沟道区处跨坐于所述半导体材料鳍之上的栅极电极；
从所述半导体材料鳍的所述源极区生长出来并且掺杂有第一导电类型的外延含锗源极区；以及
从所述半导体材料鳍的所述漏极区生长出来并且掺杂有第二导电类型的外延含硅漏极区。
2.如权利要求1所述的隧穿场效应晶体管，其中，所述源极区掺杂有所述第一导电类型而所述漏极区掺杂有所述第二导电类型。
3.如权利要求2所述的隧穿场效应晶体管，其中，所述沟道区掺杂有所述第二导电类型。
4.如权利要求1所述的隧穿场效应晶体管，其中，所述半导体材料鳍由拉伸应变硅制成。
5.如权利要求1所述的隧穿场效应晶体管，其中，所述栅极电极包括：功函数金属和铁电材料。
6.如权利要求1所述的隧穿场效应晶体管，其中，所述栅极电极包括：功函数金属和金属填充物。
7.如权利要求1所述的隧穿场效应晶体管，其中，所述支撑衬底包括绝缘体上硅衬底。
8.如权利要求1所述的隧穿场效应晶体管，其中，所述支撑衬底包括体衬底。
9.一种用于形成隧穿场效应晶体管的方法，包括：
在支撑衬底上限定半导体材料鳍，所述半导体材料鳍包括源极区、漏极区和介于所述源极区与所述漏极区之间的沟道区；
减小所述半导体材料鳍的所述源极区和所述漏极区的厚度至小于所述沟道区的厚度；
形成在所述沟道区处跨坐于所述半导体材料鳍之上的栅叠层；
从所述半导体材料鳍的所述源极区以外延方式生长出含锗源极区，所述含锗源极区掺杂有第一导电类型；并且
从所述半导体材料鳍的所述漏极区以外延方式生长出含硅漏极区，所述含硅漏极区掺杂有第二导电类型。
10.如权利要求9所述的方法，其中，所述沟道区掺杂有所述第二导电类型。
11.如权利要求9所述的方法，其中，限定半导体材料鳍包括：
形成拉伸应变硅半导体材料层；并且
图案化所述半导体材料层以限定所述半导体材料鳍。
12.如权利要求9所述的方法，其中，形成所述栅叠层包括：沉积功函数金属并且沉积铁电材料。
13.如权利要求9所述的方法，其中，形成所述栅叠层包括：
提供假栅叠层；并且
用替换金属栅极替换所述假栅叠层，所述替换金属栅极包括：功函数金属和金属填充物。
14.如权利要求9所述的方法，其中，所述支撑衬底包括绝缘体上硅衬底。
15.如权利要求9所述的方法，其中，所述支撑衬底包括体衬底。
16.一种用于形成隧穿场效应晶体管的方法，包括：
限定第一半导体材料鳍，所述第一半导体材料鳍包括掺杂有第一导电类型的源极区、掺杂有第二导电类型的漏极区以及掺杂有所述第二导电类型并且位于所述源极区和所述漏极区之间的沟道区；
在所述第一半导体材料鳍的顶部和侧面上沉积一个或多个栅极堆叠材料层；
图案化沉积的所述栅极堆叠材料层，以限定至少在所述沟道区之上延伸的栅极堆叠；
第一掩模，以覆盖所述栅极堆叠和所述漏极区的第一部分并且暴露所述源极区；
在所述源极区处在所述第一半导体材料鳍的顶部和侧面上第一外延生长第二半导体材料，以形成外延源极区；
第二掩模，以覆盖所述栅极堆叠和所述源极区的第二部分并且暴露所述漏极区；
减小所述漏极区处的所述第一半导体材料鳍的厚度；以及
在所述漏极区处的厚度减小的所述鳍的顶部和侧面上第二外延生成第三半导体材料，以形成外延漏极区。
17.如权利要求16所述的方法，其中所述第一半导体材料包括锗，所述第二半导体材料包括锗，并且所述第三半导体材料不包括锗。
18.如权利要求17所述的方法，其中所述第一半导体材料具有超过80％的锗含量。
19.如权利要求16所述的方法，其中沉积的所述栅极堆叠材料层包括功函数金属层和铁电材料层。
20.如权利要求16所述的方法，其中图案化沉积的所述栅极堆叠材料层以限定至少在所述沟道区之上延伸的所述栅极堆叠包括：设置所述栅极堆叠以在所述源极区的一部分之上延伸而不在所述漏极区的任一部分之上延伸。
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