CN110085551B - Process for fabricating bit line of memory device, memory device and method of fabricating the same - Google Patents

Process for fabricating bit line of memory device, memory device and method of fabricating the same Download PDF

Info

Publication number
CN110085551B
CN110085551B CN201810072900.5A CN201810072900A CN110085551B CN 110085551 B CN110085551 B CN 110085551B CN 201810072900 A CN201810072900 A CN 201810072900A CN 110085551 B CN110085551 B CN 110085551B
Authority
CN
China
Prior art keywords
bit line
etching
layer
line contact
etching step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810072900.5A
Other languages
Chinese (zh)
Other versions
CN110085551A (en
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201810072900.5A priority Critical patent/CN110085551B/en
Publication of CN110085551A publication Critical patent/CN110085551A/en
Application granted granted Critical
Publication of CN110085551B publication Critical patent/CN110085551B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

The application provides a manufacturing process of a bit line of a storage element, the storage element and a manufacturing method thereof. The manufacturing process comprises the following steps: providing a substrate, wherein the substrate comprises a semiconductor substrate and an isolation structure, and the upper surface of the substrate comprises a source electrode surface of a source region and an insulation isolation surface; depositing a bit line contact layer and a bit line conductor layer on the upper surface of the substrate; and etching and removing part of the bit line conductor layer and the bit line contact layer outside the bit line pattern according to the bit line pattern, wherein the part of the upper surface exposed out of the semiconductor substrate is formed into the bit line conductor. The manufacturing process can relieve or eliminate the side etching of the bit line contact, avoid the problem of higher resistance caused by the more serious side etching of the bit line contact, and ensure that the memory element has the performances of higher response speed and the like.

Description

Process for fabricating bit line of memory device, memory device and method of fabricating the same
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a manufacturing process of a bit line of a memory device, and a manufacturing method thereof.
Background
In a semiconductor memory device, a plurality of memory cells in the same row or column are connected in series by a common conductive line. The line that connects the memory cells is called a word line, and the other line that is perpendicular to the word line is called a bit line because it is related to the transmission of data.
With the increase of the integration level of integrated circuits, the memory devices are gradually shrinking. The width of the bit lines in the memory elements is reduced. The narrowing of the width of the bit line results in an increase in the resistance of the bit line, which causes a decrease in the current of the memory cell, resulting in an excessive bit line load, and increases the difficulty of manufacturing.
The bit line contact layer has a harsh etching condition at a small aspect ratio of line width to a high aspect ratio, which results in a bit line corresponding to the bit line connected to the active region. As shown in fig. 1A to 1E, when the trench of the start region is etched downward, the trench is larger and deeper due to the difference of the etching selectivity, such as the right trench 201 in fig. 1B; therefore, more polysilicon is required to be filled into a larger and deeper trench in the subsequent process, as shown in fig. 1C, so that in the bit line etching process, the bit line contact layer is likely to be abnormal in the word line direction, and the specific abnormality includes: in order to etch the bit line with a predetermined width, the polysilicon in the trench is not etched completely, and a part remains, as shown in fig. 1D, thereby causing the bit line to be short-circuited; in order to avoid short circuit, the polysilicon in the trench is completely etched away by over-etching, which causes the formed bit line to be laterally etched, resulting in a smaller width, and the resistance of the bit line is higher as shown in fig. 1E.
The structures shown in fig. 1A to 1E include a semiconductor substrate 100, an isolation structure 200, a trench 201, an etching mask layer 301, a bit line contact layer 402, a bit line 401, a titanium nitride layer 501, a tungsten layer 600, and a silicon nitride film layer 700, and their specific positions are shown in the figures.
Disclosure of Invention
The present disclosure is directed to a manufacturing process of a bit line of a memory device, a memory device and a manufacturing method thereof, so as to solve the problem in the prior art that when polysilicon in a trench of an active region is etched and removed, a bit line contact layer is severely etched to cause an excessively thin bit line.
In order to achieve the above object, according to one aspect of the present application, there is provided a fabrication process of a bit line of a memory element, the fabrication process including: providing a base, wherein the base comprises a semiconductor substrate and an isolation structure arranged in the semiconductor substrate, the isolation structure is used for isolating a plurality of active regions of the semiconductor substrate, and the upper surface of the base comprises a source electrode surface of the active regions and an insulation isolation surface of the isolation structure; depositing a bit line contact layer and a bit line conductor layer on the source surface and the insulation isolation surface in sequence, wherein the bit line contact layer covers the source surface and the insulation isolation surface between the adjacent source surfaces; and sequentially removing part of the bit line conductor layer and the bit line contact layer outside the bit line pattern by means of patterned etching according to the bit line pattern so as to expose part of the upper surface of the semiconductor substrate, wherein the removed bit line conductor layer is formed into a bit line conductor, the process of etching the bit line conductor layer comprises a main etching step and an over etching step, the removed bit line contact layer is formed into a bit line contact on the surface of the source electrode in the main etching step, and bit line contact residues on the insulation isolation surface between two adjacent bit line contacts in the over etching step are removed by means of etching gas controlled by means of side etching, wherein the etching gas contains hydrogen bromide and oxygen.
Furthermore, the insulation isolation surface is recessed inwards to form a groove, and after the over-etching step, the lateral etching recess depth of the bit line contact is equal to or less than the surface recess depth of the insulation isolation surface.
Further, the material of the bit line contact layer includes polysilicon.
Further, the main etching step of the bit line contact layer over the semiconductor substrate includes: and etching and removing part of the bit line contact layer above the semiconductor substrate by using etching gas comprising hydrogen bromide, chlorine and oxygen to form the bit line contact.
Further, in the etching gas for performing the main etching step of the bit line contact layer on the semiconductor substrate, the volume ratio of hydrogen bromide, chlorine and oxygen is in the range of (85-95): (4-10): (1-5).
Further, in the over-etching step, the cut-out profile of the bit line contact depends on the amount of oxygen introduced in the over-etching step, and the increase in the amount of oxygen introduced in the over-etching step accelerates the generation of the side etching protective film.
Furthermore, in the etching gas of the over-etching step for removing the bit line contact residues, the volume ratio of hydrogen bromide to oxygen is (45-55): (2-8).
Furthermore, the etching gas of the over-etching step for removing the bit line contact residues further comprises helium, and the volume ratio of the hydrogen bromide to the oxygen to the helium is (45-55): (2-8): (40-50).
Further, a main etching step for forming the bit line contact is carried out in an etching reaction chamber, wherein in the main etching step, the pressure of the etching reaction chamber is controlled to be less than or equal to 10 mTorr; the over-etching step for removing the bit line contact residue controls the pressure of the etching reaction cavity to be greater than or equal to 50 mTorr.
Further, the process of providing the above substrate includes: providing the semiconductor substrate, and forming a groove in the semiconductor substrate; arranging the isolation structure in the groove, wherein the insulation isolation surface is at least flush with the surface of the source electrode; and etching to remove part of the isolation structure, so that the insulation isolation surface is inwards recessed to form a groove.
Further, the forming of the trench includes: arranging an etching mask layer on the surface of the source electrode and the insulating isolation surface, wherein the etching mask layer is a silicon nitride layer; and etching and removing the etching mask layer and part of the isolation structure by using etching gas containing carbon tetrafluoride and trifluoromethane to form the trench, wherein the volume ratio of the trifluoromethane to the carbon tetrafluoride is 0.8-1.2.
Further, the bit line conductor layer comprises a titanium nitride layer and a tungsten layer which are sequentially overlapped in the direction far away from the bit line contact layer; the process of etching the bit line conductor layer comprises the following steps: etching and removing part of the tungsten layer by using etching gas containing sulfur hexafluoride; and etching and removing part of the titanium nitride layer by using etching gas comprising chlorine.
Further, after depositing the bit line conductor layer and before etching a portion of the bit line conductor layer and the bit line contact layer, the manufacturing process further includes: depositing a barrier layer on the surface of the bit line conductor layer far away from the bit line contact layer, wherein the barrier layer comprises a silicon nitride film layer and a silicon oxide film layer which are sequentially overlapped in the direction far away from the bit line conductor layer; before removing part of the bit line conductor layer, the manufacturing process further includes: and etching and removing part of the barrier layer outside the bit line pattern according to the bit line pattern to form a barrier part.
Further, the upper surface of the substrate further includes a drain surface of the active region, and after depositing the barrier layer and before removing a portion of the barrier layer, the manufacturing process further includes: and arranging a mask pattern layer on the surface of the barrier layer far away from the bit line conductor layer, wherein the mask pattern layer covers the structure above the surface of the drain electrode and exposes the structure above the surface of the source electrode.
Further, the etching gas ratio of the over-etching step is different from the etching gas ratio of the main etching step, so that the width of the middle part of the bit line contact is not less than 60% of the width of the top part of the bit line contact, and the bit line contact residue on the insulating isolation surface is completely removed.
In order to achieve the above object, according to another aspect of the present application, there is provided a method of manufacturing a memory element, the method including a process of manufacturing a bit line of the memory element.
In order to achieve the above object, according to still another aspect of the present application, there is provided a memory element including a bit line, the bit line being fabricated by a process of fabricating the bit line of the memory element described above.
By applying the technical scheme of the application, HBr and O are generated in the process of etching part of the bit line contact layer by adopting etching gas2Will react with Si/SiO in the bit line contact layer to form SiOxBry polymer, i.e. reaction Si/SiO + O occurs2+ HBr → SiOxBry, SiOxBry can protect the side wall of the bit line contact, so that the side etching of the bit line contact is relieved or eliminated in the etching process of the bit line, the problem of high resistance caused by the serious side etching of the bit line contact is avoided, and the memory element is ensured to have the performances of high response speed and the like.
The present disclosure is directed to a manufacturing process of a bit line of a memory device, a memory device and a manufacturing method thereof, so as to solve the problem in the prior art that when polysilicon in a trench of an active region is etched and removed, a bit line contact layer is severely etched to cause an excessively thin bit line.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIGS. 1A to 1E are schematic diagrams illustrating a process for fabricating a bit line of another memory device in the prior art;
FIGS. 2 to 8 are schematic diagrams illustrating a manufacturing process of a bit line of a memory device according to an embodiment of the present application;
FIG. 9 illustrates an embodiment providing a graph of etch selectivity ratio of silicon nitride to silicon oxide as a function of a ratio of volumetric amounts of gases of trifluoromethane and carbon tetrafluoride;
FIG. 10 is a graph showing the etch selectivity of silicon nitride to silicon oxide as a function of pressure in an etch reactor provided in accordance with another embodiment;
FIGS. 11 and 12 are schematic diagrams illustrating a process for fabricating a bit line of a memory device according to still another embodiment of the present application;
FIGS. 13 and 14 are schematic diagrams illustrating the fabrication process of bit lines of 30 nm bit line memory devices; and
fig. 15 and 16 are schematic diagrams illustrating a process of fabricating a bit line of a 20 nm bit line memory device.
The reference numbers illustrate:
the prior art is as follows:
100. a semiconductor substrate; 200. An isolation structure; 201. A trench;
301. etching the mask layer; 402. A bit line contact layer; 401. A bit line;
501. a titanium nitride layer; 600. A tungsten layer; 700. A silicon nitride film layer.
The invention comprises the following steps:
10. a semiconductor substrate; 11. An insulating layer; 12. A word line;
13. an active region; 130. A source surface; 121. A titanium nitride layer;
122. a tungsten layer; 20. An isolation structure; 21. An insulating isolation surface;
30. a bit line contact layer; 30A, bit line contact residue; 40. A bit line conductor layer;
50. a barrier layer; 300. A bit line contact; 400. A bit line conductor;
02. a silicon nitride layer; 41. A titanium nitride layer; 42. A tungsten layer;
51. a silicon nitride film layer; 52. A silicon oxide film layer; 60. SiOxBry polymers;
70. a word line insulating portion; 80. A mask pattern layer; 500. A blocking portion.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As described in the background art, in the prior art, when polysilicon in a trench of an active region is etched and removed, a bit line contact layer may have a severe undercut phenomenon, which results in a too thin formed bit line and a too large resistance.
In an exemplary embodiment of the present application, a process for fabricating a bit line of a memory device is provided, the process comprising: providing a base including a semiconductor substrate 10 and an isolation structure 20 disposed in the semiconductor substrate 10, as shown in fig. 3, wherein the isolation structure 20 (e.g., STI) is used for isolating a plurality of active regions 13 of the semiconductor substrate 10, and an upper surface of the base includes a source surface of the active regions 13A surface 130 and an insulating isolation surface 21 of the isolation structure 20; sequentially depositing a bit line contact layer 30 and a bit line conductor layer 40 on the source surface 130 of the active region 13 and the insulation isolation surface 21 of the isolation structure 20, as shown in fig. 4; sequentially pattern-etching and removing a portion of the bit line conductor layer 40 and the bit line contact layer 30 outside the bit line pattern according to a bit line pattern to expose a portion of the upper surface of the semiconductor substrate 10, wherein the removed bit line conductor layer 40 is formed as a bit line conductor 400, and the process of etching the bit line conductor layer 40 includes a main etching step in which the removed bit line contact layer 30 is formed as a bit line contact 300 on the source surface 130, and an over-etching step in which the bit line contact layer 30 is removed between two adjacent bit line contacts 300 and a bit line contact residue 30A on the insulation isolation surface 21 by an etching gas controlled by side etching, wherein the etching gas includes hydrogen bromide (HBr) and oxygen (O) gas2) To form the structure of fig. 6, 7 or 8, the removal process may be a continuous process or a discontinuous process, wherein HBr and O are used2The etching gas of (1) etching part of the bit line contact layer 30, i.e. dry etching the bit line contact layer 30, wherein the etching gas used for the dry etching comprises HBr and O2HBr, O as shown in FIG. 6, FIG. 7 or FIG. 82Will react with the Si/SiO in the bit line contact layer 30 to form the SiOxBry polymer 60. The bit line contact layer 30 and the bit line conductor layer 40 remaining last form the bit line.
In the above-mentioned manufacturing method, the etching step of the bit line contact layer 30 is performed by using an etching gas, HBr, O2Will react with Si/SiO in the bit line contact layer 30 to form SiOxBry, i.e., reaction Si/SiO + O occurs2+ HBr → SiOxBry, the SiOxBry polymer 60 generated can protect the sidewall of the bit line contact 300, relieve or eliminate the side etching of the bit line contact 300, avoid the problem of high resistance caused by the serious side etching of the bit line contact 300, and ensure the performance of the memory device such as fast response speed.
In an embodiment of the present application, the insulation isolation surface 21 is recessed inward to form a trench, so as to better isolate the active region 13, and after the over-etching step, the undercut depth of the bit line contact 300 is equal to or less than the surface undercut depth of the insulation isolation surface 21.
In order to better alleviate the undercut of the bit line contact layer 30 or completely eliminate the undercut of the bit line contact layer 30, in an embodiment of the present application, the material of the bit line contact layer 30 includes polysilicon.
In order to further ensure that the sidewalls of the bit line contact 300 are not undercut or are undercut only slightly, so as to further ensure that the formed bit line contact 300 is wider, and thus the memory device has good performance, in an embodiment of the present application, the main etching step of the bit line contact layer 30 over the semiconductor substrate 10 includes: the method comprises HBr and Cl2And O2The etching gas is used to etch and remove a portion of the bit line contact layer 30 above the semiconductor substrate 10 to form the bit line contact 300, as shown in fig. 5, during the etching process, the etching gas reacts with the substance in the bit line contact layer 30: si + Cl → SiCl4(g) Or Si + Br → SiBr4(g) And also includes the side reaction Si/SiO + O2+HBr→SiOxBry。
In order to better control the main etching step of the bit line contact layer 30 over the semiconductor substrate 10, in one embodiment of the present application, HBr, Cl are used as the etching gas in the process2And O2The volume ratio of (a) is in the range of (85-95): (4-10): (1-5).
In the above-described over-etching step, the cut-off profile of the bit line contact 300 depends on the amount of oxygen introduced in the over-etching step, and the increase in the amount of oxygen introduced in the over-etching step accelerates the generation of the undercut protective film.
In order to better control the process of etching and removing the polysilicon on the isolation surface 21 of the isolation structure 20, thereby ensuring the proper dimension of the formed bit line, in another embodiment of the present application, HBr and O are in the etching gas of the overetching step of removing the bit line contact residue 30A from the isolation surface 212The volume ratio of (45-55): (2-8). When HBr and O are reacted2When the volume ratio of (2) is controlled to be in the above range, the structure of the bit line formed correspondingly is as shown in FIG. 7. When HBr and O are reacted2When the volume ratio control of (3) is out of the above range, the structure of the formed bit line is as shown in FIG. 6 or FIG. 8.
The volume of oxygen in the etching gas forming the structure of fig. 6 is small, so that the generated SiOxBry polymer 60 is small, and the sidewalls of the remaining bit line contacts 300 cannot be well protected, so that the width of the last remaining bit line contacts 300 is relatively small. The greater volume of oxygen in the etching gas forming the structure of fig. 8 results in more SiOxBry polymer 60 being formed and better protects the bit line contact 300, resulting in a relatively greater width of the last remaining bit line contact 300 that is greater than the predetermined dimension.
To further ensure that the pressure in the reaction chamber is high, in one embodiment of the present application, the etching gas of the over-etching step for removing the bit line contact residue 30A further includes helium (He). And in the etching gas in the step, HBr and O2The volume ratio of the compound to He is (45-55): (2-8): (40-50). He is used here to increase the pressure in the reaction chamber, which does not actually take part in the chemical reaction.
In order to make the etching process biased to the chemical reaction and further increase the amount of the generated SiOxBry polymer 60, thereby better protecting the sidewall of the bit line contact 300 and further ensuring the formation of the bit line with the predetermined shape and the predetermined size, in an embodiment of the present application, a main etching step for forming the bit line contact 300 is performed in an etching reaction chamber, and in the main etching step, the pressure of the etching reaction chamber is controlled to be less than or equal to 10 mTorr; in the over-etching step for removing the bit line contact residue 30A, the pressure of the etching reaction cavity is controlled to be less than or equal to 10 mTorr; in the etching step of the bit line contact layer 30 between two adjacent bit line contacts 300 and on the insulating isolation surface 21, the pressure of the etching reaction chamber is controlled to be greater than or equal to 50 mTorr.
Of course, other gases may be used to increase the pressure in the reaction chamber, as long as the gases do not participate in the chemical reaction. The skilled person can select suitable gases, such as some inert gases, etc., according to the actual situation.
In another embodiment of the present application, the process of providing the substrate includes: providing a semiconductor substrate 10 layer; forming a groove in the semiconductor substrate 10 layer; providing an isolation structure 20 in the recess, wherein the isolation surface 21 is at least flush with the source surface 130; etching away part of the isolation structure 20, so that the isolation surface 21 is recessed inward to form the trench shown in fig. 3.
Note that, before the isolation structures 20 are actually provided in the grooves, the insulating layer 11 and the word line 12 may be sequentially provided in the grooves, and the insulating layer 11 is used to isolate the semiconductor substrate 10 from the word line 12, as shown in fig. 13 to 16, and since fig. 2 to 12 show cross-sectional views of the memory element along the direction of the word line 12, the insulating layer 11 and the word line 12 are not visible in these drawings.
In one embodiment, as shown in fig. 13 to 16, the insulating layer 11 is a silicon dioxide layer, and the word line 12 includes a titanium nitride layer 121 and a tungsten layer 122 sequentially disposed.
For example, as shown in fig. 13-16, in the case of 20 nm and 30 nm bit lines, the bit line fabrication structure is wavy, and the bit line contact layer 30 is etched downward instead of planar to reduce the height of the bit line, thereby reducing the difficulty in fabricating the connecting channel from the capacitor to the active region. The structure of fig. 13 to 16 includes a semiconductor substrate 10, an insulating layer 11, a word line 12, a titanium nitride layer 121, a tungsten layer 122, a word line insulating portion 70, a bit line contact layer 30, a bit line contact 300, a titanium nitride layer 41, a tungsten layer 42, a bit line conductor 400, a silicon nitride film layer 51, a silicon oxide film layer 52, a barrier portion 500, and a mask pattern layer 80, and the specific positional relationship is as shown in the figure. FIG. 13 is a schematic diagram of the structure of the memory device having 30 nm bit lines in the bit line direction corresponding to FIG. 4, and FIG. 14 is a schematic diagram of the structure of the memory device having 30 nm bit lines in the bit line direction corresponding to FIG. 5; FIG. 15 is a schematic diagram of a structure obtained after an etching step is performed on a 30 nm bit line memory element in the bit line direction; fig. 16 is a schematic structural diagram of a memory element having a 20 nm bit line in the bit line direction corresponding to fig. 5.
Of course, the insulating layer 11 of the present application is not limited to the silicon dioxide layer, and may be other material layers for isolating the semiconductor substrate 10 from the word line 12, such as a composite layer of silicon dioxide and silicon nitride, and the like. Similarly, the word line 12 of the present application is not limited to the above-mentioned titanium nitride layer 121 and tungsten layer 122, and for example, the tungsten layer 122, titanium nitride layer 121, and titanium layer may be sequentially disposed, and those skilled in the art may select an appropriate material layer to form the word line 12 of the present application according to actual circumstances.
Specifically, in an embodiment, the forming the trench includes: an etching mask layer is arranged on the source surface 130 and the insulation isolation surface 21, and the etching mask layer is a silicon nitride layer 02, so that the structure shown in fig. 2 is formed; with a composition comprising carbon tetrafluoride (CF)4) And trifluoromethane (CHF)3) The silicon nitride layer 02 and a part of the isolation structure 20 are removed by etching with the etching gas to form the trench, and in the process, the following reaction occurs:
Si3N4(s)+CF4→SiF4(g)+CN(g)
Si3N4(s)+CHF3(g)→SiF4(g)+CN(g)+HF(g)
SiO2(s)+CF4(g)→SiF4(g)+CO(g)
SiO2(s)+CHF3(g)↑→SiF4(g)+CO(g)+HF(g)
and, as shown in FIG. 9, with CHF3And CF4The etching selectivity of silicon nitride to silicon oxide is gradually increased, for example, in CHF3/CF4When the etching selectivity ratio is 0.3, the etching selectivity ratio of silicon nitride to silicon oxide is 5; in CHF3/CF4At 0.5, the etching selectivity of silicon nitride to silicon oxide is 6; in CHF3/CF4When the etching selectivity ratio is 0.8, the etching selectivity ratio of silicon nitride to silicon oxide is 8; in CHF3/CF4When the etching selectivity is 1, the etching selectivity of the silicon nitride to the silicon oxide is 10; in CHF3/CF4At 1.2, the etch selectivity of silicon nitride to silicon oxide is 15.
To further ensure that the trench formed is closer to the predetermined shape and size, in one embodiment of the present application, the CHF is as described above3And CF4The volume ratio of (A) to (B) is 0.8 to 1.2.
As shown in fig. 10, the etching selectivity of silicon nitride to silicon oxide increases with increasing pressure, and at a pressure of 50mTorr in the etching reaction chamber, the etching selectivity of silicon nitride to silicon oxide is 2.5; when the pressure in the etching reaction cavity is 100mTorr, the etching selection ratio of the silicon nitride to the silicon oxide is 5; when the pressure in the etching reaction cavity is 150mTorr, the etching selection ratio of the silicon nitride to the silicon oxide is 10; the etch selectivity ratio of silicon nitride to silicon oxide was 20 at a pressure of 200mTorr in the etch reaction chamber.
In yet another embodiment of the present application, the process of forming the trench by etching is performed in an etching reaction chamber, and in the process of forming the trench by etching, the pressure of the etching reaction chamber is controlled to be greater than or equal to 100mTorr, so that the reaction in the reaction chamber is biased to a chemical reaction, the etching reaction is accelerated, and the trench with a predetermined shape and size is rapidly formed.
In order to open the silicon nitride layer 02 at a faster speed and avoid the critical dimension (width in fig. 3) of the trench from being too large and too deep, thereby ensuring that the formed trench is closer to a predetermined shape and dimension, in an embodiment of the present application, the voltage output power of the etching reaction chamber is controlled to be 350-450W during the process of etching the trench.
In order to further ensure the good electrical performance of the formed memory device, in one embodiment of the present application, as shown in fig. 4, the bit line conductor layer 40 includes a titanium nitride layer 41 and a tungsten layer 42 sequentially stacked in a direction away from the bit line contact layer 30.
Of course, the bit line conductor layer 40 of the present application is not limited to the two layers described above, and may have a one-layer structure; the bit line conductor layer 40 of the present invention is not limited to the two material layers described above, and may be another material layer having a good conductivity. Those skilled in the art can select suitable conductive materials to form the bit line conductor layer 40 according to practical situations.
In a specific embodiment, the etching process of the bit line conductor layer 40 including the titanium nitride layer 41 and the tungsten layer 42 includes: using sulfur hexafluoride (SF)6) The etching process is performed in the reaction chamber, and the reaction occurring in the reaction chamber includes the following two reactions:
SF6→F+SFx(g)
W+6F→WF6(g)
then, with a solution containing Cl2Etching the titanium nitride layer 41 to remove a portion of the titanium nitride layer, and forming the structure shown in fig. 12, wherein the etching process is performed in a reaction chamber, and the reaction is performed in the reaction chamber: cl2+TiN→TiCl4+N。
In order to further avoid damage to the portions of the bit line contact layer 30 and the conductor layer 40 that need to be remained in the process of etching the bit line contact layer 30 and the bit line conductor layer 40, in an embodiment of the present application, after depositing the bit line conductor layer 40 and before etching the portions of the bit line contact layer 30 and the bit line conductor layer 40, the manufacturing process further includes: a barrier layer 50 is deposited on the surface of the bit line conductor layer 40 remote from the bit line contact layer 30, as shown in fig. 4. Before removing part of the bit line conductor layer 40, the manufacturing process further includes: and etching and removing a part of the barrier layer 50 outside the bit line pattern according to the bit line pattern to form a barrier part 500 shown in fig. 5.
In another embodiment of the present invention, in order to further ensure the formation of the bit line with the predetermined shape, in an embodiment of the present invention, as shown in fig. 4, the barrier layer 50 includes a silicon nitride film 51 and a silicon oxide film 52 sequentially stacked in a direction away from the bit line conductor layer 40.
Of course, the barrier layer 50 of the present application is not limited to the two film structure layers, but may also be a structural film, such as only the silicon nitride film 51; the specific materials are not limited to the two types described above, and other insulating materials that can provide a favorable protective effect on the pre-protected region may be used.
The upper surface of the substrate further includes a drain surface of the active region 13, and after depositing the barrier layer 50 and before removing a portion of the barrier layer 50, the manufacturing process further includes: a mask pattern layer 80 is disposed on the surface of the blocking layer 50 away from the bit line conductor layer 40, the pattern of the mask pattern layer 80 corresponds to the bit line pattern, as shown in fig. 13, the mask pattern layer 80 covers the structure above the drain surface and exposes the structure above the source surface 130. The mask pattern layer 80 is a photoresist pattern layer, and generally, the formation process of the layer includes: a photoresist layer is deposited, and then a photoresist pattern layer is formed through photoetching and developing.
In order to further ensure the formation of the bit line with a predetermined shape, the etching gas ratio of the over-etching step is different from the etching gas ratio of the main etching step, so that the width of the middle portion of the bit line contact 300 is not less than 60% of the width of the top portion of the bit line contact 300, and the bit line contact residue 30A on the insulating isolation surface 21 is completely removed.
In another exemplary embodiment of the present application, a method for manufacturing a memory element is provided, where the method includes a process for manufacturing a bit line of the memory element.
The manufacturing method comprises the manufacturing process of the bit line, so that the size of the bit line in the manufactured memory element is in a preset size range, and the memory element is ensured to have better electrical performance.
In another exemplary embodiment of the present application, a memory device is provided, which includes a bit line, and the bit line is fabricated by the above-mentioned fabrication process of the bit line of the memory device. The dimension of the bit line of the memory element is within a predetermined dimension range, which ensures that the memory element has better electrical performance.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the manufacturing process of the bit line, etching gas is adopted to etch part of the bit line contact layer 30, HBr and O2Will react with the Si/SiO in the bit line contact layer 30 to form the SiOxBry polymer 60, i.e., reaction Si/SiO + O occurs2+ HBr → SiOxBry, SiOxBry can protect the sidewall of the bit line contact 300, so that during the etching process of the bit line, the side etching of the bit line contact 300 is relieved or eliminated, the problem of higher resistance caused by the more serious side etching of the bit line contact 300 is avoided, and the memory device has the performance of higher response speed and the like.
2) According to the manufacturing method of the memory element, due to the fact that the manufacturing process of the bit line is included, the size of the bit line in the manufactured memory element is within a preset size range, and the memory element is guaranteed to have good electrical performance.
3) Due to the adoption of the manufacturing method, the formed storage element is ensured to have better electrical property.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (17)

1. A process for fabricating a bit line for a memory element, the process comprising:
providing a base, wherein the base comprises a semiconductor substrate and an isolation structure arranged in the semiconductor substrate, the isolation structure is used for isolating a plurality of active regions of the semiconductor substrate, and the upper surface of the base comprises a source electrode surface of the active regions and an insulation isolation surface of the isolation structure;
depositing a bit line contact layer and a bit line conductor layer on the surface of the source electrode and the insulation isolation surface in sequence, wherein the bit line contact layer covers the surface of the source electrode and the insulation isolation surface between the surfaces of the adjacent source electrodes; and
and sequentially carrying out patterned etching on the bit line conductor layer and the bit line contact layer outside the bit line pattern according to the bit line pattern to expose part of the upper surface of the semiconductor substrate, wherein the removed bit line conductor layer is formed into a bit line conductor, and the process of etching the bit line conductor layer comprises a main etching step and an over etching step, in the main etching step, the removed bit line contact layer is formed into a bit line contact on the surface of the source electrode, in the over etching step, bit line contact residues of the bit line contact layer between two adjacent bit line contacts and on the insulation isolation surface are removed by etching gas controlled by side etching, wherein the etching gas contains hydrogen bromide and oxygen, and the material of the bit line contact layer contains Si or SiO.
2. The process of claim 1, wherein the isolation surface is recessed to form a trench, and after the over-etching step, the bit line contact has a undercut depth equal to or less than a surface undercut depth of the isolation surface.
3. The process of claim 2, wherein the material of the bit line contact layer comprises polysilicon.
4. The process of claim 3, wherein the main etching step of the bit line contact layer over the semiconductor substrate comprises:
and etching and removing part of the bit line contact layer above the semiconductor substrate by using etching gas comprising hydrogen bromide, chlorine and oxygen to form the bit line contact.
5. The process of claim 4, wherein the volume ratio of hydrogen bromide, chlorine and oxygen in the etching gas used for the main etching step of the bit line contact layer on the semiconductor substrate is in the range of (85-95): (4-10): (1-5).
6. The manufacturing process according to claim 1, wherein in the over-etching step, the cross-sectional profile of the bit line contact depends on the amount of oxygen introduced in the over-etching step, and in the over-etching step, the increase of the amount of oxygen introduced accelerates the generation of a side etching protective film.
7. The manufacturing process according to claim 3, wherein in the etching gas of the over-etching step for removing the bit line contact residue, the volume ratio of hydrogen bromide to oxygen is (45-55): (2-8).
8. The process of claim 7, wherein the etching gas for the over-etching step for removing the bit line contact residue further comprises helium, and the volume ratio of hydrogen bromide to oxygen to helium is in the range of (45-55): (2-8): (40-50).
9. The process of claim 3, wherein a main etching step for forming the bit line contact is performed in an etching reaction chamber, and the pressure in the etching reaction chamber is controlled to be less than or equal to 10mTorr in the main etching step; the over-etch step of removing the bitline contact residue (30A) controls the pressure of the etch reaction chamber to be greater than or equal to 50 mTorr.
10. The fabrication process of claim 1, wherein the process of providing the substrate comprises:
providing the semiconductor substrate, and forming a groove in the semiconductor substrate;
arranging the isolation structure in the groove, wherein the insulation isolation surface is at least flush with the surface of the source electrode; and
and etching to remove part of the isolation structure, so that the insulation isolation surface is inwards recessed to form a groove.
11. The process of claim 10, wherein said forming said trench comprises:
arranging an etching mask layer on the surface of the source electrode and the insulating isolation surface, wherein the etching mask layer is a silicon nitride layer; and
and etching and removing the etching mask layer and part of the isolation structure by using etching gas containing carbon tetrafluoride and trifluoromethane to form the groove, wherein the volume ratio of the trifluoromethane to the carbon tetrafluoride is 0.8-1.2.
12. The manufacturing process according to claim 1, wherein the bit line conductor layer comprises a titanium nitride layer and a tungsten layer which are sequentially stacked along a direction away from the bit line contact layer; the process of etching the bit line conductor layer comprises the following steps:
etching and removing part of the tungsten layer by using etching gas containing sulfur hexafluoride; and
and etching and removing part of the titanium nitride layer by using etching gas comprising chlorine.
13. The fabrication process of claim 1, wherein after depositing the bit line conductor layer and before etching portions of the bit line conductor layer and the bit line contact layer, the fabrication process further comprises:
depositing a barrier layer on the surface of the bit line conductor layer far away from the bit line contact layer, wherein the barrier layer comprises a silicon nitride film layer and a silicon oxide film layer which are sequentially overlapped in the direction far away from the bit line conductor layer;
before removing part of the bit line conductor layer, the manufacturing process further includes:
and etching and removing part of the barrier layer outside the bit line pattern according to the bit line pattern to form a barrier part.
14. The process of claim 13, wherein the upper surface of the substrate further comprises a drain surface of the active region, and wherein after depositing the barrier layer and before removing a portion of the barrier layer, the process further comprises:
and arranging a mask pattern layer on the surface of the barrier layer far away from the bit line conductor layer, wherein the mask pattern layer covers the structure above the surface of the drain electrode and exposes the structure above the surface of the source electrode.
15. The process according to any one of claims 1 to 14, wherein the etching gas composition of the over-etching step is different from the etching gas composition of the main etching step, so that the width of the middle portion of the bit line contact is not less than 60% of the width of the top portion of the bit line contact, and the bit line contact residue on the insulating isolation surface is completely removed.
16. A method of manufacturing a memory element, comprising a process of manufacturing a bit line of the memory element according to claim 1.
17. A memory element comprising a bit line, wherein the bit line is fabricated using the process of fabricating a bit line for a memory element according to claim 1.
CN201810072900.5A 2018-01-25 2018-01-25 Process for fabricating bit line of memory device, memory device and method of fabricating the same Active CN110085551B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810072900.5A CN110085551B (en) 2018-01-25 2018-01-25 Process for fabricating bit line of memory device, memory device and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810072900.5A CN110085551B (en) 2018-01-25 2018-01-25 Process for fabricating bit line of memory device, memory device and method of fabricating the same

Publications (2)

Publication Number Publication Date
CN110085551A CN110085551A (en) 2019-08-02
CN110085551B true CN110085551B (en) 2021-05-25

Family

ID=67412029

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810072900.5A Active CN110085551B (en) 2018-01-25 2018-01-25 Process for fabricating bit line of memory device, memory device and method of fabricating the same

Country Status (1)

Country Link
CN (1) CN110085551B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110556359A (en) * 2019-09-17 2019-12-10 福建省晋华集成电路有限公司 Bit line structure and semiconductor memory
CN117177552A (en) * 2022-05-23 2023-12-05 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof
CN115050700A (en) * 2022-06-15 2022-09-13 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020115276A1 (en) * 2000-02-21 2002-08-22 Kazuyoshi. Yoshida A method of etching polycrystalline silicon film by using two consecutive dry-etching processes
US20030134472A1 (en) * 2001-12-22 2003-07-17 In Kwon Yang Method of manufacturing a flash memory cell
CN1494117A (en) * 2002-09-27 2004-05-05 ������������ʽ���� Method for etching polycrystalline silicon

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697123A (en) * 1992-09-14 1994-04-08 Sony Corp Dry etching method
JP2822952B2 (en) * 1995-08-30 1998-11-11 日本電気株式会社 Method for manufacturing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020115276A1 (en) * 2000-02-21 2002-08-22 Kazuyoshi. Yoshida A method of etching polycrystalline silicon film by using two consecutive dry-etching processes
US20030134472A1 (en) * 2001-12-22 2003-07-17 In Kwon Yang Method of manufacturing a flash memory cell
CN1494117A (en) * 2002-09-27 2004-05-05 ������������ʽ���� Method for etching polycrystalline silicon

Also Published As

Publication number Publication date
CN110085551A (en) 2019-08-02

Similar Documents

Publication Publication Date Title
US8377829B2 (en) Method of manufacturing a capacitor deep trench and of etching a deep trench opening
CN110085551B (en) Process for fabricating bit line of memory device, memory device and method of fabricating the same
KR100954107B1 (en) Method for manufacturing semiconductor device
JP2009164553A (en) Flash memory device and method of fabricating the same
US20080213990A1 (en) Method for forming gate electrode in semiconductor device
TWI681551B (en) Methods for processing chip, manufacturing storage structure and processing 3d-nand structure
CN112951760B (en) Memory and forming method thereof
KR100505450B1 (en) Method for fabricating semiconductor device using damascene process
US7718499B2 (en) Method of fabricating a semiconductor device
KR100667653B1 (en) Semiconductor device and method of manufacturing the same
CN111769112A (en) Semiconductor structure for three-dimensional memory element and manufacturing method thereof
KR100927777B1 (en) Manufacturing Method of Memory Device
TWI817903B (en) Method of manufacturing semiconductor device
KR20000002719A (en) Semiconductor device production method to improve contact resistance of silicide
US20060094235A1 (en) Method for fabricating gate electrode in semiconductor device
KR100290587B1 (en) Semiconductor device manufacturing method
KR20080100548A (en) Method for forming contact in semiconductor device
KR100967025B1 (en) Method for manufacturing flash memory device
KR100701425B1 (en) Method for fabrication of semiconductor device
KR100976684B1 (en) Method for forming the contact hall of semiconductor memory device
KR20040001480A (en) Method for forming landing plug
KR20070007491A (en) Semiconductor device and method of manufacturing the same
JP2012079926A (en) Method of manufacturing semiconductor device
KR100917057B1 (en) Method for forming a capacitor of a semiconductor device
KR20050116665A (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant