CN110556359A - Bit line structure and semiconductor memory - Google Patents
Bit line structure and semiconductor memory Download PDFInfo
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- CN110556359A CN110556359A CN201910875708.4A CN201910875708A CN110556359A CN 110556359 A CN110556359 A CN 110556359A CN 201910875708 A CN201910875708 A CN 201910875708A CN 110556359 A CN110556359 A CN 110556359A
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- semiconductor memory
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000004020 conductor Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 abstract description 37
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 238000000034 method Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 254
- 238000010586 diagram Methods 0.000 description 16
- 230000015654 memory Effects 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000033116 oxidation-reduction process Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The invention discloses a bit line structure and a semiconductor memory, comprising: a substrate; the bit lines comprise a contact layer and a conducting wire layer which are sequentially overlapped from the substrate, the vertical projection of the contact layer on the substrate is positioned in the vertical projection of the conducting wire layer on the substrate, and the width of the contact layer in the cross section is smaller than that of the conducting wire layer in the cross section. According to the technical scheme provided by the invention, the wire layer is used as a mask when the bit line structure is manufactured, then the material structure layer where the contact layer is located is etched, and finally the contact layer with the cross section width smaller than that of the wire layer is manufactured. Because the conducting wire layer is used as the mask layer and the corresponding mask layer when the contact layer is etched does not need to be separately prepared, the manufacture procedure of the bit line structure is further reduced, namely, the manufacture procedure of the semiconductor memory is reduced, and the manufacture cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a bit line structure and a semiconductor memory.
background
Nowadays, electronic devices such as computers and mobile phones do not have memories, which are devices capable of storing data and reading out data according to address codes, and the memories are classified into two categories, namely magnetic memories and semiconductor memories. The basic structure of the semiconductor memory is a memory cell array and other circuits, the memory cell array is a main body of the semiconductor memory, and each memory cell is positioned at the intersection of a word line and a bit line and is used for storing data; the other is composed of an address code buffer at the input end, a row decoder, a read amplifier, a column decoder, an output buffer and the like. When the semiconductor memory reads out data, firstly, an address code signal is sent to a row decoder and then to a word line through an address code buffer, then a word line is selected by the row decoder, then the data obtained on a bit line is amplified through a sense amplifier, one sense amplifier is selected by a column decoder, and the amplified signal is output through a multi-output buffer. When writing data, it is necessary to first supply the data to the bit line selected by the column decoder and then store the data in the memory cell where the bit line intersects the word line.
Semiconductor memories are widely used in the electronics industry today due to their small size, multiple functions, and low manufacturing cost. Although the semiconductor memory has the above advantages, the process is complicated and needs to be improved.
Disclosure of Invention
in view of the above, the present invention provides a bit line structure and a semiconductor memory, which effectively solve the existing technical problems, reduce the manufacturing process of the semiconductor memory, and reduce the manufacturing cost.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
A bit line architecture, comprising:
A substrate;
The bit lines comprise a contact layer and a conducting wire layer which are sequentially overlapped from the substrate, the vertical projection of the contact layer on the substrate is positioned in the vertical projection of the conducting wire layer on the substrate, and the width of the contact layer in the cross section is smaller than that of the conducting wire layer in the cross section.
Optionally, the bit line structure further includes: and the auxiliary layer wraps the side face of the contact layer.
optionally, the auxiliary layer is an oxide layer.
optionally, the material of the oxide layer is SiO 2.
Optionally, a ratio of a total width of the auxiliary layer to the contact layer in the cross section to a width of the wire layer in the cross section is in a range of 0.9 to 1.1.
optionally, the conductive line layer includes a first bit line conductive layer, a second bit line conductive layer, and a bit line capping film sublayer, which are sequentially stacked from the contact layer.
Accordingly, the present invention also provides a semiconductor memory comprising:
A substrate including a plurality of active regions defined by a device isolation layer;
The insulating layer is positioned on one side of the substrate, which is provided with the device isolating layer, a plurality of bit line contact grooves are formed in the insulating layer, and the bit line contact grooves expose the active region;
The semiconductor device comprises a plurality of first bit lines and second bit lines, wherein the first bit lines are formed on the surface of one side, away from the substrate, of the insulating layer, the second bit lines are formed in bit line contact grooves, the first bit lines and the second bit lines respectively comprise contact layers and lead layers which are sequentially overlapped from one side of the substrate, the vertical projection of the contact layers on the substrate is located in the vertical projection of the lead layers on the substrate, and the width of the contact layers in the cross section is smaller than that of the lead layers in the cross section.
optionally, the semiconductor memory further includes: and the auxiliary layer wraps the side face of the contact layer.
Optionally, the auxiliary layer is an oxide layer.
Optionally, the material of the oxide layer is SiO 2.
optionally, a ratio of a total width of the auxiliary layer to the contact layer in the cross section to a width of the wire layer in the cross section is in a range of 0.9 to 1.1.
optionally, the conductive line layer includes a first bit line conductive layer, a second bit line conductive layer, and a bit line capping film sublayer, which are sequentially stacked from the contact layer.
Optionally, a top surface of a side of the contact layer of the second bit line facing away from the substrate is higher than a surface of a side of the insulating layer facing away from the substrate.
Optionally, a top surface of a side of the contact layer of the second bit line facing away from the substrate is flush with a top surface of a side of the contact layer of the first bit line facing away from the substrate.
Optionally, a top surface of a side of the conductive line layer of the first bit line facing away from the substrate is flush with a top surface of a side of the conductive line layer of the second bit line facing away from the substrate.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a bit line structure and a semiconductor memory, comprising: a substrate; the bit lines comprise a contact layer and a conducting wire layer which are sequentially overlapped from the substrate, the vertical projection of the contact layer on the substrate is positioned in the vertical projection of the conducting wire layer on the substrate, and the width of the contact layer in the cross section is smaller than that of the conducting wire layer in the cross section.
according to the technical scheme provided by the invention, the wire layer is used as a mask when the bit line structure is manufactured, then the material structure layer where the contact layer is located is etched, and finally the contact layer with the cross section width smaller than that of the wire layer is manufactured. Because the conducting wire layer is used as the mask layer and the corresponding mask layer when the contact layer is etched does not need to be separately prepared, the manufacture procedure of the bit line structure is further reduced, namely, the manufacture procedure of the semiconductor memory is reduced, and the manufacture cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a bit line structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another bit line structure according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another bit line structure according to an embodiment of the present application;
Fig. 4 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present application;
FIG. 5 is a schematic structural diagram of another semiconductor memory according to an embodiment of the present disclosure;
FIG. 6 is a schematic structural diagram of another semiconductor memory according to an embodiment of the present application;
FIG. 7 is a schematic structural diagram of another semiconductor memory device according to an embodiment of the present application;
Fig. 8 is a schematic structural diagram of another semiconductor memory according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, electronic devices such as computers and mobile phones are not provided with memories, i.e., devices capable of storing data and reading out data according to address codes, and the memories are classified into two categories, i.e., magnetic memories and semiconductor memories. Semiconductor memories are widely used in the electronics industry today due to their small size, multiple functions, and low manufacturing cost. Although the semiconductor memory has the above advantages, the process is complicated and needs to be improved.
Accordingly, the embodiment of the application provides a bit line structure and a semiconductor memory, which effectively solve the existing technical problems, reduce the manufacturing process of the semiconductor memory and reduce the manufacturing cost. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 8.
referring to fig. 1, a schematic structural diagram of a bit line structure according to an embodiment of the present disclosure is shown, where the bit line structure includes:
A substrate 100;
the bit lines are located on the substrate 100, wherein the bit lines include a contact layer 210 and a conductive line layer 220, which are sequentially stacked from the substrate, a vertical projection of the contact layer 210 on the substrate 100 is located in a vertical projection of the conductive line layer 220 on the substrate 210, and a width d1 of the contact layer 210 in the cross section is smaller than a width d2 of the conductive line layer 220 in the cross section.
In an embodiment of the present application, the substrate provided in the present application may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate, etc., and the present application is not particularly limited thereto. The bit line is formed on the substrate, after the contact material structure layer and the conducting wire material structure layer are sequentially formed, the conducting wire structure material layer is firstly etched to obtain a conducting wire layer, then the conducting wire layer is used as a mask to etch the contact material layer, and the contact layer with the section width smaller than that of the conducting wire layer is obtained.
it can be understood that in the technical scheme provided by the embodiment of the application, the wire layer is used as a mask when the bit line structure is manufactured, then the material structure layer where the contact layer is located is etched, and finally the contact layer with the cross section width smaller than that of the wire layer is manufactured. Because the conducting wire layer is used as the mask layer and the corresponding mask layer when the contact layer is etched does not need to be separately prepared, the manufacture procedure of the bit line structure is further reduced, namely, the manufacture procedure of the semiconductor memory is reduced, and the manufacture cost is reduced.
Further, referring to fig. 2, a schematic structural diagram of another bit line structure provided in the embodiment of the present application is shown, where the bit line structure includes: a substrate 100;
The bit lines are located on the substrate 100, wherein the bit lines include a contact layer 210 and a conductive line layer 220, which are sequentially stacked from the substrate, a vertical projection of the contact layer 210 on the substrate 100 is located in a vertical projection of the conductive line layer 220 on the substrate 210, and a width d1 of the contact layer 210 in the cross section is smaller than a width d2 of the conductive line layer 220 in the cross section.
And, the bit line structure that this application embodiment provided still includes: an auxiliary layer 300 wrapping the side of the contact layer 210.
It can be understood that, as shown in fig. 2, the contact layer 210 provided in the embodiment of the present application is further wrapped by an auxiliary layer 300, and when the material filling 400 is performed on the side of the subsequent alignment line structure having the bit line, the width d3 of the structure layer below the conductive line layer (compared with the structure layer having only the contact layer 210 without the auxiliary layer 300) is increased because the auxiliary layer 300 wraps the contact layer 210, thereby reducing the area to be filled at the outer side of the auxiliary layer 300 (as shown by the dashed-line frame in the figure), reducing the difficulty of material filling at the outer side of the auxiliary layer 300, reducing the probability of occurrence of voids when the outer side of the auxiliary layer 300 is filled with the material, and improving the filling quality.
In an embodiment of the present application, the auxiliary layer provided in the present application may be an oxide layer. In the embodiment of the present application, the auxiliary layer made of an oxide may be obtained by performing oxidation reduction on the outer side of the contact layer, and the present application is not particularly limited. It should be noted that, in other embodiments of the present application, the auxiliary layer may be made of other materials and may be manufactured by other types of processes, which need to be specifically designed according to practical applications.
Optionally, the material of the oxide layer provided in the embodiment of the present application is SiO 2. The contact layer provided by the embodiment of the application can be made of polycrystalline silicon, and then the outer side of the contact layer made of the polycrystalline silicon is subjected to oxidation-reduction treatment, so that the auxiliary layer made of SiO2 is finally obtained.
Further, in order to improve the manufacturing efficiency and ensure that the probability of voids occurring when the outer side of the auxiliary layer is filled with a material is lower, the ratio of the total width of the cross section of the auxiliary layer to the total width of the contact layer to the width of the cross section of the conductive line layer provided by the embodiment of the present application is in the range of 0.9 to 1.1, inclusive.
referring to fig. 3, a schematic structural diagram of another bit line structure provided in the embodiment of the present application is shown, wherein the conductive line layer 220 provided in the embodiment of the present application includes a first bit line conductive sub-layer 221, a second bit line conductive sub-layer 222, and a bit line capping film sub-layer 223, which are sequentially stacked from the contact layer 210.
In an embodiment of the present application, the materials of the first bit line conductive sub-layer and the second bit line conductive sub-layer provided in the present application may be the same or different, and the present application is not limited thereto. Any one of the first bit line conductive sub-layer and the second bit line conductive sub-layer may include a polysilicon layer, a conductive metal nitride layer (such as titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal layer (such as a single layer formed by any one of tungsten, titanium, tantalum, etc., or a stack formed by multiple layers), a conductive alloy (such as a combination alloy of tungsten, titanium, tantalum, etc.), and the like. And, the bit line cap film sub-layer provided by the embodiments of the present application may include, but is not limited to, a silicon nitride film.
Correspondingly, an embodiment of the present application further provides a semiconductor memory, which is shown in fig. 4 and is a schematic structural diagram of another semiconductor memory provided in the embodiment of the present application, where the semiconductor memory includes:
A substrate 10, the substrate 10 including a plurality of active regions 12 defined by a device isolation layer 11;
an insulating layer 20 on the substrate 10 having the device isolation layer 11, the insulating layer 20 having a plurality of bit line contact trenches formed thereon, the bit line contact trenches exposing the active regions 12;
A plurality of first bit lines 31 formed on a surface of the insulating layer 20 facing away from the substrate 10, and a second bit line 32 formed in the bit line contact trench, wherein each of the first bit lines 31 and the second bit line 32 includes a contact layer 331 and a wire layer 332 stacked in sequence from a side of the substrate 10, a perpendicular projection of the contact layer 331 on the substrate 10 is located in a perpendicular projection of the wire layer 332 on the substrate 10, and a width d4 in a cross section of the contact layer 331 is smaller than a width d5 in the cross section of the wire layer 332.
In an embodiment of the present application, the substrate provided in the present application may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate, and the like, and the present application is not particularly limited. The device isolation layer is filled between the active regions, and is made of an insulating material, such as silicon oxide, silicon nitride and/or silicon oxynitride. The bit line provided by the present application is formed on a substrate, and specifically may be: after the contact material structure layer and the conducting wire material structure layer are formed in sequence, firstly, the conducting wire structure material layer is etched to obtain a conducting wire layer, then, the conducting wire layer is used as a mask to etch the contact material layer, and the contact layer with the section width smaller than that of the conducting wire layer is obtained.
It should be noted that the semiconductor memory provided in the embodiments of the present application further includes structures such as word lines, which are the same as those in the prior art, and therefore redundant description is not repeated in the present application.
it can be understood that in the technical scheme provided by the embodiment of the application, the wire layer is used as a mask when the bit line structure is manufactured, then the material structure layer where the contact layer is located is etched, and finally the contact layer with the cross section width smaller than that of the wire layer is manufactured. Because the conducting wire layer is used as the mask layer and the corresponding mask layer when the contact layer is etched does not need to be separately prepared, the manufacture procedure of the bit line structure is further reduced, namely, the manufacture procedure of the semiconductor memory is reduced, and the manufacture cost is reduced.
Further, referring to fig. 5, a schematic structural diagram of another semiconductor memory provided in the embodiment of the present application is shown, where the semiconductor memory includes: a substrate 10, the substrate 10 including a plurality of active regions 12 defined by a device isolation layer 11;
an insulating layer 20 on the substrate 10 having the device isolation layer 11, the insulating layer 20 having a plurality of bit line contact trenches formed thereon, the bit line contact trenches exposing the active regions 12;
A plurality of first bit lines 31 formed on a surface of the insulating layer 20 facing away from the substrate 10, and a second bit line 32 formed in the bit line contact trench, wherein each of the first bit lines 31 and the second bit line 32 includes a contact layer 331 and a wire layer 332 stacked in sequence from a side of the substrate 10, a perpendicular projection of the contact layer 331 on the substrate 10 is located in a perpendicular projection of the wire layer 332 on the substrate 10, and a width d4 in a cross section of the contact layer 331 is smaller than a width d5 in the cross section of the wire layer 332.
And, the semiconductor memory provided by the embodiment of the present application further includes: and an auxiliary layer 30 wrapping the side of the contact layer 331.
it can be understood that, as shown in fig. 5, the contact layer 331 provided in the embodiment of the present application is further wrapped by an auxiliary layer 30, and further when the subsequent bit line structure has a bit line side for material filling 40, the auxiliary layer 30 wraps the contact layer 331, so that the width d6 of the structure layer below the conductive line layer (compared with the structure layer having only the contact layer 331 but no auxiliary layer 30) is increased, thereby reducing the area to be filled at the outer side of the auxiliary layer 30 (as shown in the dashed-line frame in the figure), reducing the difficulty of material filling at the outer side of the auxiliary layer 30, reducing the probability of occurrence of voids when the outer side of the auxiliary layer 30 is filled with the material, and improving the filling quality.
In an embodiment of the present application, the auxiliary layer provided in the present application may be an oxide layer. In the embodiment of the present application, the auxiliary layer made of an oxide may be obtained by performing oxidation reduction on the outer side of the contact layer, and the present application is not particularly limited. It should be noted that, in other embodiments of the present application, the auxiliary layer may be made of other materials and may be manufactured by other types of processes, which need to be specifically designed according to practical applications.
Optionally, the material of the oxide layer provided in the embodiment of the present application is SiO 2. The contact layer provided by the embodiment of the application can be made of polycrystalline silicon, and then the outer side of the contact layer made of the polycrystalline silicon is subjected to oxidation-reduction treatment, so that the auxiliary layer made of SiO2 is finally obtained.
Further, in order to improve the manufacturing efficiency and ensure that the probability of voids occurring when the outer side of the auxiliary layer is filled with a material is lower, the ratio of the total width of the cross section of the auxiliary layer to the total width of the contact layer to the width of the cross section of the conductive line layer provided by the embodiment of the present application is in the range of 0.9 to 1.1, inclusive.
referring to fig. 6, a schematic structural diagram of another semiconductor memory provided in this embodiment is shown, wherein the conductive line layer 332 includes a first bit line conductive sub-layer 3321, a second bit line conductive sub-layer 3322, and a bit line capping film sub-layer 3323, which are sequentially stacked from the contact layer 331.
In an embodiment of the present application, the materials of the first bit line conductive sub-layer and the second bit line conductive sub-layer provided in the present application may be the same or different, and the present application is not limited thereto. Any one of the first bit line conductive sub-layer and the second bit line conductive sub-layer may include a polysilicon layer, a conductive metal nitride layer (such as titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal layer (such as a single layer formed by any one of tungsten, titanium, tantalum, etc., or a stack formed by multiple layers), a conductive alloy (such as a combination alloy of tungsten, titanium, tantalum, etc.), and the like. And, the bit line cap film sub-layer provided by the embodiments of the present application may include, but is not limited to, a silicon nitride film.
referring to fig. 7, a schematic structural diagram of another semiconductor memory provided in this embodiment of the present application is shown, wherein a top surface of the contact layer 331 of the second bit line 32 facing away from the substrate 10 is higher than a surface of the insulating layer 20 facing away from the substrate 10.
It can be understood that after the bit line contact trench is formed in the insulating layer and the substrate, the contact material structure layer can be manufactured on one side of the insulating layer, wherein after the bit line contact trench is completely filled in the contact material structure layer and is higher than the insulating layer by a preset height range, the conductor material structure layer is continuously manufactured on the contact material structure layer, then the contact layer and the conductor layer are respectively manufactured, and finally the top surface of the contact layer of the second bit line in the bit line contact trench is higher than the surface of the insulating layer.
Referring to fig. 8, a schematic structural diagram of another semiconductor memory provided in this embodiment is shown, wherein a top surface of the contact layer 331 of the second bit line 32 facing away from the substrate 10 is flush with a top surface of the contact layer 331 of the first bit line 31 facing away from the substrate 10.
it can be understood that after the bit line contact trench is formed on the insulating layer and the substrate, a contact material structure layer can be manufactured on one side of the insulating layer, wherein the contact material structure layer is a flat structure layer which completely fills the bit line contact trench and is higher than the insulating layer by a preset height; and continuously manufacturing a conducting wire material structure layer on the contact material structure layer, and then respectively manufacturing a contact layer and a conducting wire layer to finally obtain a structure with the top surfaces of the contact layers of the first bit line and the second bit line being flush.
As shown in fig. 7 or 8, in an embodiment of the present application, a top surface of the side of the conductor layer 332 of the first bit line 31 facing away from the substrate 10 is flush with a top surface of the side of the conductor layer 332 of the second bit line 32 facing away from the substrate 10, and the present application is not particularly limited.
An embodiment of the present application provides a bit line structure and a semiconductor memory, including: a substrate; the bit lines comprise a contact layer and a conducting wire layer which are sequentially overlapped from the substrate, the vertical projection of the contact layer on the substrate is positioned in the vertical projection of the conducting wire layer on the substrate, and the width of the contact layer in the cross section is smaller than that of the conducting wire layer in the cross section.
According to the technical scheme provided by the embodiment of the application, the wire layer is used as a mask when the bit line structure is manufactured, then the material structure layer where the contact layer is located is etched, and finally the contact layer with the cross section width smaller than that of the wire layer is manufactured. Because the conducting wire layer is used as the mask layer and the corresponding mask layer when the contact layer is etched does not need to be separately prepared, the manufacture procedure of the bit line structure is further reduced, namely, the manufacture procedure of the semiconductor memory is reduced, and the manufacture cost is reduced.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. A bit line structure, comprising:
A substrate;
The bit lines comprise a contact layer and a conducting wire layer which are sequentially overlapped from the substrate, the vertical projection of the contact layer on the substrate is positioned in the vertical projection of the conducting wire layer on the substrate, and the width of the contact layer in the cross section is smaller than that of the conducting wire layer in the cross section.
2. The bit line structure of claim 1, further comprising: and the auxiliary layer wraps the side face of the contact layer.
3. The bit line structure of claim 1, wherein the assist layer is an oxide layer.
4. The bit line structure of claim 3, wherein the oxide layer is made of SiO 2.
5. the bit line structure of claim 1, wherein a ratio of a total width of the auxiliary layer to the contact layer in a cross section to a width of the conductive line layer in the cross section is in a range of 0.9-1.1.
6. The bit line structure of claim 1, wherein the conductor layer comprises a first bit line conductor layer, a second bit line conductor layer, and a bit line capping film layer stacked in this order from the contact layer.
7. A semiconductor memory, comprising:
A substrate including a plurality of active regions defined by a device isolation layer;
The insulating layer is positioned on one side of the substrate, which is provided with the device isolating layer, a plurality of bit line contact grooves are formed in the insulating layer, and the bit line contact grooves expose the active region;
The semiconductor device comprises a plurality of first bit lines and second bit lines, wherein the first bit lines are formed on the surface of one side, away from the substrate, of the insulating layer, the second bit lines are formed in bit line contact grooves, the first bit lines and the second bit lines respectively comprise contact layers and lead layers which are sequentially overlapped from one side of the substrate, the vertical projection of the contact layers on the substrate is located in the vertical projection of the lead layers on the substrate, and the width of the contact layers in the cross section is smaller than that of the lead layers in the cross section.
8. The semiconductor memory according to claim 7, further comprising: and the auxiliary layer wraps the side face of the contact layer.
9. The semiconductor memory according to claim 7, wherein the auxiliary layer is an oxide layer.
10. The semiconductor memory according to claim 9, wherein the oxide layer is made of SiO 2.
11. The semiconductor memory according to claim 7, wherein a ratio of a total width of the auxiliary layer to the contact layer in a cross section to a width of the conductive line layer in a cross section is in a range of 0.9 to 1.1.
12. The semiconductor memory according to claim 7, wherein the conductor layer comprises a first bit line conductor layer, a second bit line conductor layer, and a bit line capping film layer, which are stacked in this order from the contact layer.
13. the semiconductor memory according to claim 7, wherein a top surface of a side of the contact layer of the second bit line facing away from the substrate is higher than a surface of a side of the insulating layer facing away from the substrate.
14. the semiconductor memory according to claim 7, wherein a top surface of a side of the contact layer of the second bit line facing away from the substrate is flush with a top surface of a side of the contact layer of the first bit line facing away from the substrate.
15. The semiconductor memory according to claim 7, wherein a top surface of a side of the wiring layer of the first bit line facing away from the substrate is flush with a top surface of a side of the wiring layer of the second bit line facing away from the substrate.
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