CN104576503A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN104576503A CN104576503A CN201310522011.1A CN201310522011A CN104576503A CN 104576503 A CN104576503 A CN 104576503A CN 201310522011 A CN201310522011 A CN 201310522011A CN 104576503 A CN104576503 A CN 104576503A
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- deep trench
- sidewall
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- nitride layer
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
The invention discloses a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; sequentially forming an oxidizing layer and a nitride layer on the semiconductor substrate; patterning the nitride layer, the oxidizing layer and the semiconductor substrate to form a deep trench; oxidizing the bottom and the side wall of the deep trench to form a first oxide layer; performing wet etching to remove the first oxide layer to enable the side wall of the deep trench to recess inwardly relative to the side wall of the nitride layer; oxidizing the bottom and the side wall of the deep trench again to form a second oxide layer which is flush with the side wall of the nitride layer; etching to remove the second oxide layer at the bottom of the deep trench. A thermal oxide spacer formed by the manufacturing process provided by the invention is high in insulation capability; loss is avoided as the top end of the deep trench spacer is protected by a silicon nitride layer; a protective layer of the side wall of the deep trench is uniform, which is greatly beneficial to follow-up filling to avoid the forming of holes.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
Along with the integration (integration) of the inner member of integrated circuit constantly promotes, due to Distance Shortened between adjacent elements, thus the possibility of electronic jamming improves each other, for this reason, suitable isolation structure must be had, to avoid interfering with each other between element.
Generally speaking, particularly for high voltage device, in order to the isolated high voltage device being arranged in low concentration deep-well region or low concentration polysilicon layer, deep trench (deep trench) must be used to reach required isolated degree.
Usually the groove of the degree of depth more than 3 μm is called deep trench, deep groove structure obtains applying comparatively widely in semiconductor technology now, deep trench isolation structure is mainly used in high-power integrated BCD circuit or smart power technology (smart power technology), the isolation that wherein deep trench is good can make various high-low voltage device such as simulate, numeral, high pressure and EE etc. integrate, and can not cause EMI(electromagnetic interference) interference.Such as, deep trench can be used as isolation structure with the electronic device of isolated different operating voltage.Be applied to the electric capacity that can reduce substrate and NPN triode (triode be made up of 2 pieces of N type semiconductor sandwich, one piece of P type semiconductor) in SiGe BiCMOS (SiGe bipolar complementary metal oxide semiconductor) technique, improve the frequency characteristic of device.And for example, deep trench can be applicable to super junction MOS transistor (super junction MOSFET), reaches high-breakdown-voltage performance as PN junction by the charge balance exhausting state.
At present, in fabrication of semiconductor device, etching and the large method of filling deep trench are provide Semiconductor substrate, and form oxide layer and silicon nitride layer on a semiconductor substrate, oxide layer and nitride layer are as hard mask layer; Then, silicon nitride layer forms the photoresist layer of patterning, photoresist layer has deep trench pattern; Again according to photoresist layer etch nitride silicon layer, oxide layer and the Semiconductor substrate successively of patterning, to form deep trench, remove the photoresist layer of patterning; Then, the sidewall of deep trench forms side wall protection oxide layer, what sidewall protected oxide layer can be silicon dioxide side wall (tetraethoxysilane oxide sidewall spacers, TEOS spacer) or thermal oxide side wall (Thermal Oxide spacer); Then, in deep trench, polysilicon layer is filled.Concrete; the method that tradition forms groove side wall is form sidewall oxide layer on the bottom of deep trench and sidewall and silicon nitride layer; adopt anisotropic etching sidewall oxide layer; to retain the sidewall oxide layer being positioned at deep trench sidewall; remove the sidewall oxide layer be positioned at bottom deep trench; finally, in deep trench, side wall protection is formed.
The object being formed in the deep trench side wall protective layer in deep trench is the device isolation for transverse direction, but, three difficult problems can be run in the sidewall protection of the deep trench of prior art, (1) outstanding phenomenon is arranged at the top of side wall protective layer, outstanding phenomenon is had 1. at the top of side wall protective layer, as shown in Figure 1A when side wall protective layer is the dioxide sidewalls adopting chemical deposition process to be formed; Outstanding phenomenon is had 1. at the top of side wall protective layer, as shown in Figure 1B when side wall protective layer is the thermal oxide side wall layer of thermal oxidation technology formation.(2) the anti-etching ability of side wall protective layer in follow-up technique; easy generation depression, if when using the silicon dioxide of thermal oxidation, the oxide layer at top can etch away when side wall protective layer is formed; in as isolation structure, top protective value is bad.(3) side wall protective layer formed due to thermal oxidation technology has the difficulty that polysilicon layer adds hole, can cause the appearance of defects of semiconductor device.
Therefore; propose a kind of method of making deep trench protection side wall newly; there is protrusion phenomenon to avoid the top appearing at sidewall protection oxide layer in the deep trench sidewall protection formed, avoid in follow-up technique, occur that the anti-etching ability of side wall protective layer easily produces depressed phenomenon and avoids the difficulty that polysilicon layer adds hole occurs; cause the problems such as the appearance of defect, with the yields of the performance and device that improve semiconductor device.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprising the following steps, Semiconductor substrate is provided; Form oxide layer and nitride layer successively on the semiconductor substrate; Nitride layer, described oxide layer and described Semiconductor substrate described in patterning, to form deep trench; Be oxidized bottom and the sidewall of described deep trench, to form the first oxide skin(coating); Wet etching removes described first oxide skin(coating), caves inward relative to the sidewall of described nitride layer to make the sidewall of described deep trench; Reoxidize bottom and the sidewall of described deep trench, to form the second oxide skin(coating), described second oxide skin(coating) flushes with the sidewall of described nitride layer; Etching removes described second oxide skin(coating) be positioned at bottom described deep trench.
The invention allows for the another kind of method making semiconductor device, comprising: Semiconductor substrate is provided; Form oxide layer and nitride layer successively on the semiconductor substrate; Nitride layer, described oxide layer and described Semiconductor substrate described in patterning, to form deep trench; Wet-cleaned is adopted to remove the oxide layer of the described deep trench sidewall surfaces of part; Etch the sidewall of described deep trench, cave inward relative to the sidewall of described nitride layer to make the sidewall of described deep trench; Be oxidized bottom and the sidewall of described deep trench, to form oxide skin(coating), described oxide skin(coating) flushes with the sidewall of described nitride layer; Etching removes the described oxide skin(coating) be positioned at bottom described deep trench.
Preferably, anisotropic etching is adopted to remove described second oxide skin(coating) be positioned at bottom described deep trench.
Preferably, anisotropic etching is adopted to remove the described oxide skin(coating) be positioned at bottom described deep trench.
Preferably, wet-etching technology is adopted to etch the sidewall of described deep trench.
Preferably, thermal oxidation technology is adopted to perform described oxidation step.
Preferably, the material of described nitride layer is silicon nitride.
Preferably, the described oxide layer that described wet-cleaned is removed is native oxide layer.
Preferably, the sidewall of deep trench described in dry method or wet etching is adopted.
Preferably, described etching technics has the high etching selection ratio of sidewall to described nitride layer of described deep trench.
In sum, the present invention utilizes the characteristic of silica oxidation consumption silicon to produce a kind of Embedded sidewall protection, also utilize the characteristic that nitride is not oxidized, make nitride protective side wall oxide layer in follow-up sidewall etch process of giving prominence to, the form of deep trench protection side wall in Semiconductor substrate can be optimized according to manufacture craft of the present invention, make the corner of the protection side wall formed more sphering and level and smooth, the thermal oxidation side wall insulating capacity formed can save space by force, the top of deep trench side wall is by silicon nitride layer protection not loss, the protective layer of deep trench side wall is even, follow-up filling is very helpful to avoid producing hole, also the reduction of semiconductor device Width size is contributed to, also the follow-up filling to deep trench is conducive to.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
The cutaway view of the device that Figure 1A-1B obtains for the correlation step making deep trench protection side wall according to prior art
The cutaway view of the device that Fig. 2 A-2D obtains for the correlation step making deep trench isolation structure according to one embodiment of the present invention;
Fig. 3 is the process chart making deep trench isolation structure according to one embodiment of the present invention;
The cutaway view of the device that Fig. 4 A-4D obtains for the correlation step making deep trench isolation structure according to another execution mode of the present invention;
Fig. 5 is the process chart making deep trench isolation structure according to another execution mode of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention improves the technique making semiconductor device structure to solve the problems of the prior art.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
In order to solve the problems of the prior art, the present invention proposes a kind of deep trench that makes and protecting side wall method.With reference to Fig. 2 A to Fig. 2 D, the cutaway view of the correlation step of the embodiment according to one aspect of the invention is shown.
As shown in Figure 2 A, there is provided the bulk silicon substrate 200 that includes source region, the constituent material of Semiconductor substrate 200 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Form oxide layer 201 on semiconductor substrate 200, its main material is silicon dioxide.This oxide layer 201 is formed by thermal oxidation method, and general thickness is 100 ~ 160 dusts, and it is not subject to chemical spot (as isolating oxide layer) to protect active area when removing nitride layer mainly as separator.Oxide layer 201 is formed nitride layer 202; the material preferred nitrogen SiClx of nitride layer; boiler tube deposition process or Low Pressure Chemical Vapor Deposition can be adopted to form silicon nitride layer 202; its thickness is generally 600 ~ 1200 dusts; this nitride layer 202 is mainly used in protecting active area in deposition oxide process in deep trench isolation structure, and can be used as the barrier material of grinding when the silica that cmp is filled.Oxide layer 201 and nitride layer 202 are as the mask defining STI.
Photoetching process is adopted on nitride layer 202 and oxide layer 201, to define deep trench region and active area region, to form opening 303 in nitride layer 202 and oxide layer 201.
In a specific embodiment of the present invention, silicon nitride layer 202 forms hard mask layer, its material is agraphitic carbon, chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition can be adopted to form amorphous carbon layer, hard mask layer is formed dielectric anti-reflective coating (DARC), its material is silicon oxynitride, the method that chemical gas can be adopted to deposit prepares dielectric anti-reflective coating, the object of deposition formation dielectric anti-reflective coating is the reflectivity in order to reduce silicon nitride layer, and dielectric anti-reflective coating is formed the photoresist layer of patterning.
According to photoresist etching dielectrics antireflecting coating, hard mask layer, nitride layer 202 and the oxide layer 201 successively of patterning.Wherein, etching gas can adopt the gas based on chlorine or the gas based on hydrogen bromide or both mists.Adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0 ~ 200 cc/min (sccm), and reative cell internal pressure can be 5 ~ 20 millis millimetres of mercury (mTorr).Then, the photoresist layer of patterning, dielectric anti-reflective coating and hard mask layer is removed, to form opening.Wherein, original position cineration technics (In-situ Asher) is used to remove the photoresist of patterning, dielectric anti-reflective coating and hard mask layer, the gas that cineration technics adopts is preferably oxygen, concrete, silicon semiconductor substrate is inserted in reactive ion etching device, by additional heater such as Halogen lamp LED, in the chamber of direct heating reactive ion etching device, the temperature range of heating is 60 DEG C ~ 250 DEG C, then, use oxygen-containing gas to supply in the chamber of heated reactive ion etching device, described oxygen-containing gas is O
2, O
3, H
2o, N
2o, CH
3oH or its combination in any.The flow of oxygen-containing gas asks 4000 ~ 8000 cc/min (sccm), and ashing power is 300 watts ~ 1200 watts, has also passed into nitrogen and hydrogen simultaneously.
Then, according to the opening etch semiconductor substrates formed in nitride layer 202 and oxide layer 201, to form deep trench 203.The etching agent of usual employing is fluorine-containing gas, such as CF
4or CHF
3.Dry etching can be adopted, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
In an embodiment of the present invention, the opening formed in described nitride layer 202 and oxide layer 201 defines deep trench isolation structural region and active region.
Then, adopt the Semiconductor substrate and oxide layer 201 exposed in oxidation technology process deep trench 203, concrete, oxidation technology process deep trench 203 silicon of deep trench sidewall and bottom in oxidizing process is adopted to be consumed, to form silica (sidewall oxide) 204 on the bottom and sidewall of deep trench 203.
In a specific embodiment of the present invention, adopt the silicon exposed in thermal oxidation (thermal oxidation) process oxidizes deep trench 203, with the silicon of the trenched side-wall and bottom that consume part in oxidizing process to form silica (sidewall oxide) 204.
In a specific embodiment of the present invention, thermal oxidation technology can be film by wet hot oxidation technique or xeothermic oxidation technology, alternatively, by oxygen source as molecular oxygen or/and carry out thermal oxidation technology in the atmosphere of ozone.
It should be noted that, the above-mentioned bottom of oxidation deep trench and the method for sidewall are exemplary, are not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 2 B, adopt etching technics to remove the silica (sidewall oxide) 204 formed in deep trench 203, after etching, the polysilicon layer of deep trench 203 sidewall and silicon oxide layer 202 cave inward relative to nitride layer 202.In the present invention, the preferred wet etching of described etching technics.
The hydrofluoric acid of dilution and phosphoric acid can be adopted to perform wet-etching technology, in a specific embodiment of the present invention, the hydrofluoric acid of dilution is adopted to implement wet-etching technology to oxide skin(coating), the concentration ratio of the hydrofluoric acid of dilution is 2%, the time of reaction is 1 minute, Semiconductor substrate can be immersed in hydrofluoric acid solution.
It should be noted that, the method for above-mentioned execution wet-etching technology process oxide skin(coating) is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
As shown in Figure 2 C, adopt oxidation technology secondary oxidative treatments deep trench 203, flush to make the sidewall of side wall (sidewall oxide) the 205 and nitride layer 202 formed on the bottom of deep trench 203 and sidewall after secondary oxidation PROCESS FOR TREATMENT.
In a specific embodiment of the present invention, adopt the silicon exposed caved inward relative to nitride layer 202 in thermal oxidation (thermal oxidation) process oxidizes deep trench 203, flush to make the side wall 205 of the deep trench 203 after oxidation technology process and nitride layer 202 sidewall.
In a specific embodiment of the present invention, thermal oxidation technology can be film by wet hot oxidation technique or xeothermic oxidation technology, alternatively, by oxygen source, as at molecular oxygen or/and carry out thermal oxidation technology in the atmosphere of ozone.
It should be noted that, bottom and the sidewall of above-mentioned secondary oxidation deep trench are exemplary with the method forming oxide skin(coating), are not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 2 D, etching removes the side wall (oxide skin(coating)) 205 bottom groove 203, retains the sidewall oxidation protective layer being positioned at deep trench 203 sidewall, to form the side wall 206 of deep trench 203.
In of the present invention one specifically example; anisotropic etching is adopted to remove not by side wall 205 that nitride layer 202 is protected; in the present invention, because the protection of nitride layer 203 is when adopting anisotropy to etch, side wall 206 free of losses be positioned at below nitride layer in deep trench 203.
Alternatively, anisotropic etching adopts dry etching usually, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
It should be noted that, the method for above-mentioned execution anisotropic etch process is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
Then, the method for high density plasma CVD (HDP) is adopted in deep trench 203, to fill spacer material layer, the preferred insulating oxide of material of described spacer material layer; Adopt flatening process process insulating oxide, as adopted chemical mechanical milling tech, to expose silicon nitride layer; Remove the oxide layer 201 of nitride layer 202 and part, to form the Semiconductor substrate with deep trench isolation structure.
With reference to Fig. 3, show the process chart making deep trench isolation structure according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 301, one is provided to include source region bulk silicon substrate, form oxide layer on a semiconductor substrate, oxide layer forms nitride layer, nitride layer described in patterning and described oxide layer, to form opening in described nitride layer and described pad oxide, etch described Semiconductor substrate, to form deep trench according at described nitride layer and described oxide layer split shed;
In step 302, perform deep trench described in oxidation technology process, the first side wall is formed on the bottom and sidewall of described deep trench;
In step 303, the first side wall on the bottom of removing and being positioned at described deep trench and sidewall is etched;
In step 304, perform deep trench described in secondary oxidation PROCESS FOR TREATMENT, the second side wall is formed on the bottom and sidewall of described deep trench;
In step 305, anisotropic etching is adopted to remove the second side wall be positioned at bottom deep trench.
The present invention proposes the another kind of deep trench that makes and protect side wall method.With reference to Fig. 4 A to Fig. 4 D, the cutaway view of the correlation step of the embodiment according to one aspect of the invention is shown.
As shown in Figure 4 A, provide the bulk silicon substrate 400 that includes source region, the constituent material of Semiconductor substrate 400 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator
(SOI), stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Semiconductor substrate 400 is formed oxide layer 401, and its main material is silicon dioxide.This oxide layer 401 is formed by thermal oxidation method, and general thickness is 100 ~ 160 dusts, and it is not subject to chemical spot (as isolating oxide layer) to protect active area when removing nitride layer mainly as separator.Oxide layer 401 is formed nitride layer 402; the material preferred nitrogen SiClx of nitride layer; boiler tube deposition process or Low Pressure Chemical Vapor Deposition can be adopted to form silicon nitride layer 402; its thickness is generally 600 ~ 1200 dusts; this nitride layer 402 is mainly used in protecting active area in deposition oxide process in deep trench isolation structure, and can be used as the barrier material of grinding when the silica that cmp is filled.Oxide layer 401 and nitride layer 402 are as the mask defining STI.
Photoetching process is adopted on nitride layer 402 and oxide layer 401, to define deep trench region and active area region, to form opening 403 in nitride layer 402 and oxide layer 401.
In a specific embodiment of the present invention, silicon nitride layer 402 forms hard mask layer, its material is agraphitic carbon, chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition can be adopted to form amorphous carbon layer, hard mask layer is formed dielectric anti-reflective coating (DARC), its material is silicon oxynitride, the method that chemical gas can be adopted to deposit prepares dielectric anti-reflective coating, the object of deposition formation dielectric anti-reflective coating is the reflectivity in order to reduce silicon nitride layer, and dielectric anti-reflective coating is formed the photoresist layer of patterning.
According to photoresist etching dielectrics antireflecting coating, hard mask layer, nitride layer 402 and the oxide layer 401 successively of patterning.Wherein, etching gas can adopt the gas based on chlorine or the gas based on hydrogen bromide or both mists.Adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0 ~ 200 cc/min (sccm), and reative cell internal pressure can be 5 ~ 20 millis millimetres of mercury (mTorr).Then, the photoresist layer of patterning, dielectric anti-reflective coating and hard mask layer is removed, to form opening.Wherein, original position cineration technics (In-situ Asher) is used to remove the photoresist of patterning, dielectric anti-reflective coating and hard mask layer, the gas that cineration technics adopts is preferably oxygen, concrete, silicon semiconductor substrate is inserted in reactive ion etching device, by additional heater such as Halogen lamp LED, in the chamber of direct heating reactive ion etching device, the temperature range of heating is 60 DEG C ~ 250 DEG C, then, use oxygen-containing gas to supply in the chamber of heated reactive ion etching device, described oxygen-containing gas is O
2, O
3, H
2o, N
2o, CH
3oH or its combination in any.The flow of oxygen-containing gas asks 4000 ~ 8000 cc/min (sccm), and ashing power is 300 watts ~ 1200 watts, has also passed into nitrogen and hydrogen simultaneously.
Then, according to the opening etch semiconductor substrates 400 formed in nitride layer 402 and oxide layer 401, to form deep trench 403.The etching agent of usual employing is fluorine-containing gas, such as CF
4or CHF
3.Dry etching can be adopted, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
In an embodiment of the present invention, the opening formed in described nitride layer 402 and oxide layer 401 defines deep trench isolation structural region and active region.
Then, wet-cleaned is adopted to remove the oxide skin(coating) of deep trench 403 sidewall surfaces to expose the polysilicon layer of sidewall, the oxide skin(coating) being positioned at deep trench 403 sidewall surfaces is native oxide layer, when Semiconductor substrate exposes in atmosphere, Water Molecular Adsorption on a semiconductor substrate and penetrate into silicon face, silicon face is caused to be oxidized, generate thin oxide layer, the hydrofluoric acid of dilution and hot phosphoric acid can be adopted to perform wet clean process, in a specific embodiment of the present invention, the hydrofluoric acid of dilution is adopted to implement wet clean process to oxide skin(coating), the concentration ratio of the hydrofluoric acid of dilution is 1%, the time of reaction is 1 minute, Semiconductor substrate can be immersed in the hydrofluoric acid solution of dilution.
It should be noted that, the method for above-mentioned execution wet-cleaned is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 4 B, adopt the polysilicon being positioned at deep trench 403 sidewall and the silicon oxide layer 401 of etching technics etching removal part, etching technics can adopt selectivity in the same way dry etching or wet etching the polysilicon layer of deep trench sidewall and oxide layer are etched, cave inward relative to the sidewall of described nitride layer 402 to make the sidewall of described deep trench.Described etching technics has the polysilicon of the sidewall of described deep trench 403 and silicon oxide layer 401 to the high etching selection ratio of described nitride layer 402, adopts dry etching or wet etching to perform described etch step.Alternatively, the combination in any of dry etching such as reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.
Alternatively, wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent (buffer oxide etchant (BOE)) or hydrofluoric acid cushioning liquid (buffer solution of hydrofluoric acid (BHF)).
It should be noted that, the method for above-mentioned etching deep trench sidewall is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 4 C, adopt oxidation process oxidizes process deep trench 403, the bottom and sidewall of deep trench 403 are formed sidewall oxide (side wall) 404, flushes to make the sidewall of the side wall (sidewall oxide) 404 formed in deep trench 403 after oxidation technology process and nitride layer 402.
In a specific embodiment of the present invention, adopt thermal oxidation (thermal oxidation) technique growth side wall (sidewall oxide) 404, flush with the sidewall of the side wall 404 and nitride layer 402 that make the deep trench 403 after oxidation technology process.
In a specific embodiment of the present invention, thermal oxidation technology can be film by wet hot oxidation technique or xeothermic oxidation technology, alternatively, by oxygen source, as at molecular oxygen or/and carry out thermal oxidation technology in the atmosphere of ozone.
It should be noted that, the method for above-mentioned execution thermal oxidation technology is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 4 D, etching removes the side wall (sidewall oxidation protective layer) 404 bottom groove 403, retains the side wall (sidewall oxidation protective layer) being positioned at deep trench 403 sidewall, to form the side wall 405 of deep trench 403.
In of the present invention one specifically example; anisotropic etching is adopted to remove not by side wall 404 that nitride layer 402 is protected; in the present invention, because the protection of nitride layer 403 is when adopting anisotropy to etch, side wall 405 free of losses be positioned at below nitride layer in deep trench 403.
Alternatively, anisotropic etching adopts dry etching usually, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
It should be noted that, the method for above-mentioned execution anisotropic etch process is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
Then, the method for high density plasma CVD (HDP) is adopted in deep trench 403, to fill spacer material layer, the preferred insulating oxide of material of described spacer material layer; Adopt flatening process process insulating oxide, as adopted chemical mechanical milling tech, to expose silicon nitride layer; Remove the oxide layer 401 of nitride layer 402 and part, to form the Semiconductor substrate with deep trench isolation structure.
With reference to Fig. 5, show the process chart making deep trench isolation structure according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 501, one is provided to include source region bulk silicon substrate, form oxide layer on a semiconductor substrate, oxide layer forms nitride layer, nitride layer described in patterning and described oxide layer, to form opening in described nitride layer and described pad oxide, etch described Semiconductor substrate, to form deep trench according at described nitride layer and described oxide layer split shed;
In step 502, wet clean process is adopted to remove the oxide layer of deep trench sidewall surfaces;
In step 503, employing selectivity in the same way dry etching or wet-etching technology etches polysilicon layer and the oxide layer of deep trench sidewall, caves inward relative to the sidewall of described nitride layer to make the sidewall of described deep trench;
In step 504, perform thermal oxidation technology, side wall on the bottom and sidewall of deep trench, flushes to make the sidewall of sidewall oxide and the nitride layer that deep trench sidewall is formed;
In step 505, anisotropic etching is adopted to remove the side wall be positioned at bottom deep trench.
The form of deep trench protection side wall in Semiconductor substrate can be optimized according to manufacturing process of the present invention; make the corner of the protection side wall formed more sphering and level and smooth; the thermal oxidation side wall insulating capacity formed can save space by force; the top of deep trench side wall is by silicon nitride layer protection not loss; the protective layer of deep trench side wall is even; follow-up filling is very helpful to avoid producing hole; also contribute to the reduction of semiconductor device Width size, be also conducive to the follow-up filling to deep trench.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (10)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form oxide layer and nitride layer successively on the semiconductor substrate;
Nitride layer, described oxide layer and described Semiconductor substrate described in patterning, to form deep trench;
Be oxidized bottom and the sidewall of described deep trench, to form the first oxide skin(coating);
Wet etching removes described first oxide skin(coating), caves inward relative to the sidewall of described nitride layer to make the sidewall of described deep trench;
Reoxidize bottom and the sidewall of described deep trench, to form the second oxide skin(coating), described second oxide skin(coating) flushes with the sidewall of described nitride layer;
Etching removes described second oxide skin(coating) be positioned at bottom described deep trench.
2. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form oxide layer and nitride layer successively on the semiconductor substrate;
Nitride layer, described oxide layer and described Semiconductor substrate described in patterning, to form deep trench;
Wet-cleaned is adopted to remove the oxide layer of the described deep trench sidewall surfaces of part;
Etch the sidewall of described deep trench, cave inward relative to the sidewall of described nitride layer to make the sidewall of described deep trench;
Be oxidized bottom and the sidewall of described deep trench, to form oxide skin(coating), described oxide skin(coating) flushes with the sidewall of described nitride layer;
Etching removes the described oxide skin(coating) be positioned at bottom described deep trench.
3. the method for claim 1, is characterized in that, adopts anisotropic etching to remove described second oxide skin(coating) be positioned at bottom described deep trench.
4. method as claimed in claim 2, is characterized in that, adopts anisotropic etching to remove the described oxide skin(coating) be positioned at bottom described deep trench.
5. method as claimed in claim 2, is characterized in that, adopts wet-etching technology to etch the sidewall of described deep trench.
6. method as claimed in claim 1 or 2, is characterized in that, adopts thermal oxidation technology to perform described oxidation step.
7. method as claimed in claim 1 or 2, it is characterized in that, the material of described nitride layer is silicon nitride.
8. method as claimed in claim 2, is characterized in that, the described oxide layer that described wet-cleaned is removed is native oxide layer.
9. method as claimed in claim 2, is characterized in that, adopts the sidewall of deep trench described in dry method or wet etching.
10. method as claimed in claim 9, it is characterized in that, described etching technics has the high etching selection ratio of sidewall to described nitride layer of described deep trench.
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| CN109950148A (en) * | 2017-12-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110556359A (en) * | 2019-09-17 | 2019-12-10 | 福建省晋华集成电路有限公司 | Bit line structure and semiconductor memory |
| CN111710602A (en) * | 2020-06-10 | 2020-09-25 | 上海华力集成电路制造有限公司 | Manufacturing method of high-K dielectric layer |
| CN112885707A (en) * | 2019-11-30 | 2021-06-01 | 长鑫存储技术有限公司 | Method for manufacturing memory device |
| CN112967997A (en) * | 2021-02-02 | 2021-06-15 | 长江存储科技有限责任公司 | Back-end metal filling method, filling device, storage device and semiconductor device |
| CN114093941A (en) * | 2020-07-30 | 2022-02-25 | 中国科学院微电子研究所 | Transistor device, forming method thereof and DRAM |
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| CN112885707A (en) * | 2019-11-30 | 2021-06-01 | 长鑫存储技术有限公司 | Method for manufacturing memory device |
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| CN111710602A (en) * | 2020-06-10 | 2020-09-25 | 上海华力集成电路制造有限公司 | Manufacturing method of high-K dielectric layer |
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| CN112967997A (en) * | 2021-02-02 | 2021-06-15 | 长江存储科技有限责任公司 | Back-end metal filling method, filling device, storage device and semiconductor device |
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