CN101740458A - Manufacturing method of shallow trench structure - Google Patents
Manufacturing method of shallow trench structure Download PDFInfo
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- CN101740458A CN101740458A CN200810203541A CN200810203541A CN101740458A CN 101740458 A CN101740458 A CN 101740458A CN 200810203541 A CN200810203541 A CN 200810203541A CN 200810203541 A CN200810203541 A CN 200810203541A CN 101740458 A CN101740458 A CN 101740458A
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Abstract
The invention relates to a manufacturing method of a shallow trench structure, which comprises the following steps of: providing a semiconductor substrate and forming a shallow trench on the semiconductor substrate; forming an oxide sacrifice layer in the shallow trench; removing the oxide sacrifice layer; forming a substrate oxide layer in the shallow trench; and forming a filling oxide layer for filling the shallow trench on the substrate oxide layer. Through the technical scheme, a corner at the top end of the shallow trench can be rounded in the forming process, thereby improving the stress environment in the shallow trench, avoiding the damage of a subsequent process to the shallow trench, improving the electrical performance of a semiconductor device and enhancing the yield of a semiconductor product.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, particularly manufacturing method of shallow trench structure.
Background technology
The developing direction of semiconductor integrated circuit is for increasing density and dwindling element.In production of integrated circuits, isolation structure is a kind of important technology, be formed on the silicon base element must with other element separation.Along with the progress of semiconductor fabrication techniques, shallow trench isolation from (Shallow Trench Isolation, STI) technology replaced gradually conventional semiconductor devices make adopted wait other partition methods as localized oxidation of silicon method (LOCOS).
The manufacture method of existing fleet plough groove isolation structure generally comprises: silica wafer in the high-temperature oxydation boiler tube, on silicon substrate, form cushion oxide layer (Pad Oxide) and silicon nitride layer (Nitride), carry out the shallow trench etching again, bottom and sidewall at shallow trench forms substrate oxide layer (Liner) with thermal oxidation technology afterwards, and on described substrate oxide layer, be formed for filling the filling oxide layer of shallow trench with for example low-pressure chemical vapor phase deposition (LPCVD) technology or high concentration plasma-chemical vapour deposition (CVD) (HDP-CVD) technology, then remove the material that the surface has more with cmp (CMP) technology, and with silicon nitride layer as grinding stop layer, stay a smooth surface, again silicon nitride layer and cushion oxide layer are removed at last, for the making of subsequent technique.
Because in the prior art, shallow trench utilizes etch process to form, and its each corner is tip shape mostly, and the shape of described shallow trench not only influences the filling effect of follow-up groove, and sharp-pointed shallow trench corner also causes edge current leakage easily, makes the device electric property descend.In addition, what shallow trench was filled employing is chemical vapor deposition (CVD) technology, particularly high concentration plasma-chemical vapour deposition (CVD) (HDP-CVD) technology, and in the bottom of shallow trench and the substrate oxide layer that forms of sidewall because thickness is less, generally for example be 30 dust to 200 dusts.In the process that forms filling oxide layer, plasma is known from experience constantly bombardment substrate oxide layer, particularly for that part that is tip shape that is positioned at each corner of shallow trench in the substrate oxide layer, it is more obvious to be subjected to plasma erosion meeting, thicknesses of layers can be by wear down, in addition can occur being the worse for wear and and then destroy the situation that is positioned at the silicon substrate under the substrate oxide layer, produce leakage current, reduce the isolation characteristic of shallow trench, thereby cause the final quality of semiconductor devices that forms to descend.
Summary of the invention
The problem that the present invention solves provides a kind of manufacturing method of shallow trench structure, has avoided in the prior art because the problem of the impurity effect product yield of polysilicon layer surface contamination.
For addressing the above problem, the invention provides a kind of manufacturing method of shallow trench structure, comprising: Semiconductor substrate is provided, on described Semiconductor substrate, forms shallow trench; In described shallow trench, form oxide sacrificial layer; Remove described oxide sacrificial layer; In described shallow trench, form the substrate oxide layer; On described substrate oxide layer, be formed for filling the filling oxide layer of shallow trench.
Alternatively, the method that forms described oxide sacrificial layer is a thermal oxidation technology.
Alternatively, described thermal oxidation technology comprises that situ steam generates technology.
Alternatively, the temperature conditions that forms described oxide sacrificial layer is 800 degrees centigrade to 1200 degrees centigrade.
Alternatively, the thickness of described oxide sacrificial layer is 30 dust to 200 dusts.
Alternatively, the material of described oxide sacrificial layer is a silica.
Alternatively, the number of times that forms oxide sacrificial layer is secondary at least.
Alternatively, the method for removing described oxide sacrificial layer is dry method etch technology or wet etching process.
Alternatively, the method that forms described substrate oxide layer is a thermal oxidation method.
Alternatively, the method for formation filling oxide layer is high concentration plasma-chemical vapor deposition method.
Compared with prior art, technical solution of the present invention forms additionally to have increased before the substrate oxide layer in making shallow ditch groove structure technology in shallow trench and forms oxide sacrificial layer and in the follow-up processing step of being removed again in shallow trench, make each corner of shallow trench be able to sphering, improve the ambient stress in the shallow trench, avoid when carrying out subsequent technique and make destruction to shallow trench (particularly top corner), improve the electric property of semiconductor device, and then promote the yield of semiconductor product.
Description of drawings
Fig. 1 is the flow chart according to manufacturing method of shallow trench structure in the embodiment of the present invention;
Fig. 2 to Fig. 6 is a structural representation of making shallow ditch groove structure according to Fig. 1 flow process.
Embodiment
The inventor finds, when making shallow ditch groove structure, each corner of shallow trench is tip shape, and when later use HDP-CVD technology forms filling oxide layer, because HDP has certain etching power, plasma causes bombardment to the substrate oxide layer, and the substrate oxidated layer thickness is less, particularly the substrate oxide layer at each angle position place of shallow trench also is tip shape, so the substrate oxide layer is very easy destroyed under plasma bombardment, causes filling oxide layer silicon substrate direct and that shallow trench is interior to contact, make STRESS VARIATION in the shallow trench, even can destroy the interior lattice of shallow trench, make lattice produce defective, thereby cause the electric property of semiconductor device to descend.
Therefore, when making semiconductor device, for preventing of the influence of above-mentioned defective to the product yield.The invention provides a kind of manufacturing method of shallow trench structure, comprising: Semiconductor substrate is provided, on described Semiconductor substrate, forms shallow trench; In described shallow trench, form oxide sacrificial layer; Remove described oxide sacrificial layer; In described shallow trench, form the substrate oxide layer; On described substrate oxide layer, be formed for filling the filling oxide layer of shallow trench.Additionally increased in shallow trench and to have formed oxide sacrificial layer and in the follow-up processing step of being removed again, make each corner of shallow trench be able to sphering, improve the ambient stress in the shallow trench, avoid the destruction of subsequent technique to substrate oxide layer and silicon substrate, improve the electric property of semiconductor device, and then promote the yield of semiconductor product.
The invention provides a kind of manufacturing method of shallow trench structure, comprise Semiconductor substrate is provided, described Semiconductor substrate is formed with shallow trench; In described shallow trench, form oxide sacrificial layer; Remove described oxide sacrificial layer; In described shallow trench, form the substrate oxide layer.Compared with prior art, make shallow trench top corner be able to sphering, improve the ambient stress in the shallow trench, when avoiding follow-up execution high density plasma CVD and cmp to the destruction of shallow trench (particularly top corner), thereby the decline of surperficial semiconductor device electric property.
For this reason, as shown in Figure 1, described manufacturing method of shallow trench structure comprises the steps:
S100 provides Semiconductor substrate, forms shallow trench on described Semiconductor substrate.
S102 forms oxide sacrificial layer in described shallow trench.
S104 removes described oxide sacrificial layer.
S106 forms the substrate oxide layer in described shallow trench.
S108 is formed for filling the filling oxide layer of shallow trench on described substrate oxide layer.
Below in conjunction with accompanying drawing content of the present invention is elaborated.
Execution in step S100 provides Semiconductor substrate, forms cushion oxide layer 201, silicon nitride layer 202 and shallow trench 203 on Semiconductor substrate 200 in regular turn, forms structure as shown in Figure 2.
Wherein, described Semiconductor substrate 200 is silicon, the silicon-on-insulator (SOI) that is formed with semiconductor device that is formed with semiconductor device or is II-VI or the III-V compound semiconductor that is formed with semiconductor device.
The material of cushion oxide layer 201 is generally silica.In the prior art, the technology that forms cushion oxide layer 201 is thermal oxidation method, promptly under hot environment, Semiconductor substrate 200 is exposed in the aerobic environment.This technology realizes in boiler tube usually.Usually the thickness of the cushion oxide layer 201 that forms is all on the tens Izod right sides, and for example about 50 dust to 250 dusts are thick.Because of the technology that forms cushion oxide layer 201 is well known to those skilled in the art, so do not repeat them here.
On cushion oxide layer 201, form silicon nitride layer 202.The material of described silicon nitride layer 202 is a silicon nitride.In the prior art, the method for formation silicon nitride layer 202 for example is chemical vapor deposition method (CVD).In the present embodiment, the thickness of the silicon nitride layer 202 of formation is approximately 1000 dusts～2000 dusts.Because of the technology that forms silicon nitride layer 202 is well known to those skilled in the art, so do not repeat them here.
Then, be etched with and form shallow trench 203, shallow trench 203 is to be used for that Semiconductor substrate 200 formed grid structures (diagram) are carried out electricity to isolate.In the prior art, the method that forms shallow trench 203 is a lithography technology, specifically, is by anisotropic etching, and to contain HBr, Cl and CF
4For reacting gas forms.It is dark that the degree of depth of the shallow trench 203 that forms is generally 0.4um to 0.5um.Because of the technology that forms shallow trench 203 is well known to those skilled in the art, so do not repeat them here.
Then execution in step S102 forms oxide sacrificial layer 204 in shallow trench 203, forms structure as shown in Figure 3.
Oxide sacrificial layer 204 is formed on the bottom and sidewall of shallow trench 203.The material of oxide sacrificial layer 204 is a silica.In the prior art, oxide sacrificial layer 204 can for example be a thermal oxidation method, promptly under hot environment, Semiconductor substrate 200 is exposed in the aerobic environment.Preferably; can be that situ steam generates technology (ISSG); specifically; be the hydrogen (having oxygen and atmosphere hydroxy) that in common oxygen atmosphere, has mixed constant; at high temperature; for example 800 degrees centigrade～1200 degrees centigrade; generation is similar to the chemical reaction of detonation; described reaction can produce a large amount of gas-phase activity free radicals; it wherein mainly is the elemental oxygen that is easy to silicon atom reaction; because the strong oxidation of elemental oxygen, protection is not being arranged; exposed silicon surface all can be oxidized and then be formed ISSG oxide skin(coating) (being oxide sacrificial layer 204), and the thickness of the oxide sacrificial layer 204 of formation is roughly 30 dust to 200 dusts.Described oxide sacrificial layer 204 can be repaired the substrate lattice defective in the shallow trench 203 and improve substrate surface stress in the shallow trench 203.
Then execution in step S104 removes described oxide sacrificial layer 204, forms structure as shown in Figure 4.Oxide sacrificial layer 204 can be removed by dry method etch technology or wet etching process.With the wet etching process is that example describes, and for example can corrode and removes oxide sacrificial layer 204 by dilution water dissolubility hydrofluoric acid (HF) solution.The selection of described hydrofluoric acid solution should be with reference to the factors such as thickness of humidity, drying condition and oxide sacrificial layer 204.Can guarantee better the microroughness of silicon chip surface in processing procedure, can not produce extra impurity by dilution water dissolubility hydrofluoric acid solution cleaning technique.The specific implementation method that this hydrofluoric acid is removed technology is well known to those skilled in the art, does not repeat them here.
Know easily, by the step S102 of above-mentioned formation oxide sacrificial layer 204 and the step S104 of removal oxide sacrificial layer 204, can make shallow trench 203 in the high-temperature process that oxide sacrificial layer 204 forms and removes, stress can obtain certain release, each corner of shallow trench 203 (comprising the bottom of shallow trench and the corner of the formed corner of sidewall and sidewall and semiconductor substrate surface formation) is obtained sphering to a certain degree, each corner is tip shape before comparing, and effect is obvious.
Follow execution in step S106,203 form substrate oxide layers 205 in shallow trench, form structure as shown in Figure 5.
Oxide sacrificial layer 204 is formed on the bottom and sidewall of shallow trench 203.The material of substrate oxide layer 205 is a silica, and its thickness is 30 dust to 200 dusts.In the prior art, oxide sacrificial layer 204 is similar with forming, and the method that forms substrate oxide layer 205 also can be utilized thermal oxidation method, be preferably ISSG technology, realizes.Because of this ISSG technology is well known to those skilled in the art, do not repeat them here.
It should be noted that, what adopt when forming substrate oxide layer 205 in step S106 is thermal oxidation method, so in processing procedure, particularly under the high temperature situation, the stress of shallow trench 203 can further be discharged, and each corner sphering effect of shallow trench 203 is more obvious, makes that final substrate oxide layer 205 thickness that form are even, and that part of of each corner at corresponding shallow trench 203 is rounding off equally, and the tip shape before can avoiding occurring.
Follow execution in step S108, on substrate oxide layer 205, be formed for filling the filling oxide layer 206 of shallow trench 203, form structure as shown in Figure 6.
The material of filling oxide layer 206 is a silica.In the prior art, the method for formation filling oxide layer 206 can be low-pressure chemical vapor phase deposition (LPCVD) technology or high concentration plasma-chemical vapour deposition (CVD) (HDP-CVD) technology.Preferably, can be for example with SiH
4, O
2Groove is filled as the HDP-CVD technology of the gas source of plasma with the mist of Ar,, do not repeat them here because of the specific implementation method of this HDP-CVD technology is well known to those skilled in the art.Owing to pass through above-mentioned steps; make each corner of shallow trench and each corner of the substrate oxide layer 205 corresponding obtain sphering with it; substrate oxide layer 205 can effectively be protected the Semiconductor substrate under it, avoids the destruction of HDP-CVD technology ionic medium to substrate oxide layer 205 and following Semiconductor substrate thereof.
Technical solution of the present invention in making shallow ditch groove structure technology by in shallow trench, being pre-formed oxide sacrificial layer and in the follow-up processing step of being removed again, make that each corner of shallow trench is able to sphering under the high-temperature process that forms oxide sacrificial layer, improve the ambient stress in the shallow trench, make that the substrate oxidated layer thickness of follow-up formation is more even, its corresponding each corner also can obtain sphering, when avoiding follow-up execution high density plasma CVD and cmp to the destruction of shallow trench (particularly top corner), improve the electric property of semiconductor device, and then promote the yield of semiconductor product.
Though the present invention discloses as above with preferred embodiment, but the present invention is defined in this, for example in the above-described embodiment, the processing step that forms oxide sacrificial layer and removed is not limited in once, influence production efficiency and increasing the balance that processing step improves shallow trench internal stress environment and consider for increasing processing step, above-mentioned processing step also can carry out secondary even repeatedly above according to the actual needs, to reach better effect.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. a manufacturing method of shallow trench structure is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms shallow trench;
In described shallow trench, form oxide sacrificial layer;
Remove described oxide sacrificial layer;
In described shallow trench, form the substrate oxide layer;
On described substrate oxide layer, be formed for filling the filling oxide layer of shallow trench.
2. according to the described manufacturing method of shallow trench structure of claim 1, it is characterized in that the method that forms described oxide sacrificial layer is a thermal oxidation technology.
3. according to the described manufacturing method of shallow trench structure of claim 1, it is characterized in that described thermal oxidation technology comprises that situ steam generates technology.
4. according to the described manufacturing method of shallow trench structure of claim 1, it is characterized in that the temperature conditions that forms described oxide sacrificial layer is 800 degrees centigrade to 1200 degrees centigrade.
5. according to claim 1 or 2 described manufacturing method of shallow trench structure, it is characterized in that the thickness of described oxide sacrificial layer is 30 dust to 200 dusts.
6. manufacturing method of shallow trench structure as claimed in claim 1 or 2 is characterized in that, the material of described oxide sacrificial layer is a silica.
7. according to the described manufacturing method of shallow trench structure of claim 1, it is characterized in that the number of times that forms oxide sacrificial layer is secondary at least.
8. manufacturing method of shallow trench structure as claimed in claim 1 is characterized in that, the method for removing described oxide sacrificial layer is dry method etch technology or wet etching process.
9. manufacturing method of shallow trench structure as claimed in claim 1 is characterized in that, the method that forms described substrate oxide layer is a thermal oxidation method.
10. manufacturing method of shallow trench structure as claimed in claim 1 is characterized in that, the method that forms filling oxide layer is high concentration plasma-chemical vapor deposition method.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
| CN102646603A (en) * | 2012-04-24 | 2012-08-22 | 上海宏力半导体制造有限公司 | Grooved MOS (metal oxide semiconductor) forming method |
| CN103646862A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | A manufacturing method of a CMOS device gate oxide layer |
| WO2014088976A1 (en) * | 2012-12-05 | 2014-06-12 | Robert Bosch Gmbh | Structured gap for a mems pressure sensor |
| CN107731822A (en) * | 2017-08-22 | 2018-02-23 | 长江存储科技有限责任公司 | The preparation method and its structure of a kind of three-dimensional storage |
| CN110462823A (en) * | 2017-03-30 | 2019-11-15 | 超威半导体公司 | Sinusoidal shape capacitor framework in oxide |
-
2008
- 2008-11-27 CN CN200810203541A patent/CN101740458A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
| CN102646603A (en) * | 2012-04-24 | 2012-08-22 | 上海宏力半导体制造有限公司 | Grooved MOS (metal oxide semiconductor) forming method |
| CN102646603B (en) * | 2012-04-24 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | The formation method of groove type MOS |
| WO2014088976A1 (en) * | 2012-12-05 | 2014-06-12 | Robert Bosch Gmbh | Structured gap for a mems pressure sensor |
| US9073749B2 (en) | 2012-12-05 | 2015-07-07 | Robert Bosch Gmbh | Structured gap for a MEMS pressure sensor |
| CN103646862A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | A manufacturing method of a CMOS device gate oxide layer |
| CN103646862B (en) * | 2013-11-29 | 2016-06-15 | 上海华力微电子有限公司 | The manufacture method of cmos device gate oxide |
| CN110462823A (en) * | 2017-03-30 | 2019-11-15 | 超威半导体公司 | Sinusoidal shape capacitor framework in oxide |
| CN107731822A (en) * | 2017-08-22 | 2018-02-23 | 长江存储科技有限责任公司 | The preparation method and its structure of a kind of three-dimensional storage |
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Open date: 20100616 |