CN103646862A - A manufacturing method of a CMOS device gate oxide layer - Google Patents

A manufacturing method of a CMOS device gate oxide layer Download PDF

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CN103646862A
CN103646862A CN201310630240.5A CN201310630240A CN103646862A CN 103646862 A CN103646862 A CN 103646862A CN 201310630240 A CN201310630240 A CN 201310630240A CN 103646862 A CN103646862 A CN 103646862A
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gate oxide
cmos device
oxide layer
active area
manufacture method
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CN103646862B (en
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马旭
周维
徐炯�
魏峥颖
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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Abstract

The invention discloses a manufacturing method of a CMOS device gate oxide layer. The manufacturing method comprises: producing shallow trench isolation regions, a liner oxide layer, and a hard mask on a silicon substrate; etching a field region between two shallow trench isolation regions in order to expose an active region and a part of shallow trench isolation regions on the edge of the active region; growing a oxide layer on the surface of the active region with furnace tube technology in order to make the edge of the active region circular; removing the oxide layer on the surface of the active region with wet etching; and growing a gate oxide layer on the surface of the active region with the furnace tube technology. The manufacturing method generates the oxide layer on the surface of the active region with the furnace tube technology and then removes the oxide layer with the wet etching method. By the two steps of the technology, edge sharp corners of the active region and the appearance of the gate oxide layer are improved such that the performance of the device is enhanced.

Description

The manufacture method of cmos device gate oxide
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacture method of gate oxide in a kind of cmos device.
Background technology
Along with the development of semiconductor technology, more and more higher to the requirement of device performance, and at CMOS(Complementary Metal Oxide Semiconductor) in device, the thickness of gate oxide and pattern thereof can directly affect the performance of device.
Especially, along with the fast development of LCD industry, the demand of respective drive device and also corresponding increase of requirement.And on the basis of balance illumination cost and device performance, HV(High Voltage) CMOS is in the space that has a wide range of applications aspect LCD driving.The gate oxide thickness of tradition HV CMOS manufacturing process is about 100 nanometer left and right, and the quality of grid oxygen pattern directly has influence on the stability of the performance of device.Therefore, for grid oxygen thicker in HV CMOS technique, control the quality of its pattern, seem particularly most important.
The long oxidizing process of grid oxygen demand due to thicker, will inevitably cause the increase of growth rate difference between silicon substrate different crystal orientations.Fig. 1 has shown the pattern of HV CMOS surfaces of active regions after grid oxygen forms, wherein, increase along with oxidization time, by making gate oxide thickness, at edge, active area, (near STI place) is significantly less than in the middle of active area (away from STI place), also at edge, active area, form wedge angle, will directly reduce the reliability performance such as HV device GOI like this.
In order to address this problem, more common way is by controlling oxidizing temperature and gas flow at present, thereby controls oxidization time, and then realizes the object of improving HV grid oxygen pattern, as shown in Figure 2.But this method still cannot be avoided the different difference of gate oxide growth speed that different crystal orientations causes, but also will be limited to the factors such as board ability, therefore cannot thoroughly improve and at edge, active area, form wedge angle and the inhomogeneous technical problem of gate oxide thickness.
Summary of the invention
The problem existing in order to solve above-mentioned prior art, the invention provides a kind of manufacture method of cmos device gate oxide, the pattern, thickness evenness that can effectively improve gate oxide in cmos device with and at the wedge angle of active area edge, thereby improve device performance.
The manufacture method that the invention provides a kind of cmos device gate oxide, it comprises the following steps:
Step S01, on silicon substrate, prepare shallow trench isolation regions (shallow trench isolation, be called for short STI), cushion oxide layer and hard mask, by the place between two shallow trench isolation regions of etching to expose the part shallow trench isolation regions at active area and edge, active area;
Step S02, by boiler tube technique, in surfaces of active regions growth layer of oxide layer, makes the edge sphering of active area;
Step S03, by wet etching, removes the oxide layer of surfaces of active regions growth;
Step S04, at surfaces of active regions growth gate oxide.
" active area " of wherein, exposing described in step S01 of the present invention refers to the silicon substrate of removing the active device prepared exposing after hard mask and cushion oxide layer between two shallow trench isolation regions through over etching.
The part shallow trench isolation regions at the Yu Qi edge, active area exposing in step S01 further, is equal.
Further, step S01 also comprises that the active area to exposing carries out prerinse.
Further, the oxidated layer thickness of growing in step S02 is 5-20nm, so that the edge sphering of active area.
Further, in step S03, the medium of wet etching is the solution that contains HF.Its preferred concentration is 0.5-2%.
Further, step S02 or step S04 technique used are boiler tube technique or ISSG technique.
Further, between step S03 and step S04, also comprise and repeat at least one times step S02 to step S03.
Further, described cmos device is high voltage CMOS device, and in step S04, the thickness of gate oxide is 80-150nm.
Wherein, in step S01, STI is by CVD(Chemical Vapor Deposition, chemical vapour deposition (CVD)) technique makes.
The present invention proposes a kind of manufacture method of cmos device gate oxide, utilize boiler tube technique to generate the thin oxide layer of one deck in surfaces of active regions, make edge, active area sphering, utilize subsequently wet etching to be removed, by this two step process, can improve the edge wedge angle of active area, after preparing gate oxide, can improve the pattern of gate oxide, thereby improve the concentrated distribution of active area edge power line, reach the performance that improves the cmos devices such as device GOI reliability.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention is described in detail, wherein:
Fig. 1 is the shape appearance figure of existing HV CMOS surfaces of active regions after gate oxide forms;
Fig. 2 is the shape appearance figure of another existing HV CMOS surfaces of active regions after gate oxide forms;
Fig. 3 a to Fig. 3 d is the flow chart of first embodiment of the invention grating oxide layer preparation method;
Fig. 4 is according to the shape appearance figure of surfaces of active regions after the manufacture method formation gate oxide of first embodiment of the invention.
Embodiment
the first embodiment
Refer to Fig. 3 a to Fig. 3 d, the manufacture method of the cmos device gate oxide of the present embodiment, comprises the following steps:
Step S01, provides a silicon chip, and it has silicon substrate 1 and lip-deep pad silicon dioxide 3(SiO thereof 2); On silicon substrate 1, form shallow channel and pass through CVD(Chemical Vapor Deposition, chemical vapour deposition (CVD)) process deposits silicon dioxide, to prepare two shallow trench isolation regions 2; On pad silicon dioxide 3 and shallow trench isolation regions 2, prepare hard mask silicon nitride 4(Si 3n 4); Then, by dry etch process, remove between two shallow trench isolation regions 2 hard mask silicon nitride and pad silicon dioxide to expose the part shallow trench isolation regions 52 at 51 edges, 51Ji active area, active area, the active area 51 of exposing is layer-of-substrate silicon, the part shallow trench isolation regions 52 at the 51Yu Qi edge, active area exposing is equal, so that the generation of subsequent oxidation layer; Then, prerinse is carried out in 51 surfaces, active area, to remove active area 51, C/O of silicon face etc. is residual, as shown in Figure 3 a.Wherein, this prerinse can be suitable for HF, SPM(H 2sO 4, H 2o 2, H 2the mixed liquor of O) or SC1(NH 4oH, H 2o 2, H 2the mixed liquor of O).
Step S02, by boiler tube technique, puts into above-mentioned silicon chip boiler tube and passes into oxygen and steam, makes active area 51 superficial growths go out the silicon dioxide layer 6 that a layer thickness is about 10nm, makes the edge sphering of active area 51, as shown in Figure 3 b.
Wherein, this step can adopt dry oxygen or wet oxygen, and technique can adopt traditional burner plumber skill or ISSG technique (situ steam produces, in-situ steam generation).
Step S03, utilizes wet-etching technology, by the HF solution of 1% concentration, remove the silicon dioxide layer 6 on 51 surfaces, active area, also can etch away the part shallow trench isolation regions 52 at edge, part active area simultaneously, make active area 51 there is the edge of sphering, as shown in Figure 3 c.
Wherein, the principle of this step is: on active area, by boiler tube technique, grow the oxide layer that one deck is thin, in oxidizing process, the silicon of surfaces of active regions is progressively oxidized to silicon dioxide, principle based on growth rate difference between silicon face different crystal orientations, at the oxidation initial stage, growth rate on the edge angle of active area is all higher than end face or side, therefore the silicon at edge, active area is oxidized and form fillet more, increase along with oxidization time, the growth rate of active area end face or side again can be gradually fast than on edge angle, now just there is no to the silicaization at edge, active area the many of end face or side, so fillet can gradually become wedge angle again.Technical scheme of the present invention is exactly first in surfaces of active regions, to generate the thin oxide layer of one deck, after forming rounded edges, the initial stage of oxidation stops oxidation, the oxide layer remove generating again, last at edge sphering surfaces of active regions prepare gate oxide, especially thick grating oxide layer (
Figure BDA0000426196820000031
left and right), edge, active area is along with the degree that edge comes to a point of carrying out being oxidized while preparing gate oxide just can to offset part, and after having made gate oxide, edge, active area is no longer wedge angle.
Step S04, by boiler tube technique, puts into above-mentioned silicon chip boiler tube and passes into oxygen and steam, and in active area, 51 superficial growths go out the gate oxide 7 that thickness is 100nm, as shown in Figure 3 d.
Wherein, this step can adopt dry oxygen or wet oxygen, and technique can adopt traditional burner plumber skill or ISSG technique (situ steam produces, in-situ steam generation).
In the present embodiment, described " boiler tube technique " and " wet etching " can adopt process means of the prior art, process conditions, technological parameter.
The present embodiment is the gate oxide of preparing high voltage CMOS device, and its thickness reaches
Figure BDA0000426196820000041
(being 100nm).But protection scope of the present invention is not limited only to this, by technique of the present invention, can improve the wedge angle problem at edge, active area in any type cmos device, just to high tension apparatus to improve effect more obvious.Therefore, in other embodiments, preparation method of the present invention is also applicable to other cmos devices, and the thickness of gate oxide also can be adjusted according to actual needs.
In other embodiments, between step S03 and step S04, also comprise that repetition one or many step S02 is to step S03, the technique that repeatedly generates oxide-film and remove, the further edge of sphering active area, improve wedge angle problem, thereby improve the reliability of device grid oxygen.
Fig. 4 has shown the gate oxide pattern that utilizes first embodiment of the invention manufacture method to form, and can see, the edge wedge angle of active area has clear improvement.

Claims (9)

1. a manufacture method for cmos device gate oxide, is characterized in that, comprises the following steps:
Step S01 prepares shallow trench isolation regions, cushion oxide layer and hard mask on silicon substrate, by the place between two shallow trench isolation regions of etching to expose the part shallow trench isolation regions at active area and edge, active area;
Step S02, in surfaces of active regions growth layer of oxide layer, makes the edge sphering of active area;
Step S03, by wet etching, removes the oxide layer of surfaces of active regions;
Step S04, at surfaces of active regions growth gate oxide.
2. the manufacture method of cmos device gate oxide according to claim 1, is characterized in that: step S02 or step S04 technique used are boiler tube technique or ISSG technique.
3. the manufacture method of cmos device gate oxide according to claim 2, is characterized in that: the oxidated layer thickness of growing in step S02 is 5-20nm.
4. the manufacture method of cmos device gate oxide according to claim 3, is characterized in that: in step S03, the medium of wet etching is the solution that contains HF.
5. the manufacture method of cmos device gate oxide according to claim 5, is characterized in that: the HF that this solution contains 0.5-2%.
6. the manufacture method of cmos device gate oxide according to claim 1, is characterized in that: the part shallow trench isolation regions at the Yu Qi edge, active area exposing in step S01 is equal.
7. the manufacture method of cmos device gate oxide according to claim 2, is characterized in that: step S01 also comprises that the active area to exposing carries out prerinse.
8. according to the manufacture method of the cmos device gate oxide described in claim 1 to 7 any one, it is characterized in that: between step S03 and step S04, also comprise and repeat at least one times step S02 to step S03.
9. the manufacture method of cmos device gate oxide according to claim 8, is characterized in that: described cmos device is high voltage CMOS device, and in step S04, the thickness of gate oxide is 80-150nm.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731822A (en) * 2017-08-22 2018-02-23 长江存储科技有限责任公司 The preparation method and its structure of a kind of three-dimensional storage
CN113053816A (en) * 2019-12-27 2021-06-29 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof

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Publication number Priority date Publication date Assignee Title
TW434904B (en) * 1999-12-08 2001-05-16 United Semiconductor Corp Method for reducing inverse narrow width effect
US6960514B2 (en) * 2001-10-26 2005-11-01 International Business Machines Corporation Pitcher-shaped active area for field effect transistor and method of forming same
CN1913121A (en) * 2005-08-09 2007-02-14 印芬龙科技股份有限公司 Manufacturing method of semiconductor structure and associated semiconductor structure
CN101740458A (en) * 2008-11-27 2010-06-16 中芯国际集成电路制造(上海)有限公司 Manufacturing method of shallow trench structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW434904B (en) * 1999-12-08 2001-05-16 United Semiconductor Corp Method for reducing inverse narrow width effect
US6960514B2 (en) * 2001-10-26 2005-11-01 International Business Machines Corporation Pitcher-shaped active area for field effect transistor and method of forming same
CN1913121A (en) * 2005-08-09 2007-02-14 印芬龙科技股份有限公司 Manufacturing method of semiconductor structure and associated semiconductor structure
CN101740458A (en) * 2008-11-27 2010-06-16 中芯国际集成电路制造(上海)有限公司 Manufacturing method of shallow trench structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731822A (en) * 2017-08-22 2018-02-23 长江存储科技有限责任公司 The preparation method and its structure of a kind of three-dimensional storage
CN107731822B (en) * 2017-08-22 2019-01-29 长江存储科技有限责任公司 A kind of preparation method and its structure of three-dimensional storage
CN113053816A (en) * 2019-12-27 2021-06-29 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
CN113053816B (en) * 2019-12-27 2022-08-26 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof

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