CN104157602B - The preparation method of fleet plough groove isolation structure - Google Patents
The preparation method of fleet plough groove isolation structure Download PDFInfo
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- CN104157602B CN104157602B CN201410427369.0A CN201410427369A CN104157602B CN 104157602 B CN104157602 B CN 104157602B CN 201410427369 A CN201410427369 A CN 201410427369A CN 104157602 B CN104157602 B CN 104157602B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
The present invention provides a kind of preparation methods of fleet plough groove isolation structure, including successively carrying out: forming groove in the semiconductor substrate, form linear oxide layer in the trench, fill spacer medium layer and high annealing in the trench, wherein, the method for forming linear oxide layer includes: the inner surface cvd nitride layer in groove；Oxidation nitridation layer forms nitrogen oxidation layer in the inner surface of groove.It deposited nitration case to be aoxidized again later, with round and smooth flute surfaces and the stress in groove can be alleviated, it can also avoid directly being aoxidized severe attrition to trenched side-wall material to trenched side-wall, and then increase oxygen-containing group or the H of formation during subsequent anneal2The difficulty of diffusion of the O into semiconductor substrate；Nitrogen oxidation layer can be used as the transitional material of subsequent trench filling, can also effectively prevent oxygen-containing group or the H of formation during subsequent anneal2The substrate for being diffused into trenched side-wall of O, avoids the oxidation to active area boundary, to reduce the diminution of active area critical dimension.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of preparation method of fleet plough groove isolation structure.
Background technique
With the development of integrated circuit, modern CMOS chip usually on one piece of common silicon substrate material integrate number with
Then the active device (i.e. NMOS transistor and PMOS transistor) of million meters realizes various complicated patrol by specifically connection
Function or analog functuion are collected, and other than these specific functions, in the design process of circuit, usually assume that different devices
It is usually there is no others to interact between part.Therefore it allows for device isolation to come in integrated circuit fabrication,
This just needs isolation technology.
With device to deep-submicron develop, isolation technology by selective oxidation (Local Oxidation of Silicon,
LOCOS) technological development becomes shallow trench isolation (STI) technology.The common shallow trench isolation of industry (STI) method mainly include with
Lower step: firstly, being sequentially depositing oxide layer, silicon nitride layer on a silicon substrate, and patterned photoetching is formed on silicon nitride layer
Glue-line；Later using the patterned photoresist layer as mask etching silicon nitride layer, oxide layer and substrate, so that groove is formed, and
Define active area (Active Area)；Then linear oxide layer (Liner Oxide) is grown, in the trench to improve silicon lining
The interfacial characteristics of the oxide of bottom and subsequent filling carry out high annealing (High Temperature Anneal) then to release
Stress is put, the quality of oxide layer is optimized；Then oxide material (such as SiO2 material) is inserted in these grooves as isolation material
Material；Carry out high annealing (High Temperature Anneal) finally to discharge stress, and the oxide material in densification groove
Material.Above-mentioned isolation technology can completely eliminate the beak at oxide layer edge specific to selective oxidation (LOCOS) isolation technology
Shape, it is possible thereby to form smaller device isolation region.
Liner oxidation layer for there is fleet plough groove isolation structure needs the film of low defect and high-compactness, can not only change
The interfacial characteristics of kind silicon substrate and the oxide of subsequent filling, and isolation can be stopped in subsequent high-temperature annealing process
Diffusion of the oxygen-containing group to active area in medium, avoids the oxidation to active area boundary, so that it is critical to greatly reduce active area
Size (AA CD) reduces；And liner oxidation layer can also stop the H formed in high-temperature annealing process2O is diffused into semiconductor lining
The loss of silicon is caused in bottom, and can result in the reduction of active area critical dimension.H is formed in high-temperature annealing process2The reaction of O is former
It manages as follows :~Si-O-H+H-O-Si~... →... Si-O-Si ...+H2O。
In the method for the linear oxide layer of existing growth, generally include: oxidation groove side wall forms a thin layer of linear
Oxide layer forms oxide layer due to directly carrying out oxidation technology in the trench, will cause a large amount of damages of silicon materials on trenched side-wall
Consumption, and the H of the oxygen-containing group or formation in subsequent spacer medium layer2O be particularly easy to be diffused into the boundary of active area by its
Oxidation, to reduce the critical dimension of active area.The critical dimension of active area reduces the saturation current that will affect device, in turn
Influence the performance of entire device.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide a kind of preparation method of fleet plough groove isolation structure, passes through improvement
The growth pattern of liner oxidation layer reduces oxygen-containing group or H2The diffusion of O avoids the oxidation to active area boundary, thus
Avoid the diminution of active area critical dimension.
The present invention provides a kind of preparation method of fleet plough groove isolation structure, a kind of preparation side of fleet plough groove isolation structure
Method, including successively carry out: formed in the semiconductor substrate groove, formed in the trench linear oxide layer, fill in the trench every
From dielectric layer and high annealing, the method for forming linear oxide layer includes:
Step S41: in the inner surface cvd nitride layer of the groove；
Step S42: aoxidizing the nitration case, forms nitrogen oxidation layer in the inner surface of the groove.
Preferably, the process for forming groove in the semiconductor substrate specifically includes:
Step S1: a semiconductor substrate is provided；
Step S2: etched technique forms groove in the semiconductor substrate；
Step S3: surface clean is carried out to the groove.
Preferably, in the step 41, the nitration case is deposited using atom layer deposition process.Further, described
Reaction gas used by atom layer deposition process includes: SiH2Cl2And NH3, technological parameter are as follows: and 400-650 DEG C of depositing temperature,
Reaction gas SiH2Cl2Flow be 1~5slm, NH3Flow be 2~10slm, radio-frequency power 80-200W.
Preferably, in the step 42, the nitration case is aoxidized using steam oxidation technique in situ.
Preferably, in the step 42, the nitrogen oxidation layer include the nitration case being oxidized and the groove with
The surface of the nitration case contact.
Further, reaction gas used by the steam oxidation technique in situ is H2And O2Mixed gas, it is described
The total flow of mixed gas is 10~40slm, wherein H2Content can be 0.5~33%；Used temperature is 1000-
1100℃
Preferably, in the step 41, the nitration case with a thickness of
Preferably, in the step 42, the nitrogen oxidation layer with a thickness of
Preferably, in the step 42, the material of the nitrogen oxidation layer is silicon oxynitride
The present invention grows fleet plough groove isolation structure by the group technology of cvd nitride layer first and then oxidation nitridation layer
Liner oxidation layer, with reduce active area critical dimension diminution.
Wherein, on the one hand to the oxidation of trenched side-wall, can in the top corner of round and smooth groove and removal etching process
The damage that flute surfaces introduce, to alleviate the stress in groove, to be conducive to being sufficient filling with for subsequent trench；Also, by
Then it is aoxidized again after it deposited nitration case, it is possible to avoid directly aoxidizing to trenched side-wall trenched side-wall
The severe attrition of material, and then increase oxygen-containing group or the H of formation during subsequent anneal2Expansion of the O into semiconductor substrate
Scattered difficulty avoids the diminution of active area critical dimension it is possible thereby to avoid the oxidation to active area boundary；
On the other hand, nitrogen oxidation layer acts not only as the transitional material of subsequent trench filling, can make high-aspect-ratio
Fill process surface deposition is slack-off, the cavity inside the spacer medium of filling or gap defect is effectively avoided result in, for example, preventing
Since surface deposition velocity comparatively fast causes groove upper end corner blocking etc. in U-shaped or V-groove filling process；Nitrogen oxidation layer may be used also
Effectively to prevent oxygen-containing group or the H of formation during subsequent anneal2O avoids the oxidation to active area boundary, so that reducing has
The diminution of source region critical dimension.
Detailed description of the invention
Fig. 1 is the flow diagram of the preparation method of the fleet plough groove isolation structure of a preferred embodiment of the invention
Schematic diagram after Fig. 2 a active area nitride deposition
Schematic diagram after Fig. 2 b etching groove
Schematic diagram after Fig. 2 c silicon nitride after drawing process
Schematic diagram after the formation of Fig. 2 d liner oxidation layer
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
The preparation method of fleet plough groove isolation structure is made into one below with reference to attached drawing 1 and Fig. 2 a-2d and specific embodiment
Step is described in detail.Wherein, the schematic diagram after Fig. 2 a active area nitride deposition, the schematic diagram after Fig. 2 b etching groove, Fig. 2 c nitrogen
Schematic diagram after SiClx after drawing process, the schematic diagram after the formation of Fig. 2 d liner oxidation layer.It should be noted that attached drawing is all made of very
Simplified form, using non-accurate ratio, and only to it is convenient, clearly achieve the purpose that aid in illustrating the present embodiment.
Referring to Fig. 1, being the fleet plough groove isolation structure preparation method flow chart of steps of a preferred embodiment of the invention.
The preparation method of the fleet plough groove isolation structure of the present embodiment, comprising:
Step S1: a semiconductor substrate is provided；
Specifically, as shown in Figure 2 a, semiconductor substrate have a underlying membrane 100,100 surface of underlying membrane from bottom to up according to
It is secondary to be covered with oxide layer 101 and silicon nitride layer 102.Semiconductor substrate can be the silicon for being formed with semiconductor devices, be formed with half
It the silicon-on-insulator (SOI) of conductor device or is partly led to be formed with the II-VI of semiconductor devices or III-V compound
Body.Oxide layer 101 is generally silicon dioxide layer, and the preparation of silicon dioxide layer 101 and silicon nitride layer 102 is all made of art technology
Technique known to personnel, therefore not to repeat here.
Step S2: etching to form groove in the semiconductor substrate；
Specifically, as shown in Figure 2 b, forming photoresist layer 103 on silicon nitride layer 102.To the graphical shape of the photoresist layer
At the opening for defining shallow trench.It is that exposure mask dry etching covers 100 surface of semiconductor substrate with the patterned photoresist layer 103
Silicon dioxide layer 101 and silicon nitride layer 102, until in underlying membrane 100, silicon dioxide layer 101 and silicon nitride layer 102 shape
At groove 104, fleet plough groove isolation structure of the groove 104 to form isolation active area.In the present embodiment, the groove of formation is etched
104 be V-type or U-type groove.
Step S3: surface clean is carried out to groove 104；
Specifically, 104 surface of groove is cleaned in acid tank equipment using DHF, SC1 and SC2, removal 104 surface of groove
Particle and natural oxidizing layer obtain clean 104 surface of groove, are conducive to the growth of subsequent liner oxidation layer.
Preferably, further including laterally being carved to silicon nitride layer 102 between step S2 and step S3 as shown in Figure 2 c
The step of erosion.Specifically, a part for the silicon nitride layer 102 for being located at groove upper portion side wall is etched away, silicon nitride layer is exposed
The silicon oxide layer 101 of 102 lower sections, wherein the width for the silicon nitride layer 102 being etched can beThe etch silicon nitride
Wet-etching technology can be used in the technique of layer 102.By the way that silicon nitride layer 102 is etched away the opening that a part makes groove 104
Increase, so when subsequent spacer medium layer fills groove, is not likely to produce cavity, is conducive to spacer medium layer and fills up groove.
It should be noted that the present invention before step S 4, is not limited to above-mentioned steps S1-S3, but all existing systems
The process and technique of groove in standby fleet plough groove isolation structure can be applied to the present invention, and shallow trench isolation of the invention
The groove of structure is also not limited to structure shown in Fig. 2 c.
Step S4: liner oxidation layer 105 is formed in the inner surface for the groove that step S3 is formed；
Specifically, it is as shown in Figure 2 d to be formed by liner oxidation layer 105.In the present embodiment, liner oxidation layer 105 is nitrogen oxygen
SiClx (SiOxNy) layer, formation process are the combination of atomic layer deposition and oxidation technology.A kind of concrete technology condition is as follows:
Step 41: in the inner surface cvd nitride layer of groove 104；
It here, may include: SiH using reaction gas used by atom layer deposition process2Cl2And NH3, concrete technology
Parameter can be, but not limited to are as follows: and 400-650 DEG C of depositing temperature, reaction gas SiH2Cl2Flow be 1~5slm, NH3Flow
For 2~10slm, radio-frequency power 80-200W；By repeatedly recycling needed for available nitration case in atom layer deposition process
Thickness, the thickness of nitration case can be, but not limited to forThe material of nitration case can be silicon nitride.
For example, at 550 DEG C, using 22 circulations (Cycle), flute surfaces atomic layer deposition obtain with a thickness of
Silicon nitride.
Step 42: oxidation nitridation layer forms nitrogen oxidation layer in the inner surface of groove 104.
Here it is possible to which used reaction gas can using steam oxidation technique (ISSG) in situ come oxidation nitridation layer
Think H2And O2Mixed gas, the total flow of the mixed gas can be, but not limited to as 10~40slm, wherein H2Content can
Think 0.5~33%.Temperature in this oxidation process can be, but not limited to be 1000-1100 DEG C.Finally formed nitrogen oxidation layer
Thickness can beThe material of nitrogen oxidation layer can be silicon oxynitride.
For example, in 1050 DEG C, pressure 9Torr, H2For 10slm and O2Under the conditions of the steam oxidation in situ of 20slm,
Oxidation nitridation silicon layer and flute surfaces, ultimately form with a thickness ofLinear silicon oxynitride layer.
It should be noted that also unavoidably oxidizing away the surface of trenched side-wall, finally during oxidation nitridation layer
The nitrogen oxidation layer of formation not only can be improved the round and smooth degree of shallow trench and improve the ambient stress in groove, but also can be effectively
Active area critical dimension is reduced to reduce.
This is because:
On the one hand the oxidation to trenched side-wall with the top corner of round and smooth groove and can remove in etching process in groove table
The damage that face introduces, to alleviate the stress in groove, to be conducive to being sufficient filling with for subsequent trench；Also, due to be
It deposited nitration case to be aoxidized again later, it is possible to avoid directly aoxidizing to trenched side-wall material trenched side-wall
Severe attrition, and then increase oxygen-containing group or the H of formation during subsequent anneal2The difficulty of diffusion of the O into semiconductor substrate
Degree, it is possible thereby to avoid the oxidation to active area boundary, avoids the diminution of active area critical dimension；
On the other hand, nitrogen oxidation layer acts not only as the transitional material of subsequent trench filling, can make high-aspect-ratio
Fill process surface deposition is slack-off, the cavity inside the spacer medium of filling or gap defect is effectively avoided result in, for example, preventing
Since surface deposition velocity comparatively fast causes groove upper end corner blocking etc. in U-shaped or V-groove filling process；Nitrogen oxidation layer may be used also
Effectively to prevent oxygen-containing group or the H of formation during subsequent anneal2O avoids the oxidation to active area boundary, so that reducing has
The diminution of source region critical dimension.
Step S5: spacer medium layer is filled in the trench；
Specifically, spacer medium can be silica；The method of filling can be, but not limited to as vapor deposition method.
Step S6: high annealing is carried out to spacer medium layer.
It should be pointed out that the process in the present invention after step s4 is not limited to step S5-S6, it can also include it
He is used to complete the technical process of fleet plough groove isolation structure；
The fleet plough groove isolation structure preparation method that present embodiment provides further includes annealing, planarization, and cleaning etc.
Conventional steps, the process that above-mentioned technique is well known to the skilled person, therefore not to repeat here.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrate only for the purposes of explanation and
, it is not intended to limit the invention, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection scope that the present invention is advocated should be subject to described in claims.
Claims (8)
1. a kind of preparation method of fleet plough groove isolation structure, including successively carry out: groove is formed in the semiconductor substrate, in groove
It is middle to form linear oxide layer, fill spacer medium layer and high annealing in the trench, which is characterized in that described to form linear oxidation
Layer method include:
Step S41: in the inner surface cvd nitride layer of the groove；
Step S42: aoxidizing the nitration case, forms nitrogen oxidation layer in the inner surface of the groove, the nitrogen oxidation layer includes quilt
The nitration case of oxidation and the surface of the groove contacted with the nitration case.
2. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that described in semiconductor substrate
The middle process for forming groove specifically includes:
Step S1: a semiconductor substrate is provided；
Step S2: etched technique forms groove in the semiconductor substrate；
Step S3: surface clean is carried out to the groove.
3. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that in the step 41, adopt
The nitration case is deposited with atom layer deposition process.
4. the preparation method of fleet plough groove isolation structure according to claim 3, which is characterized in that the atomic layer deposition work
Reaction gas used by skill includes: SiH2Cl2And NH3, technological parameter are as follows: and 400-650 DEG C of depositing temperature, reaction gas
SiH2Cl2Flow be 1~5slm, NH3Flow be 2~10slm, radio-frequency power 80-200W.
5. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that in the step 42, adopt
The nitration case is aoxidized with steam oxidation technique in situ.
6. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that in the step 41, institute
State nitration case with a thickness of
7. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that in the step 42, institute
State nitrogen oxidation layer with a thickness of
8. the preparation method of fleet plough groove isolation structure according to claim 1, which is characterized in that in the step 42, institute
The material for stating nitrogen oxidation layer is silicon oxynitride.
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| CN104779195A (en) * | 2015-04-15 | 2015-07-15 | 上海华力微电子有限公司 | Preparation method of shallow trench isolation structure |
| CN106803484B (en) * | 2015-11-26 | 2021-08-10 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107887322A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of isolation structure and the forming method of semiconductor devices |
| CN111128854A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Shallow trench isolation structure and forming method thereof |
| US11881428B2 (en) | 2021-01-05 | 2024-01-23 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154617A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing isolation structure of shallow plough groove |
| CN101452875A (en) * | 2007-12-03 | 2009-06-10 | 东部高科股份有限公司 | Method of forming isolation layer in semiconductor device |
| KR20090063657A (en) * | 2007-12-14 | 2009-06-18 | 주식회사 동부하이텍 | Method for fabricating a sti |
| KR20110075403A (en) * | 2009-12-28 | 2011-07-06 | 주식회사 동부하이텍 | Method for fabricating ldram capacitor |
| CN103000565A (en) * | 2011-09-14 | 2013-03-27 | 和舰科技(苏州)有限公司 | Method for improving isolation properties of shallow trenches in CMOS (complementary metal oxide semiconductor) process |
| CN103295950A (en) * | 2012-02-27 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolating structure manufacturing method |
| CN103531522A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
| CN103531523A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
| CN103855073A (en) * | 2014-03-27 | 2014-06-11 | 上海华力微电子有限公司 | Preparation method of shallow-groove isolation structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090008004A (en) * | 2007-07-16 | 2009-01-21 | 삼성전자주식회사 | Semiconductor device having sti structure and method for manufacturing the same |
-
2014
- 2014-08-27 CN CN201410427369.0A patent/CN104157602B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154617A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing isolation structure of shallow plough groove |
| CN101452875A (en) * | 2007-12-03 | 2009-06-10 | 东部高科股份有限公司 | Method of forming isolation layer in semiconductor device |
| KR20090063657A (en) * | 2007-12-14 | 2009-06-18 | 주식회사 동부하이텍 | Method for fabricating a sti |
| KR20110075403A (en) * | 2009-12-28 | 2011-07-06 | 주식회사 동부하이텍 | Method for fabricating ldram capacitor |
| CN103000565A (en) * | 2011-09-14 | 2013-03-27 | 和舰科技(苏州)有限公司 | Method for improving isolation properties of shallow trenches in CMOS (complementary metal oxide semiconductor) process |
| CN103295950A (en) * | 2012-02-27 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolating structure manufacturing method |
| CN103531522A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
| CN103531523A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
| CN103855073A (en) * | 2014-03-27 | 2014-06-11 | 上海华力微电子有限公司 | Preparation method of shallow-groove isolation structure |
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Effective date of registration: 20200413 Address after: 201203 1060, room 1, 298 Cambridge East Road, Pudong New Area, Shanghai. Patentee after: SHANGHAI HUALI INTEGRATED CIRCUIT MANUFACTURING Co.,Ltd. Address before: 201210, Gauss road 568, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: Shanghai Huali Microelectronics Corp. |
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