CN108039337B - Method for forming shallow trench isolation structure in FDSOI (fully drawn silicon on insulator) process - Google Patents

Method for forming shallow trench isolation structure in FDSOI (fully drawn silicon on insulator) process Download PDF

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CN108039337B
CN108039337B CN201711220855.5A CN201711220855A CN108039337B CN 108039337 B CN108039337 B CN 108039337B CN 201711220855 A CN201711220855 A CN 201711220855A CN 108039337 B CN108039337 B CN 108039337B
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shallow trench
silicon
oxide layer
fdsoi
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袁晓龙
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

The invention discloses a method for forming a shallow trench isolation structure in an FDSOI (fully drawn SOI) process, which comprises the following steps of: providing an FDSOI substrate structure, and forming a liner oxide layer and a first silicon nitride layer on the surface of top silicon; step two, defining a forming area of a shallow groove by photoetching, opening a hard mask layer of the forming area of the shallow groove, and etching the top silicon layer, the oxygen burying layer and the bulk silicon layer in sequence by taking the hard mask layer as a mask to form the shallow groove; thirdly, pre-cleaning is carried out, and the dilution degree of the HF solution and the cleaning time of the HF solution in the pre-cleaning are controlled to reduce the protruding amount of the top layer silicon at the edge of the shallow trench; step four, growing a linear oxide layer by adopting an atomic layer deposition process; and step five, filling an oxide layer of the shallow trench by adopting an HARP process. The invention can reduce the consumption of the top silicon in the growth process of the linear oxide layer, thereby improving the electrical property of the device and enabling the electrical property of the device to reach the required value.

Description

Method for forming shallow trench isolation structure in FDSOI (fully drawn silicon on insulator) process
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a shallow trench isolation in a Fully Depleted Silicon On Insulator (FDSOI) process.
Background
In order to meet the requirement of continuously reducing the size of a semiconductor device in proportion in the manufacturing of an integrated circuit, a plane type FDSOI provides another effective technical solution besides a three-dimensional structure. A typical feature of the FDSOI-based process is that a wafer having a Buried Oxide (BOX) layer and an ultra-thin silicon-on-insulator (SOI) layer is used, and in this application, the wafer is generally composed of a silicon substrate, which is referred to as bulk silicon, the buried oxide layer forms a surface with the bulk silicon, and the ultra-thin silicon formed on the surface of the buried oxide layer, i.e., the SOI layer, is referred to as top silicon. The formation of the ultra-thin transistor in the ultra-thin top layer silicon in the FDSOI can well control the short channel effect, and further can reduce the power supply voltage; due to the presence of the buried silicon oxide layer, the modulation of the threshold voltage can be performed by changing the body bias (body bias); in addition, the FDSOI-based process can directly follow the design architecture of bulk CMOS.
Typically, in the FDSOI process of 22nm and below, the minimum Active Area (AA) width is around 80nm and the top silicon thickness of the active area is around 6 nm. From this, it is known that the top silicon of the active region has a width of 80nm and a thickness of only 6nm, and has a short width and an ultra-thin thickness. The loss of the top silicon in the AA region can greatly affect the electrical performance of the formed device. In the conventional 28nm process node, Shallow Trench Isolation (STI) is formed, a precleaning process is performed before a linear Oxidation process (Liner Oxidation) for forming a shallow trench, and the precleaning process usually adopts a wet process. The dilute hydrofluoric acid (HF) during wet processing causes excessive loss of pad oxide (pad oxide) and BOX, where the top silicon at the edge of the AA region is exposed. After the pre-cleaning treatment, subsequent Liner Oxidation growth is carried out, In the prior art, Liner Oxidation is usually carried out by high-temperature Oxidation technology such as In-Situ Steam Generation (ISSG), and the exposed top silicon is oxidized together In the process of forming Liner Oxidation, so that the loss of the top silicon at the edge of the AA area is caused; where ISSG is also typically translated into in situ steam generation or in situ steam generation, etc. At the extremely small device scale, since the width and thickness of the active region are small in nature, the loss of the top layer silicon at the edge of the AA region is not negligible in size relative to the width and thickness of the active region, and thus the electrical property of the device is greatly adversely affected.
Disclosure of Invention
The invention aims to provide a method for forming a shallow trench isolation structure in an FDSOI (fully-doped silicon on insulator) process, which can reduce the loss of top silicon at the edge of an active region and improve the electrical performance of a device.
In order to solve the technical problem, the method for forming the shallow trench isolation structure in the FDSOI process provided by the invention comprises the following steps:
providing an FDSOI substrate structure, wherein the FDSOI substrate comprises a bulk silicon layer, an oxygen buried layer and top silicon, the oxygen buried layer is formed on the surface of the bulk silicon layer, and the top silicon is formed on the surface of the oxygen buried layer; and forming a hard mask layer formed by overlapping a liner oxide layer and a first silicon nitride layer on the surface of the top layer silicon.
Step two, defining a forming area of a shallow groove by photoetching, wherein the area outside the shallow groove is an active area; and opening the first silicon nitride layer and the pad oxide layer in the formation region of the shallow trench, and sequentially etching the top layer silicon, the oxygen burying layer and the bulk silicon layer by taking the opened hard mask layer as a mask to form the shallow trench.
And thirdly, pre-cleaning before forming the linear oxide layer, wherein the pre-cleaning comprises a process of removing the oxide film on the surface of the shallow trench by adopting an HF solution, and the dilution degree of the HF solution and the cleaning time of the HF solution are controlled so that the consumption of the liner oxide layer and the buried oxide layer is reduced under the condition of ensuring the removal of the oxide film on the surface of the shallow trench, thereby reducing the protruding amount of the top silicon at the edge of the shallow trench.
And fourthly, growing a linear oxide layer by adopting an atomic layer deposition process, reducing the thermal budget in the growth process of the linear oxide layer by utilizing the atomic layer deposition process and reducing the consumption of the top layer silicon in the growth process of the linear oxide layer by combining with the reduction of the protruding amount of the top layer silicon at the edge of the shallow trench in the third step, thereby improving the electrical property of the device and enabling the electrical property of the device to reach a required value.
And fifthly, filling an oxide layer of the shallow trench by adopting an HARP process to form a shallow trench isolation structure.
The further improvement is that the FDSOI process is an FDSOI process under 22 nm.
A further improvement is that the width of the minimum active region is below 80 nm.
The further improvement is that the thickness of the top layer silicon is less than 6 nm.
In a further improvement, the consumption of the pad oxide layer and the buried oxide layer in the pre-cleaning in the third step is controlled to be
Figure BDA0001486367440000021
A further improvement is that the HF solution in the pre-rinse in step three has an HF: the volume ratio of H2O is 1: 100-1: 1000; the cleaning time of the HF solution is 0.5-10 minutes; the cleaning temperature of the HF solution is 10-70 ℃.
The further improvement is that the temperature of the atomic layer deposition process is 200-500 ℃.
In a further improvement, the thickness of the linear oxide layer grown in the fourth step is
Figure BDA0001486367440000031
In a further improvement, in the pre-cleaning process of the third step, before the cleaning with the HF solution, the following steps are further included:
ozone deionized water (DIO3) was used to remove organics.
In a further improvement, in the pre-cleaning process of the third step, after the cleaning with the HF solution, the following steps are further included:
removing residual microparticles and organic matters on the surface of the FDSOI substrate by using No. 1 liquid (SC 1);
residual atomic and ionic contaminants were removed using solution No. 2 (SC 2).
The invention has specially set the pre-cleaning process before the linear oxide layer is formed in the forming process of the shallow trench isolation structure in the FDSOI process and the forming process of the linear oxide layer, and the consumption of the liner oxide layer and the buried oxide layer is reduced under the condition of ensuring the removal of the oxide film on the surface of the shallow trench by controlling the dilution degree of the HF solution in the pre-cleaning and the cleaning time of the HF solution, so that the protruding amount of the top silicon at the edge of the shallow trench is reduced; and an atomic layer deposition process with low thermal budget is adopted in the linear oxide layer forming process, so that the oxidation of the protruding part of the top layer silicon at the edge of the shallow trench in the linear oxide layer forming process can be reduced by the low thermal budget, and finally the loss of the top layer silicon at the edge of the active area can be reduced and controlled by combining the reduction of the protruding amount of the top layer silicon at the edge of the shallow trench in the precleaning and the reduction of the oxidation of the protruding part of the top layer silicon at the edge of the shallow trench in the linear oxide layer forming process, so that the electrical performance of the device can be improved and the electrical performance of the device can reach a required value.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C are schematic views of a device structure in various steps of a method for forming a shallow trench isolation structure in a conventional FDSOI process;
FIG. 2 is a flow chart of a method for forming a shallow trench isolation structure in an FDSOI process according to an embodiment of the present invention;
fig. 3A-3C are schematic views of the device structure in the steps of the method for forming the shallow trench isolation structure in the FDSOI process according to the embodiment of the invention.
Detailed Description
The method of the embodiment of the invention is obtained on the basis of analyzing the problems in the prior art, and before the method of the embodiment of the invention is described in detail, the following method is introduced: as shown in fig. 1A to fig. 1C, the schematic device structure diagram in each step of the method for forming a shallow trench isolation structure in the conventional FDSOI process is shown, and the method for forming a shallow trench isolation structure in the conventional FDSOI process includes the following steps:
step one, as shown in fig. 1A, providing an FDSOI substrate structure, where the FDSOI substrate includes a bulk silicon layer 101, a buried oxide layer 102 and a top silicon layer 103, the buried oxide layer 102 is formed on the surface of the bulk silicon layer 101, and the top silicon layer 103 is formed on the surface of the buried oxide layer 102; a hard mask layer formed by overlapping a pad oxide layer 104 and a first silicon nitride layer 105 is formed on the surface of the top layer silicon 103.
Step two, as shown in fig. 1A, defining a formation region of a shallow trench 201 by photolithography, wherein a region outside the shallow trench 201 is an active region; and opening the first silicon nitride layer 105 and the pad oxide layer 104 in the formation region of the shallow trench 201, and sequentially etching the top silicon 103, the buried oxide layer 102 and the bulk silicon layer 101 by using the opened hard mask layer as a mask to form the shallow trench 201.
Step three, as shown in fig. 1B, a precleaning process is performed before the linear oxide layer 203 is formed. In the prior art, the pre-cleaning includes a process of removing an oxide film on the surface of the shallow trench 201 by using an HF solution, and the cleaning process of the HF solution of the prior art consumes the pad oxide layer 4 and the buried oxide layer, so that the top silicon 103 may form a protruding region on the side surface of the shallow trench 201 as shown by the dotted line 202.
Step four, as shown in fig. 1C, an ISSG process is used to grow the linear oxide layer 203, and the protruding region of the top silicon 103 shown by the dotted circle 202 is easily oxidized by the thermal process of the ISSG process, so that the size of the active region is reduced, and the performance of the device is finally affected.
And step five, filling an oxide layer of the shallow trench 201 by adopting an HARP process to form a shallow trench isolation structure.
In the conventional method, the edge region of the top layer silicon 103 formed in fig. 1B is easily oxidized by combining the protruding region of the top layer silicon 103 with the subsequent ISSG process with a high temperature thermal process, the oxidized size of the oxidized region of the edge region of the top layer silicon 103 is negligible relative to the size of the whole AA region when the size of the active region is large, but as the process node is increased, such as in the FDSOI process below 22nm, the oxidized size of the edge region of the top layer silicon 103 formed by the above conventional method becomes non-negligible, and the oxidized edge region of the top layer silicon 103 may have a great adverse effect on the electrical property of the device.
The method of the embodiment of the invention comprises the following steps:
fig. 2 is a flow chart of a method for forming a shallow trench isolation structure in an FDSOI process according to an embodiment of the present invention; as shown in fig. 3A to fig. 3C, the schematic device structure diagrams in the steps of the method for forming a shallow trench isolation structure in the FDSOI process according to the embodiment of the present invention are shown, and the method for forming a shallow trench isolation structure in the FDSOI process according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing an FDSOI substrate structure, where the FDSOI substrate includes a bulk silicon layer 1, a buried oxide layer 2 and a top silicon layer 3, the buried oxide layer 2 is formed on the surface of the bulk silicon layer 1, and the top silicon layer 3 is formed on the surface of the buried oxide layer 2; and forming a hard mask layer formed by overlapping a pad oxide layer 4 and a first silicon nitride layer 5 on the surface of the top layer silicon 3.
In the embodiment of the invention, the FDSOI process is an FDSOI process with the thickness of less than 22 nm. The width of the minimum active region is less than 80 nm. The thickness of the top layer silicon 3 is less than 6 nm.
Step two, as shown in fig. 3A, defining a formation region of a shallow trench 301 by photolithography, wherein a region outside the shallow trench 301 is an active region; and opening the first silicon nitride layer 5 and the pad oxide layer 4 in the formation region of the shallow trench 301, and sequentially etching the top layer silicon 3, the buried oxide layer 2 and the bulk silicon layer 1 by using the opened hard mask layer as a mask to form the shallow trench 301.
And step three, as shown in fig. 3B, performing precleaning before forming the linear oxide layer 303, wherein the precleaning includes a process of removing an oxide film on the surface of the shallow trench 301 by using an HF solution, and controlling the dilution degree of the HF solution and the cleaning time of the HF solution so as to reduce consumption of the pad oxide layer 4 and the buried oxide layer under the condition of ensuring removal of the oxide film on the surface of the shallow trench 301, thereby reducing the protruding amount of the top layer silicon 3 at the edge of the shallow trench 301. The protruding area of the top layer silicon 3 at the side of the shallow trench 301 is shown as a dashed circle 302.
In the embodiment of the invention, the consumption of the liner oxide layer 4 and the buried oxide layer is controlled in the pre-cleaning
Figure BDA0001486367440000051
Preferably, the HF solution in the pre-cleaning has an HF: the volume ratio of H2O is 1: 100-1: 1000; the cleaning time of the HF solution is 0.5-10 minutes; the cleaning temperature of the HF solution is 10-70 ℃.
In the pre-cleaning process, the following steps are also included before the cleaning of the HF solution is carried out:
ozone deionized water is adopted to remove organic matters.
The method also comprises the following steps after the cleaning of the HF solution is carried out:
removing residual microparticles and organic matters on the surface of the FDSOI substrate by using No. 1 liquid;
and (3) removing residual atomic and ionic pollutants by using No. 2 liquid.
Step four, as shown in fig. 3C, growing the linear oxide layer 303 by using an atomic layer deposition process, and reducing the thermal budget in the growth process of the linear oxide layer 303 by using the atomic layer deposition process and reducing the consumption of the top silicon 3 in the growth process of the linear oxide layer 303 by combining with the reduction of the protruding amount of the top silicon 3 at the edge of the shallow trench 301 in the step three, so as to improve the electrical performance of the device and enable the electrical performance of the device to reach a required value.
In the embodiment of the invention, the temperature of the atomic layer deposition process is 200-500 ℃.
The thickness of the linear oxide layer 303 is
Figure BDA0001486367440000061
And step five, filling an oxide layer of the shallow trench 301 by adopting an HARP process to form a shallow trench isolation structure.
The embodiment of the invention particularly sets a pre-cleaning process before the linear oxidation layer 303 is formed and a forming process of the linear oxidation layer 303 in the forming process of the shallow trench isolation structure in the FDSOI process, and reduces the consumption of a liner oxidation layer 4 and a buried oxidation layer under the condition of ensuring the removal of an oxidation film on the surface of a shallow trench 301 by controlling the dilution of an HF solution and the cleaning time of the HF solution in the pre-cleaning, thereby reducing the protruding amount of top silicon 3 at the edge of the shallow trench 301; and an atomic layer deposition process with low thermal budget is adopted in the forming process of the linear oxide layer 303, so that the oxidation of the protruding part of the top layer silicon 3 at the edge of the shallow trench 301 in the forming process of the linear oxide layer 303 can be reduced by the low thermal budget, and finally the loss of the top layer silicon 3 at the edge of the active area can be reduced and controlled by combining the reduction of the protruding amount of the top layer silicon 3 at the edge of the shallow trench 301 in the pre-cleaning process and the reduction of the oxidation of the protruding part of the top layer silicon 3 at the edge of the shallow trench 301 in the forming process of the linear oxide layer 303, so that the electrical performance of the device can be improved and the electrical performance of the device can reach a required value.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (6)

1. A method for forming a shallow trench isolation structure in an FDSOI process is characterized by comprising the following steps:
providing an FDSOI substrate structure, wherein the FDSOI substrate comprises a bulk silicon layer, an oxygen buried layer and top silicon, the oxygen buried layer is formed on the surface of the bulk silicon layer, and the top silicon is formed on the surface of the oxygen buried layer; forming a hard mask layer formed by overlapping a liner oxide layer and a first silicon nitride layer on the surface of the top silicon layer;
the FDSOI process is an FDSOI process with the thickness of less than 22 nm;
the width of the minimum active region is less than 80 nm;
the thickness of the top layer silicon is less than 6 nm;
step two, defining a forming area of a shallow groove by photoetching, wherein the area outside the shallow groove is an active area; opening the first silicon nitride layer and the pad oxide layer in the formation region of the shallow trench, and sequentially etching the top silicon layer, the buried oxide layer and the bulk silicon layer by taking the opened hard mask layer as a mask to form the shallow trench;
thirdly, pre-cleaning before forming the linear oxide layer, wherein the pre-cleaning comprises a process of removing the oxide film on the surface of the shallow trench by adopting an HF solution, and the dilution degree of the HF solution and the cleaning time of the HF solution are controlled so that the consumption of the liner oxide layer and the oxygen burying layer is reduced under the condition of ensuring the removal of the oxide film on the surface of the shallow trench, thereby reducing the protrusion amount of the top silicon at the edge of the shallow trench;
controlling consumption of the pad oxide layer and the buried oxide layer in the pre-cleaning
Figure FDA0002567868810000011
Step four, growing a linear oxide layer by adopting an atomic layer deposition process, wherein the linear oxide layer is made of silicon oxide, and reducing the consumption of the top layer silicon in the growth process of the linear oxide layer by utilizing the atomic layer deposition process and combining the reduction of the protrusion amount of the top layer silicon at the edge of the shallow trench in the step three, so that the electrical property of the device is improved and the electrical property of the device reaches a required value;
and fifthly, filling an oxide layer of the shallow trench by adopting an HARP process to form a shallow trench isolation structure.
2. The method of claim 1, wherein the shallow trench isolation structure in the FDSOI process comprises: HF of the HF solution in the pre-rinse in step three: the volume ratio of H2O is 1: 100-1: 1000; the cleaning time of the HF solution is 0.5-10 minutes; the cleaning temperature of the HF solution is 10-70 ℃.
3. The method of claim 1, wherein the shallow trench isolation structure in the FDSOI process comprises: the temperature of the atomic layer deposition process is 200-500 ℃.
4. The method of claim 1, wherein the shallow trench isolation structure in the FDSOI process comprises: the thickness of the linear oxide layer grown in the fourth step is
Figure FDA0002567868810000021
5. The method of claim 1, wherein the shallow trench isolation structure in the FDSOI process comprises: in the pre-cleaning process of the third step, before the cleaning with the HF solution, the following steps are further included:
ozone deionized water is adopted to remove organic matters.
6. The method of claim 1 or 5, wherein the shallow trench isolation structure is formed by: in the pre-cleaning process of the third step, after the cleaning with the HF solution, the following steps are further included:
removing residual microparticles and organic matters on the surface of the FDSOI substrate by using No. 1 liquid;
and (3) removing residual atomic and ionic pollutants by using No. 2 liquid.
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CN1447412A (en) * 2002-03-22 2003-10-08 三洋电机株式会社 Mfg. method of semiconductor device
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