CN110071050B - Chip interconnection structure and preparation method thereof - Google Patents

Chip interconnection structure and preparation method thereof Download PDF

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Publication number
CN110071050B
CN110071050B CN201910331322.7A CN201910331322A CN110071050B CN 110071050 B CN110071050 B CN 110071050B CN 201910331322 A CN201910331322 A CN 201910331322A CN 110071050 B CN110071050 B CN 110071050B
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nano
metal film
chip
metal
size
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CN110071050A (en
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刘旭
叶怀宇
张卫红
敖日格力
李俊
韩飞
张国旗
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Southwest University of Science and Technology
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Shenzhen Third Generation Semiconductor Research Institute
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Priority to PCT/CN2019/123823 priority patent/WO2020215738A1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/05—Metallic powder characterised by the size or surface area of the particles
    • B22F1/052—Metallic powder characterised by the size or surface area of the particles characterised by a mixture of particles of different sizes or by the particle size distribution
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/05—Metallic powder characterised by the size or surface area of the particles
    • B22F1/054—Nanosized particles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F3/00—Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sintering; Apparatus specially adapted therefor ; Presses and furnaces
    • B22F3/10—Sintering only
    • B22F3/11—Making porous workpieces or articles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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Abstract

The invention provides a chip interconnection structure and a preparation method thereof, wherein the structure comprises the following steps: the chip comprises N nano metal film small pieces, N is more than or equal to 2, and the substrate, wherein the nano metal film small pieces comprise first-size nano metal particles and second-size nano metal particles, and the diameters of the first-size nano metal particles and the second-size nano metal particles are different. The problems of high porosity, low thermal conductivity and chip inclination of the original metal sintering film are solved, the compactness is improved after sintering, and the thermal conductivity of the interconnection layer is improved.

Description

Chip interconnection structure and preparation method thereof
Technical Field
The invention relates to the field of chip packaging interconnection, in particular to a preparation technology of a metal film for sintering.
Background
In the field of power semiconductor packaging, the problem that the interconnection material with low temperature process, high temperature service, matched thermal expansion coefficient, high heat conductivity and electric conductivity and low cost is required to be solved urgently now is sought. The traditional material process of welding and wire bonding has the problems of low melting point, high-temperature creep failure, wire winding, parasitic parameters and the like which cannot be solved, and the novel interconnection material is developing from welding to sintering technology. By reducing the size of the sintering particles and lowering the sintering temperature, the nano metal particle sintering technology has become the most promising technology in the novel interconnection material of the power semiconductor device.
At present, the advanced process represented by nano silver sintering gradually becomes the mainstream of power semiconductor device packaging interconnection, and main packaging application manufacturers at home and abroad enter practical and large-scale use. However, the patent, material, process and equipment for sintering nano silver are mainly controlled by foreign manufacturers, and the development in China is greatly limited. Meanwhile, the nano-silver sintering technology is also insufficient: 1) the silver material itself is expensive, which limits its widespread use. 2) The difference in thermal expansion coefficients of the silver and SiC chip backside materials requires the addition of additional intermediate metal layers to improve interconnect performance, thereby increasing process complexity and cost. 3) The silver layer has electromigration phenomenon, which is not favorable for long-term reliable application of power devices. The nano copper particles similar to the nano silver can be melted at low temperature, the melting point of the sintered nano copper particles is close to that of a copper simple substance material (1083 ℃), and a stable metal interconnection layer can be constructed. Due to the characteristics of single-component metal, the problem of service reliability under the thermal cycle effect of an alloy material is solved, copper-copper bonding is realized, the problem of thermal expansion coefficient matching between a chip and a substrate is solved, and the reliability problem caused by the electromigration phenomenon is avoided. Compared with nano silver particles, the material and processing cost of interconnection packaging is effectively reduced. More importantly, the practical application and industrialization of the concept of 'All copper' (All copper) can be further promoted from the field of chip packaging application, and the innovative development of the semiconductor industry is promoted.
Prior art patent document CN103262172A discloses a sintered material and a thin layer made of the sintered material, and a method for attaching the material. The thin layer is composed of metal powder, soldering paste, adhesive and solvent. Wherein the metal powder comprises gold, palladium, silver, copper, aluminum, silver palladium alloy or gold palladium alloy, and may further comprise one or more functional additives. The metal powder includes nanoparticles. Metal powder is applied to the substrate and the material on the substrate is dried to form a thin layer. The substrate material comprises polyester fiber, and the prior art has the defects that the nano metal layer on the substrate has single component and size, so that the porosity is high after sintering, the electric conduction and heat conduction effects are poor, and the like.
Prior art No. two is a patent document CN105492198A, which discloses a composite and multilayer silver film for electrical and mechanical parts, wherein reinforcing particles or fibers are added to the sinterable silver layer to improve its strength. A reinforcing metal foil layer is further added on the layer of slightly dissolvable silver particles, which may be silver, copper, gold or any other metal or any alloy, or may be a metal polymer or ceramic foil, or may be a composite or plated structure with layers of different metals and alloys. The reinforcing metal foil layer may be applied in the form of a solid, perforated or mesh, etc. However, the prior art has problems in that the addition of the multi-layer composite metal film and the reinforced metal foil layer increases the number of interfaces of the connection layer after sintering, thereby possibly reducing the connection strength; in addition, a single size silver particle layer, which has a large porosity after sintering, reduces thermal conductivity, electrical conductivity, and shear stress, thereby reducing reliability.
Prior Art three is a Chinese patent application having patent publication No. CN106660120A, which discloses a discrete sintered material and a fixing method using the same. The material includes a metal powder including shell structured nanoparticles and a substrate including a polymer. The metal powder film is printed or cast on the polymer substrate and the material is formed into an array of discrete shapes using a specific method. The method has the disadvantages that on one hand, a large-piece sintered metal film is used, and gas generated in the middle position is not effectively discharged in the sintering process, so that the problems of large porosity of an interconnection layer after sintering and the like can be caused; the direct use of printing or casting to prepare discrete shapes may result in the shape of discrete patches being dependent on the design of the printing screen, making shape changes difficult; meanwhile, the problems of rough edge, uneven thickness, low resolution, etc. are caused.
Disclosure of Invention
In order to overcome the defects of the prior art and avoid the problems of high porosity, low thermal conductivity and chip inclination of the original metal sintering film, the invention provides a chip interconnection structure, which comprises:
the chip is provided with a plurality of chips,
n nano metal film small pieces, N is more than or equal to 2,
a substrate, a first electrode and a second electrode,
the nano-metal film chip comprises first-size nano-metal particles and second-size nano-metal particles,
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
Preferably, the nano-metal particle material is copper.
Preferably, the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver-nickel alloy or copper-aluminum alloy.
Preferably, of the first-size and second-size nano-metal particles, the larger-size nano-metal particles have a diameter of 1nm < D <10 μm; the diameter of the metal nanoparticles with smaller size in the first size metal nanoparticles and the second size metal nanoparticles is 0.5nm < d <20 nm.
Preferably, the nano metal film small pieces are positioned between the chip and the substrate, and the nano metal film small pieces are arranged at intervals; one or more layers of nano metal film small pieces are arranged between the chip and the substrate.
Preferably, the N single-layer nano-metal platelets are in length A1Width of one, B1A is an array of1*B1。
Preferably, the N multilayer nano-metal platelets are according to length a2Width of one, B2A is an array of2*B2。
Preferably, the multi-layered nano-metal platelet includes:
a first organic medium material layer, a second organic medium material layer,
a second organic medium material layer;
the first organic medium material layer contains first-size nano-metal particles,
the first organic medium material layer comprises second-size nano metal particles;
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
Preferably, the distribution mode of the multi-layer nano metal film platelets is as follows:
a first metal film layer comprising a length A31Width of one, B31An arrangement of single-layer nano-metal film platelets or multi-layer nano-metal film platelets, N1＝A31*B31；
A second metal film layer comprising a length A32Width of one, B32An arrangement of single-layer nano-metal film platelets or multi-layer nano-metal film platelets, N2＝A32*B32；
……
An nth metal film layer including a length A3nWidth of one, B3nAn arrangement of single-layer nano-metal film platelets or multi-layer nano-metal film platelets, Nn＝A3n*B3n；
N＝N1+N2+…+Nn。
A chip interconnection structure connection method comprises the following steps:
step 1: preparing a nano metal film, wherein the nano metal film comprises first-size nano metal particles and second-size nano metal particles, and the diameters of the first-size nano metal particles and the second-size nano metal particles are different;
step 2: cutting the nano metal film to obtain N nano metal film chips;
and step 3: attaching one surface of the nano metal film chip to the bottom of the chip;
and 4, step 4: attaching the other side of the substrate and the other side of the nano metal film chip;
and 5: interconnecting the chip and the substrate.
Preferably, the nano-metal particle material is copper.
Preferably, the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver-nickel alloy or copper-aluminum alloy.
Preferably, of the first-size and second-size nano-metal particles, the larger-size nano-metal particles have a diameter of 1nm < D <10 μm; the diameter of the metal nanoparticles with smaller size in the first size metal nanoparticles and the second size metal nanoparticles is 0.5nm < d <20 nm.
Preferably, the nano metal film small pieces are positioned between the chip and the substrate, and the nano metal film small pieces are arranged at intervals; one or more layers of nano metal film small pieces are arranged between the chip and the substrate.
Preferably, the distribution mode of the nano metal film platelets of the layer comprises:
and sticking the nano metal film chips to the bottom of the chip according to the length of A and the width of B.
Preferably, the distribution mode of the multi-layer nano metal film platelets comprises:
the length A is31Width of one, B31N in total1Arranging and sticking the small metal film pieces to the bottom of the chip according to a design, and then drying to obtain a first metal film layer;
the length A is32Width of one, B32N in total2The small metal film pieces are arranged according to the design and adhered to the bottom of the first metal film layer, and then drying treatment is carried out to obtain a second metal film layer;
……
the length A is3nWidth of one, B3nN in totalnAnd arranging and sticking the small metal film pieces to the bottom of the n-1 metal film layer according to the design, and then drying to obtain the n metal film layer.
Preferably, the step 3 and the step 4 further comprise a drying treatment.
Preferably, the step 4 further comprises:
step 5.1: peeling the support substrate;
step 5.2: placing the chip with the adhered multi-layer metal film on a substrate;
step 5.3: the multilayer metal film chip is heated in a sintering furnace, and the substrate and the multilayer metal film chip are interconnected with the pressure assistance.
The metal film is provided with a plurality of discontinuous small pieces and arranged between the chip and the substrate according to the pre-design, and small piece gaps left by the discrete arrangement can be used as channels for discharging gas during sintering, so that the compactness after sintering is improved, and the thermal conductivity of the interconnection layer is improved; meanwhile, as the sintering is carried out, the small metal film pieces can generate deformation in the x and y directions due to the limitation of the z direction and are contacted with each other to form a compact sintering layer, and compared with the use of a single large metal film, the problem of inclination in the chip die bonding process can be effectively reduced.
Drawings
Fig. 1 is a schematic view of a non-continuous nano-copper sintered film according to an embodiment of the present invention.
Fig. 2 is a schematic view of a method for sintering an interconnect structure using a single-layer discontinuous metal film according to a second embodiment.
Fig. 3 is a schematic view of a method for sintering an interconnect structure using multiple discontinuous metal films according to a third embodiment.
Fig. 4 is a schematic view of a method for sintering an interconnect structure using multiple layers of periodically discontinuous metal films according to a fourth embodiment.
The chip comprises a discretely arranged nano copper film (before sintering) 1, a chip (set to be transparent for convenient observation) 2, a substrate 3, a discretely arranged nano copper film (during sintering) 4, a complete interconnection layer (after sintering) 5, a single-layer composite nano copper film small piece 6, large-size nano copper particles 7, small-size nano copper particles 8, a first material layer 9 and a second material layer 10.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, the following examples of which are intended to be illustrative only and are not to be construed as limiting the scope of the invention.
Example one
The present embodiment provides a chip substrate connection structure and method using a nano metal film, as shown in fig. 1, including:
the chip is provided with a plurality of chips,
n pieces of preformed metal film, N ≧ 2, N ^ N2, N is a natural number (e.g., N ═ 4, 9, 16 …)
A substrate, a first electrode and a second electrode,
the metal film comprises an organic carrier and nano metal particles;
the metal film can be of a single-layer structure or a multi-layer structure;
the single-layer structure can contain first-size nano metal particles and second-size nano metal particles mixed together;
the multilayer structure includes a layer of first-sized nano-metal particles and a layer of second-sized nano-metal particles,
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
The nano metal particle material is copper.
The nano metal particle material is gold, palladium, silver, copper, aluminum, silver palladium alloy, gold palladium alloy, copper silver nickel alloy or copper aluminum alloy.
The diameter of the larger nano metal particle in the first-size nano metal particles and the second-size nano metal particles is 1nm < D <10 mu m. The discontinuous metal film sintered interconnect structure of claim 1, wherein the diameter of the smaller of said first size nano-metal particles and said second size nano-metal particles is 0.5nm < d <20 nm.
The preformed metal film pieces may be forged, sheared, or programmable laser cut to obtain a sequence of discrete structured film pieces of a particular shape.
Continuous means that in the traditional die bonding process, a whole piece of die bonding material metal film is often fixed at the bottom of a chip; the discontinuous mode means that the metal film at the bottom of the chip is not a complete piece, but a plurality of small metal film structures which are arranged at certain intervals according to a certain arrangement. The discontinuous metal film sintering interconnection structure is characterized in that the sizes of the N metal film small pieces are the same; or both are different; or a combination of multiple metal films of the same and different sizes.
The discontinuous metal film sintering interconnection structure is characterized in that the positions of the N metal film small pieces are arranged according to a N x N square matrix (shown in figure 1); the size of the N metal film chips is set according to [ (1/N) -k ] which is the area of the bottom surface of the chip, k is the designed chip spacing, and k ranges from 10 mu m to 2 mm.
The correlation performance of the nano metal film obtained by the invention and the prior art is compared as follows:
TABLE 1
Figure GDA0003138656880000061
Figure GDA0003138656880000071
Example two
The present embodiment provides a chip substrate connection structure and method using a single-layer nano metal film, as shown in fig. 2.
The single-layer structure can contain first-size nano metal particles and second-size nano metal particles mixed together;
the mixing mode comprises the following steps: 1) directly preparing a mixed solution; 2) preparing solution, paste and film of large-size particles, and driving the solution, paste and film into small-size particles by a physical impact method;
the nano metal particle material is copper.
The nano metal particle material is gold, palladium, silver, copper, aluminum, silver palladium alloy, gold palladium alloy, copper silver nickel alloy or copper aluminum alloy.
The diameter of the larger nano metal particle in the first-size nano metal particles and the second-size nano metal particles is 1nm < D <10 mu m. The discontinuous metal film sintered interconnect structure of claim 1, wherein the diameter of the smaller of said first size nano-metal particles and said second size nano-metal particles is 0.5nm < d <20 nm.
The preparation method comprises the following steps:
step 1: preparing a single-layer metal film;
step 2: cutting the metal film to obtain N metal film small pieces;
and step 3: pasting the metal film to the bottom of the chip to be interconnected, wherein 3x3 chips are arranged as an example as shown in FIG. 2;
and 4, step 4: heating the chip pasted with the metal film to obtain a chip pasted with the metal film;
and 5: the substrate and the metal film chip are interconnected.
The method for sintering interconnection by using single-layer discontinuous metal film is characterized in that the step 1 comprises the following steps:
step 1.1: preparing a mixed solution of nano metal particles with a first size and nano metal with a second size to prepare a metal paste;
step 1.2: placing the metal paste on a support substrate, and drying the support substrate to form a metal film;
the method is characterized in that the step 5 comprises the following steps:
step 5.1: the support substrate is peeled off.
Step 5.2: placing the multilayer metal film chip on a substrate;
step 5.3: the multilayer metal film chip is heated in a sintering furnace, and the substrate and the multilayer metal film chip are interconnected with the pressure assistance.
The specific parameters are as follows:
using a 10mmx10mmIGBT dummy chip, a 50mmx50mm alumina DBC substrate, a single layer of large and small sized nano-copper particles mixed with metal film a, the small sized copper particles having an average longest dimension from 0.5nm < D <20nm, the large sized nano-copper particles having an average longest dimension from 1nm < D <10 um;
firstly, cutting a single-layer copper film into a plurality of 2.5mmx2.5mm small pieces;
secondly, adhering the single-layer metal small-piece metal film to the bottom of the chip to be interconnected; the arrangement mode is three rows and three columns, the distance between every two small metal film pieces is set to be 1mm, and the outermost metal film and the edge of the chip are 0.5 mm;
thirdly, stripping the supporting base material; optionally preheating the chip and the copper film system for 10min at 100-130 ℃;
fourthly, the chip/copper film system is arranged on the substrate;
fifthly, sintering the system in a sintering furnace at 200-280 ℃ for 10 minutes optionally, so that the substrate and the chip are interconnected.
The test result shows that the porosity of the chip and the substrate system which are interconnected by the discontinuous copper film is less than 25 percent after sintering, the gas is effectively discharged, the thermal conductivity is more than 100(W/mK), and the shear stress is more than 10 MPa. In at least some of the test results, the shear stress was still greater than 8MPa after 1000 thermal cycles at a temperature of-40 to 150 ℃.
EXAMPLE III
The present embodiment provides a chip substrate connection structure and method using a multi-layered nano metal film, as shown in fig. 3.
The multilayer discontinuous metal film comprises
A first organic medium material layer, a second organic medium material layer,
a second organic medium material layer;
the first organic medium material layer contains first-size nano-metal particles,
the first organic medium material layer comprises second-size nano metal particles;
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
Preferably, the nano-metal particle material is copper.
Preferably, the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver-nickel alloy or copper-aluminum alloy.
The preparation method comprises the following steps
Step 1: preparing a multilayer metal film;
step 2: cutting the metal film to obtain N metal film small pieces;
and step 3: pasting the metal film to the bottom of the chip to be interconnected, as shown in FIG. 3, arranging the small pieces of 3x3 as an example;
and 4, step 4: heating the chip pasted with the metal film to obtain a chip pasted with the metal film;
and 5: the substrate and the metal film chip are interconnected.
The method is characterized in that the step 5 comprises the following steps:
step 5.1: the support substrate is peeled off.
Step 5.2: placing the multilayer metal film chip on a substrate;
step 5.3: the multilayer metal film chip is heated in a sintering furnace, and the substrate and the multilayer metal film chip are interconnected with the pressure assistance.
The specific parameters are as follows:
the method comprises the following steps of using a 10mmx10mmIGBT dummy chip, a 50mmx50mm aluminum oxide DBC substrate, 3 layers of copper films, wherein a small-size copper particle film B is arranged in the middle, small-size copper particles have the average longest dimension of which the D is more than 0.5nm and less than 20nm, a large-size copper particle film C is clamped at the upper end and the lower end, and large-size nano copper particles have the average longest dimension of which the D is more than 1nm and less than 10 um;
firstly, cutting a plurality of 2.5mmx2.5mm small pieces from the multilayer copper film;
secondly, sticking the small metal film to the bottom of the chip to be interconnected; the arrangement mode is three rows and three columns, the distance between every two small metal film pieces is set to be 1mm, and the outermost metal film and the edge of the chip are 0.5 mm;
thirdly, stripping the supporting base material; optionally preheating the chip and the copper film system for 20min at 100-130 ℃;
fourthly, the chip/copper film system is arranged on the substrate;
fifthly, sintering the system in a sintering furnace at 200-280 ℃ for 20 minutes optionally, so that the substrate and the chip are interconnected.
Test results show that the porosity after sintering is further improved to be less than 20% by utilizing the chip and the substrate system which are interconnected by the discontinuous copper film.
Example four
The present embodiment provides a chip substrate connection structure and method using a periodic multilayer nanometal film, as shown in fig. 4.
The multilayer discontinuous metal film comprising:
a first organic medium material layer, a second organic medium material layer,
a second organic medium material layer;
the first organic medium material layer contains first-size nano-metal particles,
the first organic medium material layer comprises second-size nano metal particles;
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
The first material layer and the second material layer have different length, width and height dimensions
Preferably, the nano-metal particle material is copper.
Preferably, the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver-nickel alloy or copper-aluminum alloy.
The method for sintering interconnection by utilizing the multilayer discontinuous metal film specifically comprises the following steps:
step 1: preparing a multilayer metal film A and a multilayer metal film B;
step 2: cutting the metal film to obtain N metal film small pieces b (as the number 10 in FIG. 4);
and step 3: pasting the metal film A to the bottom of the chip to be interconnected, and drying;
and 4, step 4: the N small metal film pieces b are arranged according to the design and are adhered to the bottom of the metal film A, and the metal film A is dried;
and 5: pasting another metal film A to the bottoms of the n metal film small pieces b, and drying;
step 6: heating the chip pasted with the metal film to obtain a chip pasted with the metal film;
and 7: the substrate and the metal film chip are interconnected.
The specific parameters are as follows:
using a 10mmx10mmIGBT dummy chip, a small-size copper particle film B, the small-size copper particles having an average longest dimension from 0.5nm < D <20nm, a large-size copper particle film C, the large-size nano copper particles having an average longest dimension from 1nm < D <10 um;
firstly, cutting a single-layer copper film B into a plurality of 2.5mmx2.5mm small pieces; cutting out 2 pieces of 10mmx10mm large copper film C;
secondly, sticking the large piece cut out from the copper film C to the bottom of the chip to be interconnected;
thirdly, sticking the small pieces cut out from the copper film B to the bottom of the large copper film in an arrangement mode of three rows and three columns, setting the distance between every two small metal film pieces to be 1mm, and setting the distance between the outermost metal film and the edge of the large copper film to be 0.5 mm;
fourthly, pasting the large piece with the other copper film C cut off to the bottom surface of the small piece, and aligning the large piece with the first large piece;
fifthly, preheating the chip and the copper film system for 20min at 100-130 ℃ optionally;
test results show that the porosity is improved to be less than 20% after sintering by using the chip and the substrate system which are interconnected by the discontinuous copper film, and gas is effectively discharged.
The metal film chip of the invention has the following advantages:
1) the invention provides a discontinuous nano metal sintering film for chip die bonding and a method thereof.A conventional continuous metal film is arranged into a plurality of discontinuous small pieces and arranged between a chip and a substrate according to a preset design, and small piece gaps left by discrete arrangement can be used as a channel for discharging gas during sintering, so that the compactness after sintering is improved, and the thermal conductivity of an interconnection layer is improved; meanwhile, as the sintering proceeds, the metal film pieces deform in the x and y directions due to the restriction in the z direction, and contact each other to form a dense sintered layer. Compared with the single large metal film, the discontinuous multi-metal film small-piece structure adopted by the invention can effectively reduce the inclination problem in the chip die bonding process according to the single-layer or multi-layer design of certain arrangement, so that the structure and the process are also suitable for interconnecting larger-size power chips in the future.
2) The preparation and subsequent stable retention of nano metal particles with the particle size of less than 20nm, even less than 1nm, of nano metal particles prepared by a chemical method in the packaging field are difficult to realize, and although the operation and the environment are strictly controlled, the technical problems of poor distribution and concentration and large dispersion degree still exist in the particle size range prepared in the same batch, so that the performance of the metal film after sintering is influenced to different degrees. The metal particle size design adopted by the invention achieves the effects of improving the compactness of the metal layer and reducing the porosity after sintering, which cannot be achieved by the combination of nano metal particles with other diameter sizes.
3) In order to avoid the problems of high cost of the original silver film, thermal mismatch with a Si or SiC-based chip, high electric mobility and the like, the nano-copper is preferably used for replacing a nano-silver material, so that the material and processing cost of interconnection packaging is effectively reduced. The nano copper film for sintering, which is prepared from the nano copper powder and the paste, has the characteristics of excellent characteristics of a copper material, portability, formability and the like of a metal sintering film, and is a preferred scheme for next-generation electrical interconnection.
The discontinuous nano metal sintering film for die bonding of the chip and the method thereof solve the problems of high porosity, low thermal conductivity and chip inclination of the original metal sintering film, are beneficial to improving the compactness after sintering, improve the thermal conductivity of the interconnection layer and are a preferred scheme for next-generation electrical interconnection.
Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, substitutions and the like can be made in form and detail without departing from the scope and spirit of the invention as disclosed in the accompanying claims, all of which are intended to fall within the scope of the claims, and that various steps in the various sections and methods of the claimed product can be combined together in any combination. Therefore, the description of the embodiments disclosed in the present invention is not intended to limit the scope of the present invention, but to describe the present invention. Accordingly, the scope of the present invention is not limited by the above embodiments, but is defined by the claims or their equivalents.

Claims (12)

1. A chip interconnect structure, comprising:
the chip is provided with a plurality of chips,
n nano metal film small pieces, N is more than or equal to 2,
a substrate, a first electrode and a second electrode,
the nano-metal film chip comprises first-size nano-metal particles and second-size nano-metal particles,
the first size nano-metallic particles are of a different diameter than the second size nano-metallic particles; the nano metal film small pieces are positioned between the chip and the substrate and arranged at intervals; multiple layers of nano metal film small pieces are arranged between the chip and the substrate; each layer of the multilayer nano metal film small piece is formed by arranging a plurality of discrete nano metal film small pieces at intervals, and the multilayer nano metal small piece comprises an organic medium material layer.
2. The chip interconnect structure of claim 1, wherein said nano-metallic particle material is copper.
3. The chip interconnect structure of claim 1, wherein the nano-metal particle material is gold, palladium, silver, copper, aluminum, silver palladium alloy, gold palladium alloy, copper silver nickel alloy, or copper aluminum alloy.
4. The chip interconnect structure of claim 1, wherein the diameter of the larger of the first-sized nano-metal particles and the second-sized nano-metal particles is 1nm < D <10 μm; the diameter of the metal nanoparticles with smaller size in the first size metal nanoparticles and the second size metal nanoparticles is 0.5nm < d <20 nm.
5. The chip interconnect structure of claim 1, wherein said nanometal film platelet comprises:
a first organic medium material layer, a second organic medium material layer,
a second organic medium material layer;
the first organic medium material layer contains first-size nano-metal particles,
the first organic medium material layer comprises second-size nano metal particles;
the first-sized nano-metallic particles are of a different diameter than the second-sized nano-metallic particles.
6. The chip interconnect structure of claim 1, wherein said nano-metal film platelets are distributed in the following manner:
a first metal film layer comprising a length A31Width of one, B31Nano-sized metal film flakes arranged, N1＝A31*B31；
A second metal film layer comprising a length A32Width of one, B32Nano-sized metal film flakes arranged, N2＝A32*B32；
……
An nth metal film layer including a length A3nWidth of one, B3nNano-sized metal film flakes arranged, Nn＝A3n*B3n；
N＝N1+N2+…+Nn。
7. A chip interconnection structure connection method is characterized by comprising the following steps:
step 1: preparing a nano metal film, wherein the nano metal film comprises first-size nano metal particles and second-size nano metal particles, and the diameters of the first-size nano metal particles and the second-size nano metal particles are different;
step 2: cutting the nano metal film to obtain N nano metal film chips, wherein N is more than or equal to 2;
and step 3: attaching one surface of the nano metal film chip to the bottom of the chip;
and 4, step 4: attaching the other side of the substrate and the other side of the nano metal film chip;
step 5, interconnecting the chip and the substrate;
the nano metal film small pieces are positioned between the chip and the substrate and arranged at intervals; multiple layers of nano metal film small pieces are arranged between the chip and the substrate; each layer of the multilayer nano metal film small piece is formed by arranging a plurality of discrete nano metal film small pieces at intervals, and the multilayer nano metal small piece comprises an organic medium material layer.
8. The method of claim 7, wherein the nano-metal particle material is copper.
9. The method for connecting chip interconnection structures according to claim 7, wherein the nano-metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver-nickel alloy, or copper-aluminum alloy.
10. The method for connecting chip interconnection structures according to claim 7, wherein the diameter of the larger-sized nano-metal particles of the first-sized nano-metal particles and the second-sized nano-metal particles is 1nm < D <10 μm; the diameter of the metal nanoparticles with smaller size in the first size metal nanoparticles and the second size metal nanoparticles is 0.5nm < d <20 nm.
11. The chip interconnect structure connection method according to claim 7,
the distribution mode of the nano metal film flakes comprises the following steps:
will be long by A31Width of one, B31N in total1Arranging and sticking the nano metal film chips to the bottom of the chip according to a design, and then drying to obtain a first metal film layer;
will be long by A32Width of one, B32N in total2The nano metal film chips are arranged according to the design and adhered to the bottom of the first metal film layer, and then drying treatment is carried out to obtain a second metal film layer;
……
will be long by A3nWidth of one, B3nN in totalnAnd (3) arranging and sticking the nano metal film chips to the bottom of the n-1 metal film layer according to the design, and then drying to obtain the n metal film layer.
12. The method for connecting a chip interconnection structure according to claim 7, wherein the steps 3 and 4 further comprise a drying process.
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