CN110071050A - A kind of chip interconnection structure and preparation method thereof - Google Patents

A kind of chip interconnection structure and preparation method thereof Download PDF

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Publication number
CN110071050A
CN110071050A CN201910331322.7A CN201910331322A CN110071050A CN 110071050 A CN110071050 A CN 110071050A CN 201910331322 A CN201910331322 A CN 201910331322A CN 110071050 A CN110071050 A CN 110071050A
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Prior art keywords
metal
small pieces
chip
nano
nanoporous
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CN201910331322.7A
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CN110071050B (en
Inventor
刘旭
叶怀宇
张卫红
敖日格力
李俊
韩非
张国旗
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Southwest University of Science and Technology
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Shenzhen Third Generation Semiconductor Research Institute
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Priority to PCT/CN2019/123823 priority patent/WO2020215738A1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/05—Metallic powder characterised by the size or surface area of the particles
    • B22F1/052—Metallic powder characterised by the size or surface area of the particles characterised by a mixture of particles of different sizes or by the particle size distribution
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/05—Metallic powder characterised by the size or surface area of the particles
    • B22F1/054—Nanosized particles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F3/00—Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sintering; Apparatus specially adapted therefor ; Presses and furnaces
    • B22F3/10—Sintering only
    • B22F3/11—Making porous workpieces or articles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
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Abstract

The present invention provides a kind of chip interconnection structure and preparation method thereof, structure includes: chip, N number of nanoporous metal membrane small pieces, N >=2, substrate, the nanoporous metal membrane small pieces include first size nano metal and the second sized nanostructures metallic particles, and the first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.It solves the problems, such as original metal sintering film high porosity, lower thermal conductivity, chip inclination, is conducive to the raising of compactness after sintering, improves the thermal conductivity of interconnection layer.

Description

A kind of chip interconnection structure and preparation method thereof
Technical field
The present invention relates to chip packages to interconnect field, relates more specifically to the technology of preparing of sintering metal film.
Background technique
In power semiconductor package field, seek that low temperature process, high-temperature service, thermal expansion coefficient match, high thermal conductivity is led Electricity, inexpensive interconnection material become present urgent problem.Exist with the traditional material technique of welding and wire bonding The insurmountable problems such as fusing point low and high temperature creep failure, wire wound, parasitic parameter, novel interconnection material just from welding to Sintering technology development.By reducing the size of sintered particles, sintering temperature is reduced, nano-metal particle sintering technology has become Most promising technology in the novel interconnection material of power semiconductor.
The master of power semiconductor device package interconnection has been increasingly becoming with the advanced technologies that nano silver is sintered to representative at present Stream, domestic and international predominant package application vendor have entered in practical and scale use.However nano silver sintering patent, material, Processes and apparatus is mainly controlled by foreign vendor, and development at home is by larger limitation.Nano silver sintering technology is also deposited simultaneously In deficiency: 1) ag material price itself is higher, restricted from being widely used.2) silver and SiC chip back material heat expansion The difference of coefficient needs to add other intermediate metal layers and improves interconnection performance, to increase process complexity and cost.3) silver-colored There are ELECTROMIGRATION PHENOMENONs for layer, are unfavorable for power device and apply reliably and with long-term.It can be low with the approximate nano copper particle of nano silver It is melted under the conditions of temperature, fusing point can construct stable metal interconnecting layer close to copper simple substance material (1083 DEG C) after sintering.Its one pack system The characteristic of metal, avoids the service reliability problem under alloy material heat cycle effect, realizes the bonding of copper copper, solve chip and Between substrate the problem of matched coefficients of thermal expansion, while ELECTROMIGRATION PHENOMENON being avoided to lead to integrity problem.Compare nano-Ag particles, The material and processing cost of interconnection package is effectively reduced.It can be more importantly pushed further into from chip package application field The practical application and industrialization of " Quan Tonghua " (All copper) theory, push the innovation and development of semiconductor industry.
The prior art one is the patent document of Publication No. CN103262172A, discloses a kind of agglomerated material and sintering material Expect the thin layer of preparation and the adherence method of the material.Thin layer is made of metal powder, soldering paste, adhesive and solvent.Wherein Metal powder includes gold, palladium, silver, copper, aluminium, silver palladium alloy or rhotanium, can further comprise one or more of functions Property additive.Metal powder includes nano particle.Metal powder is applied on substrate, and shape is dried to the material on substrate Straticulation.The shortcomings that substrate material includes polyester fiber, the prior art is nano metal composition of layer, size list on substrate One, porosity is larger after thereby resulting in sintering, the consequences such as conductive and heat conductive effect difference.
The prior art two is Publication No. CN105492198A patent document, is disclosed a kind of for electric component and machinery The compound and multilayer silverskin of component, wherein joined enhancing particle or fiber, in sinterable silver layer to improve its intensity.Into one Step is outer on the Argent grain layer that can slightly solve to have added enhancing metal foil layer, ingredient can be silver, copper, gold or any other metal or Any alloy is also possible to metal-containing polymer or ceramic foil, can also be compound or the plating with different metal and alloy-layer Layer structure.Enhancing metal foil layer can be applied in the form of solid, perforation or grid etc..However the problem of the prior art, is this Multilayer composite metal film, the addition for enhancing metal foil layer, increase the interface number of articulamentum after sintering, so as to reduce connection Intensity；In addition, the Argent grain layer of single size, porosity is very big after sintering, can reduce thermal conductivity, conductivity and shearing and answer Power, to reduce reliability.
The prior art three is the Chinese patent application that patent publication No. is CN106660120A, and it discloses a kind of discrete Agglomerated material and the fixing means for using it.Material includes metal powder and substrate, and metal powder includes the nanometer of shell structure Grain, substrate includes polymer.By printing or pouring metal powder film on polymeric substrate, and make the material using ad hoc approach Material forms the array of discrete shape.The disadvantages of this method is on the one hand to use large stretch of sintering metal film, in sintering process, The gas that middle position generates does not have effective channel to exclude, and interconnects the problems such as layer porosity is big after thus may cause sintering； It directly uses printing or pours mode and prepare the design that discrete shape may cause the shape dependence printing screen of discrete small pieces, become Change shape difficulty；The problems such as also resulting in edge roughness, uneven thickness, low resolution simultaneously.
Summary of the invention
In order to overcome the deficiencies of the prior art, avoid original metal sintering film film high porosity, lower thermal conductivity, chip inclined Problem, the present invention provides a kind of chip interconnection structures, comprising:
Chip,
N number of nanoporous metal membrane small pieces, N >=2,
Substrate,
The nanoporous metal membrane small pieces include first size nano metal and the second sized nanostructures metallic particles,
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
Preferably, the nano-metal particle material is copper.
Preferably, the nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil Gold, copper silver-nickel or albronze.
Preferably, in the first size nano-metal particle and the second sized nanostructures metallic particles, larger size Nano-metal particle diameter be 1nm < D < 10 μm；The first size nano-metal particle and the second sized nanostructures metal In particle, the nano-metal particle diameter of smaller size is 0.5nm < d < 20nm.
Preferably, the nanoporous metal membrane small pieces are between chip and substrate, the row of interval between nanoporous metal membrane small pieces Column；The different layers of one or more layers nanoporous metal membrane small pieces and multi-layer nano metal film small pieces are arranged between chip and substrate Between have continuous nanoporous metal membrane.
Preferably, N number of single layer nano metal small pieces are according to long A1It is a, wide B1A arrangement, N=A1*B1。
Preferably, N number of multi-layer nano splint is according to long A2It is a, wide B2A arrangement, N=A2*B2。
Preferably, the multi-layer nano splint includes:
First organic dielectric material layer,
Second organic dielectric material layer；
It include first size nano-metal particle in the first organic dielectric material layer,
It include the second sized nanostructures metallic particles in the first organic dielectric material layer；
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
Preferably, the nanoporous metal membrane small pieces distribution mode of the multilayer are as follows:
First metallic diaphragm, first metallic diaphragm include long A31It is a, wide B31The single layer nanoporous metal membrane of a arrangement is small Piece or multi-layer nano metal film small pieces, N1=A31*B31；
Second metallic diaphragm, second metallic diaphragm include long A32It is a, wide B32The single layer nanoporous metal membrane of a arrangement is small Piece or multi-layer nano metal film small pieces, N2=A32*B32；
……
N-th metallic diaphragm, n-th metallic diaphragm include long A3nIt is a, wide B3nThe single layer nanoporous metal membrane small pieces of a arrangement Or multi-layer nano metal film small pieces, Nn=A3n*B3n；
N=N1+N2+…+Nn。
A kind of chip interconnection structure connection method, comprising:
Step 1: preparing nanoporous metal membrane, the nanoporous metal membrane includes that first size nano metal and the second size are received Rice metallic particles, the first size nano-metal particle are different from the second sized nanostructures metallic particles diameter；
Step 2: cutting the nanoporous metal membrane, obtain N number of nanoporous metal membrane small pieces；
Step 3: the nanoporous metal membrane small pieces one side and chip bottom are bonded；
Step 4: the another side of substrate and nanoporous metal membrane small pieces is bonded；
Step 5: chip and substrate are interconnected.
Preferably, the nano-metal particle material is copper.
Preferably, the nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil Gold, copper silver-nickel or albronze.
Preferably, in the first size nano-metal particle and the second sized nanostructures metallic particles, larger size Nano-metal particle diameter be 1nm < D < 10 μm；The first size nano-metal particle and the second sized nanostructures metal In particle, the nano-metal particle diameter of smaller size is 0.5nm < d < 20nm.
Preferably, the nanoporous metal membrane small pieces are between chip and substrate, the row of interval between nanoporous metal membrane small pieces Column；The different layers of one or more layers nanoporous metal membrane small pieces and multi-layer nano metal film small pieces are arranged between chip and substrate Between have continuous nanoporous metal membrane.
Preferably, described one layer of nanoporous metal membrane small pieces distribution mode includes:
By the nanoporous metal membrane small pieces according to long A, wide B are labelled to chip bottom.
Preferably, the nanoporous metal membrane small pieces distribution mode of the multilayer includes:
By the long A31It is a, wide B31A total N1A metal film small pieces are pasted according to design arrangement to the chip bottom, so After be dried, obtain the first metallic diaphragm；
By the long A32It is a, wide B32A total N2A metal film small pieces are pasted according to design arrangement to first metallic diaphragm Then bottom is dried, obtain the second metallic diaphragm；
……
By the long A3nIt is a, wide B3nA total NnA metal film small pieces are pasted according to design arrangement to (n-1)th metal film Layer bottom, is then dried, and obtains the n-th metallic diaphragm.
Preferably, the step 3, step 4 further include being dried.
Preferably, the step 4 further include:
Step 5.1: removing supporting base material；
Step 5.2: the chip for posting metal multilayer film is placed on substrate；
Step 5.3: multiple layer metal membrane DNA chip being heated in sintering furnace, selection has no pressure auxiliary, interconnection substrates With multiple layer metal membrane DNA chip.
Metal film is set as multiple discontinuous small pieces and is placed between chip and substrate according to arrangement is pre-designed, discrete row The small pieces gap that cloth reserves can be used as the channel of the gas discharge in sintering, be conducive to the raising of compactness after sintering, thus Promote the thermal conductivity of interconnection layer；Meanwhile as sintering carries out, metal film small pieces can generate the direction x, y due to the limitation in the direction z Deformation, and contact with each other, chip die bond can be effectively reduced by forming dense sintering layer compared to the big metal film of monolithic is used Tilt problem in the process.
Detailed description of the invention
Fig. 1 is the discontinuous Nanometer Copper sintered membrane schematic diagram that the embodiment of the present invention one provides.
Fig. 2 is the structural approach schematic diagram using the discrete metal film sintering interconnection of single layer that embodiment two provides.
Fig. 3 is the structural approach schematic diagram using the discrete metal film sintering interconnection of multilayer that embodiment three provides.
Fig. 4 is that the structural approach using the periodically discrete metal film sintering interconnection of multilayer that example IV provides is illustrated Figure.
The plating nanocrystalline Cu film (before sintering) 1 of discrete arrangement, chip (in order to facilitate observation of, being set as see-through) 2, substrate 3 is discrete Arrange plating nanocrystalline Cu film (in sintering) 4, complete interconnection layer (after sintering) 5, single layer composite Nano copper film small pieces 6, macro nanometer copper Particle 7, small size nano copper particle 8, first material layer 9, second material layer 10
Specific embodiment
The following detailed description of specific implementation of the invention, it is necessary to it is indicated herein to be, implement to be only intended to this hair below Bright further explanation, should not be understood as limiting the scope of the invention, and field person skilled in the art is according to above-mentioned Some nonessential modifications and adaptations that summary of the invention makes the present invention, still fall within protection scope of the present invention.
Embodiment one
The present embodiment provides a kind of chip substrate connection structures and method using nanoporous metal membrane, as shown in Figure 1, packet It includes:
Chip,
N number of and preformed metal film small pieces, N >=2, N=n^2, n is natural number, (such as N=4,9,16 ...)
Substrate,
The metal film includes organic carrier and nano-metal particle；
The metal film can be single layer structure, be also possible to multilayered structure；
It may include that first size nano metal and the second sized nanostructures metallic particles are blended in one in the single layer structure It rises；
The multilayered structure includes the layer of first size nano metal and the layer of the second sized nanostructures metallic particles,
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
The nano-metal particle material is copper.
The nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil, copper silver Nickel alloy or albronze.
In the first size nano-metal particle and the second sized nanostructures metallic particles, the nanogold of larger size Metal particles diameter is 1nm < D < 10 μm.The structure of discrete metal film sintering interconnection as described in claim 1, feature exist In, in the first size nano-metal particle and the second sized nanostructures metallic particles, the nano metal of smaller size Grain diameter is 0.5nm < d < 20nm.
The preformed metal film small pieces can obtain the discrete of specific shape by forging and stamping, shearing or programmable laser cutting Structural diaphragm sequence.
Continuously refer in traditional die bond technique, is often fixed on chip bottom with whole piece die bond material metal film；It is non- Continuously refer to, complete not a piece of in the metal film of chip bottom, multi-disc there are certain intervals, according to the little Jin centainly arranged Belong to membrane structure.The structure of discrete metal film sintering interconnection, which is characterized in that the ruler of N number of metal film small pieces It is very little all the same；Or it is different；Or the combination of identical and different size metal multilayer films.
The structure of discrete metal film sintering interconnection, which is characterized in that the position of N number of metal film small pieces (as shown in Figure 1) is arranged according to the square matrix of n × n；The size of N number of metal film small pieces is according to [(1/ for die bottom surface area N)-k] setting, k is the small pieces spacing of design, and the range of k is at 10 μm to 2mm.
The correlated performance comparison for the nanoporous metal membrane that the present invention and the prior art obtain is as follows:
Table 1
Embodiment two
The present embodiment provides a kind of chip substrate connection structures and method using single layer nanoporous metal membrane, as shown in Figure 2.
It may include that first size nano metal and the second sized nanostructures metallic particles are blended in one in the single layer structure It rises；
Hybrid mode includes: 1) directly to configure mixed solution；2) solution and lotion, film of large-size particle, physics are prepared Ballistic method squeezes into small sized particles；
The nano-metal particle material is copper.
The nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil, copper silver Nickel alloy or albronze.
In the first size nano-metal particle and the second sized nanostructures metallic particles, the nanogold of larger size Metal particles diameter is 1nm < D < 10 μm.The structure of discrete metal film sintering interconnection as described in claim 1, feature exist In, in the first size nano-metal particle and the second sized nanostructures metallic particles, the nano metal of smaller size Grain diameter is 0.5nm < d < 20nm.
Preparation step includes:
Step 1: preparing single-layer metal film；
Step 2: cutting out the metal film, obtain N number of metal film small pieces；
Step 3: the metal film being affixed to interconnection die bottom, as shown in Fig. 2, for the small pieces arrangement of 3x3；
Step 4: the chip for posting metal film being heated, the glutinous chip for having metal film is obtained；
Step 5: interconnection substrates and metal membrane DNA chip.
A kind of method using the discrete metal film sintering interconnection of single layer, which is characterized in that step 1 packet It includes:
Step 1.1: configuring the nano-metal particle and the second sized nanostructures metal mixed solution with first size, preparation Metal paste；
Step 1.2: the metal paste being placed in supporting base material, dry supporting base material forms metal film；
It is characterized in that, step 5 includes:
Step 5.1: removing supporting base material.
Step 5.2: the multiple layer metal membrane DNA chip is placed on substrate；
Step 5.3: multiple layer metal membrane DNA chip being heated in sintering furnace, selection has no pressure auxiliary, interconnection substrates With multiple layer metal membrane DNA chip.
Design parameter is as follows:
Use 10mmx10mmIGBT dummy chip, 50mmx50mm aluminium oxide DBC substrate, the size dimension nanometer of single layer Copper particle mixed metal film A, small size copper particle have from 0.5nm < d < 20nm average longest dimension, macro nanometer copper Grain has from 1nm < D < 10um average longest dimension；
One, that single layer copper film is cut out 2.5mmx2.5mm small pieces is several；
Two, the single-layer metal small pieces metal film is pasted to interconnection die bottom；Arrangement mode is three rows three column, gold Belong to the spacing two-by-two between film small pieces and is set as 1mm, outermost metal film and chip edge 0.5mm；
Three, supporting base material is removed；100~130 DEG C of preheating 10min are optionally carried out to chip and copper film system；
Four, the chip/copper film system is placed on substrate；
Five, 200~280 DEG C are optionally carried out to the system in sintering furnace to be sintered 10 minutes, so that substrate and chip shape At interconnection.
Test result shows that porosity is less than after burn-back using the chip and substrate system of the discontinuous copper film interconnection 25%, gas has obtained effective discharge, and thermal conductivity is greater than 100 (W/mK), and shear stress is greater than 10MPa.In at least some of test As a result in, under the conditions of -40 to 150 DEG C of temperature, after 1000 thermal cycles, 8MPa is still greater than in shear stress.
Embodiment three
The present embodiment provides a kind of chip substrate connection structures and method using multi-layer nano metal film, as shown in Figure 3.
The discrete metal film of multilayer, including
First organic dielectric material layer,
Second organic dielectric material layer；
It include first size nano-metal particle in the first organic dielectric material layer,
It include the second sized nanostructures metallic particles in the first organic dielectric material layer；
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
Preferably, the nano-metal particle material is copper.
Preferably, the nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil Gold, copper silver-nickel or albronze.
Preparation step includes
Step 1: preparing metal multilayer film；
Step 2: cutting out the metal film, obtain N number of metal film small pieces；
Step 3: the metal film being affixed to interconnection die bottom, as shown in figure 3, for the small pieces arrangement of 3x3；
Step 4: the chip for posting metal film being heated, the glutinous chip for having metal film is obtained；
Step 5: interconnection substrates and metal membrane DNA chip.
It is characterized in that, step 5 includes:
Step 5.1: removing supporting base material.
Step 5.2: the multiple layer metal membrane DNA chip is placed on substrate；
Step 5.3: multiple layer metal membrane DNA chip being heated in sintering furnace, selection has no pressure auxiliary, interconnection substrates With multiple layer metal membrane DNA chip.
Design parameter is as follows:
Use 10mmx10mmIGBT dummy chip, 50mmx50mm aluminium oxide DBC substrate, 3 layers of copper film, small size copper Granulosa B has in centre, small size copper particle from 0.5nm < d < 20nm average longest dimension, and large scale copper membrana granulosa C is clipped in Upper and lower ends, macro nanometer copper particle have from 1nm < D < 10um average longest dimension；
One, that multilayer copper film is cut out 2.5mmx2.5mm small pieces is several；
Two, the small pieces metal film is pasted to interconnection die bottom；Arrangement mode is three rows three column, metal film small pieces Between spacing two-by-two be set as 1mm, outermost metal film and chip edge 0.5mm；
Three, supporting base material is removed；100~130 DEG C of preheating 20min are optionally carried out to chip and copper film system；
Four, the chip/copper film system is placed on substrate；
Five, 200~280 DEG C are optionally carried out to the system in sintering furnace to be sintered 20 minutes, so that substrate and chip shape At interconnection.
Test result shows the chip and substrate system using the discontinuous copper film interconnection, and porosity is into one after burn-back Step is promoted to less than 20%.
Example IV
The present embodiment provides a kind of chip substrate connection structures and method using periodic multilayer nanoporous metal membrane, such as scheme Shown in 4.
The discrete metal film of multilayer, comprising:
First organic dielectric material layer,
Second organic dielectric material layer；
It include first size nano-metal particle in the first organic dielectric material layer,
It include the second sized nanostructures metallic particles in the first organic dielectric material layer；
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
The first material layer has different length, width and height sizes from second material layer
Preferably, the nano-metal particle material is copper.
Preferably, the nano-metal particle material is gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil Gold, copper silver-nickel or albronze.
Using the method for the discrete metal film sintering interconnection of multilayer, specifically includes the following steps:
Step 1: preparing metal multilayer film A, B；
Step 2: cutting out the metal film, obtain N number of metal film small pieces b (serial number 10 in such as Fig. 4)；
Step 3: the metal film A is affixed to interconnection die bottom, it is dry；
Step 4: N number of metal film small pieces b is pasted according to design arrangement to the bottom the metal film A, it is dry；
Step 5: another metal film A is pasted to the bottom the n metal film small pieces b, it is dry；
Step 6: the chip for posting metal film being heated, the glutinous chip for having metal film is obtained；
Step 7: interconnection substrates and metal membrane DNA chip.
Design parameter is as follows:
Using 10mmx10mmIGBT dummy chip, small size copper membrana granulosa B, small size copper particle has from 0.5nm < d The average longest dimension of < 20nm, large scale copper membrana granulosa C, macro nanometer copper particle have average most from 1nm < D < 10um Long size；
One, that single layer copper film B is cut out 2.5mmx2.5mm small pieces is several；It is 2 large stretch of that copper film C is cut out into 10mmx10mm；
Two, the copper film C sheet cut out is pasted to interconnection die bottom；
Three, the copper film B small pieces cut out are pasted into above-mentioned large stretch of copper film bottom, arrangement mode is three rows three column, gold Belong to the spacing two-by-two between film small pieces and is set as 1mm, outermost metal film and sheet edge 0.5mm；
Four, another piece of copper film C sheet cut off is pasted into above-mentioned small pieces bottom surface, is aligned with first piece of sheet；
Five, 100~130 DEG C of preheating 20min are optionally carried out to chip and copper film system；
Test result shows that porosity improves after burn-back using the chip and substrate system of the discontinuous copper film interconnection To less than 20%, gas has obtained effective discharge.
Metal film small pieces of the invention have following advantage:
1) provided by the present invention for the discontinuous nano metal sintered membrane and its method of chip die bond, by former continuous metal Film is arranged to multiple discontinuous small pieces and is placed between chip and substrate according to arrangement is pre-designed, and discrete arrangement reserves small Piece gap can be used as the channel of the gas discharge in sintering, is conducive to the raising of compactness after sintering, thus promotes interconnection layer Thermal conductivity；Meanwhile as sintering carries out, metal film small pieces can generate the deformation in the direction x, y, and phase due to the limitation in the direction z Mutually contact forms dense sintering layer.Compared to the big metal film of monolithic is used, discrete multi-disc metal film that the present invention uses is small Chip architecture can effectively reduce the tilt problem during chip die bond according to the design of the single layer or multilayer that centainly arrange, by This, the structure and technique are also applied for the following larger sized power chip of interconnection.
2) encapsulation field is difficult to realize 20nm or less even 1nm or less grain by nano-metal particle prepared by chemical method The nano-metal particle of diameter prepares and subsequent stable retention, although to operation and environment strict control, with batch preparation It is poor that particle size range still remains distribution centrality, the big technical problem of dispersion degree, this is by different degrees of influence metal film Performance after sintering.The design for the above-mentioned metal particle size that the present invention uses reaches promotes metal layer compactness, drop after sintering The effect of low porosity is that the nano-metal particle combination institute of other diameter dimensions is inaccessiable.
3) in order to avoid the high cost of original silverskin, with Si or SiC base chip thermal mismatching, high electromobility the problems such as, this hair Bright preferred use Nanometer Copper replaces nano silver material, so that the material and processing cost of interconnection package be effectively reduced.By nanometer Sintering plating nanocrystalline Cu film made of copper powder body, lotion, the good characteristic for having copper product simultaneously, be also provided simultaneously with metal sintering The features such as portability of film, formability, be next-generation electric interconnection preferred option.
Provided by the present invention for the discontinuous nano metal sintered membrane and its method of chip die bond, solves original metal The problem of sintered membrane high porosity, lower thermal conductivity, chip inclination, is conducive to the raising of compactness after sintering, improves interconnection layer Thermal conductivity, be next-generation electric interconnection preferred option.
Although for illustrative purposes, it has been described that exemplary embodiments of the present invention, those skilled in the art Member it will be understood that, can be in form and details in the case where the scope and spirit for not departing from invention disclosed in appended claims On the change that carry out various modifications, add and replace etc., and all these changes all should belong to appended claims of the present invention Protection scope, and each step in the claimed each department of product and method, can in any combination Form is combined.Therefore, to disclosed in this invention the description of embodiment be not intended to limit the scope of the invention, But for describing the present invention.Correspondingly, the scope of the present invention is not limited by embodiment of above, but by claim or Its equivalent is defined.

Claims (18)

1. a kind of chip interconnection structure characterized by comprising
Chip,
N number of nanoporous metal membrane small pieces, N >=2,
Substrate,
The nanoporous metal membrane small pieces include first size nano metal and the second sized nanostructures metallic particles,
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
2. utilizing the chip substrate connection structure of nanoporous metal membrane as described in claim 1, which is characterized in that the nano metal Granular materials is copper.
3. chip interconnection structure as described in claim 1, which is characterized in that the nano-metal particle material be gold, palladium, silver, Copper, aluminium, silver palladium alloy, rhotanium, Kufil, copper silver-nickel or albronze.
4. chip interconnection structure as described in claim 1, which is characterized in that the first size nano-metal particle and described the In two sized nanostructures metallic particles, the nano-metal particle diameter of larger size is 1nm < D < 10 μm；The first size nanometer In metallic particles and the second sized nanostructures metallic particles, the nano-metal particle diameter of smaller size be 0.5nm < d < 20nm。
5. chip interconnection structure as described in claim 1, which is characterized in that the nanoporous metal membrane small pieces are located at chip and substrate Between, it is alternatively arranged between nanoporous metal membrane small pieces；One or more layers nanoporous metal membrane small pieces is arranged between chip and substrate And there is continuous nanoporous metal membrane between the different layers of multi-layer nano metal film small pieces.
6. chip interconnection structure as claimed in claim 5, which is characterized in that N number of single layer nano metal small pieces are according to long A1 It is a, wide B1A arrangement, N=A1*B1。
7. chip interconnection structure as claimed in claim 5, which is characterized in that N number of multi-layer nano splint is according to long A2 It is a, wide B2A arrangement, N=A2*B2。
8. chip interconnection structure as claimed in claim 7, which is characterized in that the multi-layer nano splint includes:
First organic dielectric material layer,
Second organic dielectric material layer；
It include first size nano-metal particle in the first organic dielectric material layer,
It include the second sized nanostructures metallic particles in the first organic dielectric material layer；
The first size nano-metal particle is different from the second sized nanostructures metallic particles diameter.
9. chip interconnection structure as claimed in claim 5, which is characterized in that the nanoporous metal membrane small pieces distribution mode of the multilayer Are as follows:
First metallic diaphragm, first metallic diaphragm include long A31It is a, wide B31The single layer nanoporous metal membrane small pieces of a arrangement or Multi-layer nano metal film small pieces, N1=A31*B31；
Second metallic diaphragm, second metallic diaphragm include long A32It is a, wide B32The single layer nanoporous metal membrane small pieces of a arrangement or Multi-layer nano metal film small pieces, N2=A32*B32；
……
N-th metallic diaphragm, n-th metallic diaphragm include long A3nIt is a, wide B3nThe single layer nanoporous metal membrane small pieces or more of a arrangement Layer nanoporous metal membrane small pieces, Nn=A3n*B3n；
N=N1+N2+…+Nn。
10. a kind of chip interconnection structure connection method characterized by comprising
Step 1: preparing nanoporous metal membrane, the nanoporous metal membrane includes first size nano metal and the second sized nanostructures gold Metal particles, the first size nano-metal particle are different from the second sized nanostructures metallic particles diameter；
Step 2: cutting the nanoporous metal membrane, obtain N number of nanoporous metal membrane small pieces；
Step 3: the nanoporous metal membrane small pieces one side and chip bottom are bonded；
Step 4: the another side of substrate and nanoporous metal membrane small pieces is bonded；
Step 5: chip and substrate are interconnected.
11. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the nano-metal particle material is Copper.
12. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the nano-metal particle material is Gold, palladium, silver, copper, aluminium, silver palladium alloy, rhotanium, Kufil, copper silver-nickel or albronze.
13. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the first size nano metal For grain with the second sized nanostructures metallic particles, the nano-metal particle diameter of larger size is 1nm < D < 10 μm；Described In one sized nanostructures metallic particles and the second sized nanostructures metallic particles, the nano-metal particle diameter of smaller size is 0.5nm<d<20nm。
14. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the nanoporous metal membrane small pieces are located at Between chip and substrate, it is alternatively arranged between nanoporous metal membrane small pieces；One or more layers nanometer is arranged between chip and substrate There is continuous nanoporous metal membrane between the different layers of metal film small pieces and multi-layer nano metal film small pieces.
15. chip interconnection structure connection method as claimed in claim 14, which is characterized in that one layer of the nanoporous metal membrane is small Piece distribution mode includes:
By the nanoporous metal membrane small pieces according to long A, wide B are labelled to chip bottom.
16. chip interconnection structure connection method as claimed in claim 14, which is characterized in that
The nanoporous metal membrane small pieces distribution mode of the multilayer includes:
By the long A31It is a, wide B31A total N1A metal film small pieces are pasted according to design arrangement to the chip bottom, then into Row is dried, and obtains the first metallic diaphragm；
By the long A32It is a, wide B32A total N2A metal film small pieces are pasted according to design arrangement to first metallic diaphragm bottom Then portion is dried, obtain the second metallic diaphragm；
……
By the long A3nIt is a, wide B3nA total NnA metal film small pieces are pasted according to design arrangement to (n-1)th metallic diaphragm bottom Then portion is dried, obtain the n-th metallic diaphragm.
17. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the step 3, step 4 further include It is dried.
18. chip interconnection structure connection method as claimed in claim 10, which is characterized in that the step 5 further include:
Step 5.1: removing supporting base material；
Step 5.2: the chip for posting metal multilayer film is placed on substrate；
Step 5.3: multiple layer metal membrane DNA chip being heated in sintering furnace, selection has a no pressure auxiliary, interconnection substrates and more Layer metal membrane DNA chip.
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Cited By (5)

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