CN110048602B - DC-DC BOOST self-charging circuit - Google Patents

DC-DC BOOST self-charging circuit Download PDF

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Publication number
CN110048602B
CN110048602B CN201910349465.0A CN201910349465A CN110048602B CN 110048602 B CN110048602 B CN 110048602B CN 201910349465 A CN201910349465 A CN 201910349465A CN 110048602 B CN110048602 B CN 110048602B
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circuit
tube
voltage
output
boost
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CN201910349465.0A
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CN110048602A (en
Inventor
方建平
石鹏举
薛永强
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Tuoer Microelectronics Co ltd
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Tuoer Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a DC-DC BOOST self-charging circuit, which charges a BOOST capacitor before a high-side power tube is opened when a voltage is input, low voltage is input or the input is electrified slowly, so that the BOOST has enough voltage capacity, and the high-side power tube can be normally opened when a LOGIC signal for opening the high-side power tube is sent out by a LOGIC circuit; when the DC-DC is in a light load or no-load state, the main power loss of the chip is the switching loss of the power tube, and when the DC-DC is in the light load or no-load mode, the inside of the chip enters a light load high-efficiency mode, and the high-side power tube and the low-side power tube are not conducted in each period, so that the switching loss is greatly reduced, and the efficiency of the chip in light load or no-load is effectively improved.

Description

DC-DC BOOST self-charging circuit
Technical Field
The invention relates to the field of power management, in particular to a self-charging circuit.
Background
The direct current-direct current conversion chip (DC-DC converter chip) has the advantages of high integration, high driving, high efficiency and the like, the DC-DC converter chip is a very important functional module in the power management chip, and along with the wide application of portable electronic products, higher requirements are also put forward on the performance of DC-DC: higher integration, higher efficiency, better transient response, etc.
The DC-DC converter chip can be divided into low-voltage, medium-voltage and high-voltage DC-DC according to input voltage, and in the non-low-voltage DC-DC, a design method of double N tubes is generally adopted for the power tube, namely N-type MOSFETs are adopted for the high-side power tube and the low-side power tube. When the high-side MOSFET is turned on, the source voltage is ideally close to the input supply voltage, so the gate voltage of the high-side MOSFET must be greater than the supply voltage to turn on, and the voltage between the gate and source of the MOSFET should be designed to be large enough for faster turn-on speed and higher efficiency, and in medium-high voltage applications, the gate-source voltage of the MOSFET is typically designed to be around 5V or higher. However, under the conditions of high output voltage and no load output, i.e., when the output voltage is 5V or higher, the DC-DC chip may have a phenomenon that the output cannot be established, i.e., the output voltage eventually cannot reach the set value.
It has been found that the BOOST voltage is a fixed voltage inside the DC-DC to charge the capacitor connected between BOOST and SW through a diode, and the main reason for this is that during slow power-up or low voltage input, the BOOST voltage cannot be charged due to the close proximity of the input and output voltages during the start-up phase, so the gate-source voltage of the DC-DC high-side MOSFET is too low to turn on the upper tube, and therefore the output energy cannot be replenished, and the output will remain at some fixed but less than normal set point when idling.
For this purpose researchers have designed a BOOST self-charging circuit, i.e. the low-side MOSFET of the DC-DC converter is forced to turn on with a fixed duty cycle at each switching cycle of the DC-DC converter, when the low-side MOSFET is turned on, the voltage of SW is zero, the BOOST voltage is less than the internal supply voltage, during which time the internal supply will charge the BOOST capacitor through the diode. The method can well solve the problem that the output cannot be started when the low-voltage input or the low-voltage power-on is performed, but the low-side MOSFET is conducted according to a fixed duty ratio in each period, so that the DC-DC efficiency is extremely poor when the low-voltage power-on is in no-load or light-load.
Disclosure of Invention
The invention provides a DC-DC BOOST self-charging circuit, which aims to overcome the defects of the prior art and solve the problems that low-voltage input, output cannot be started during slow power-on and no-load light-load efficiency is poor. The circuit can charge the BOOST in time when high voltage is output, low voltage is input or low voltage is input and is electrified slowly, and the circuit can not forcedly open the lower pipe in each period when in light load or no load, so that energy loss can not exist in each period, and the efficiency of DC-DC in no load or light load is greatly improved.
The technical scheme adopted for solving the technical problems is as follows:
a DC-DC BOOST self-charging circuit comprises a sampling resistor Rs, a high-side N-type power tube N H Low side N-type power tube N L And Nc, internal power supply and reference circuit, BOOST charge diode D1, error amplifier EA, current sampling circuit, waveform generator, PWM modulation comparator circuit, RS latch circuit, digital logic operation circuit, level conversion circuit, N H Tube driving circuit, N L A tube driving circuit, nc tube driving circuit;
one end of the sampling resistor Rs is connected to the input V IN The other end of the sampling resistor Rs is connected to N H The drain end CSN, rs of the tube flows through N by sampling H The current of the tube, the current is converted into the sampling voltage;
the N-type power tube N H Is composed of N H Output drive of tube drive circuit, N-type power tube N H Is connected with the SW end of the chip, when N H When conducting, the current is input V IN Flows to SW when N H When turned off, V IN The current path to SW is blocked;
the N-type power tube N L And Nc, N L The grid electrode is composed of N L Output drive of tube driving circuit, N L The source electrode is connected with the GND end of the chip, N L The drain terminal is connected with the SW end of the chip, the Nc grid is driven by the output of the Nc tube driving circuit, the Nc source electrode is connected with the GND end of the chip, the Nc drain terminal is connected with the SW end of the chip, and when N is L When Nc is conducted, the inductor current is freewheeled, when N L When Nc is turned off, the signal passes through N L Parasitic diodes of Nc carry out follow current on the inductance current;
the internal power supply and the reference circuit are used for carrying out coarse adjustment on input voltage to respectively generate three paths of internal power supplies VR1, VR2 and VR3 and an internal reference voltage VREF;
the anode of the BOOST charging diode D1 is connected with the internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the power supply is connected with the power supply at the N H When the tube is conducted, VR3 charges the BOOST capacitor through D1;
the error amplifier EA is connected with an internal reference voltage VREF at the positive input end and an external feedback voltage VFB at the negative input end, amplifies the voltage difference between VREF and VFB and outputs an error amplification voltage V_COMP;
the current sampling circuit COMP_IS IS connected with the input voltage VIN at the positive input end and the CSN node at the negative input end, and amplifies the sampling voltage on the sampling resistor Rs to output the voltage V_IS;
the waveform generator generates a row of square waves CLK and a row of sawtooth waves V_SLOPE when the circuit works normally;
the PWM modulation comparator circuit PWM_COMP IS characterized in that two negative input ends are respectively connected with V_IS and V_SLOPE, the positive input end IS connected with V_COMP voltage, the PWM_COMP generates modulation pulse V_PWM by comparing the sum of the V_COMP voltage which IS input positively and the V_IS and V_SLOPE voltages of the negative input ends, when the V_COMP IS larger than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a high level, and when the V_COMP IS smaller than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a low level;
the input end S of the RS latch circuit is connected with the CLK, the input end R is connected with the V_PWM, when the rising edge of the CLK signal arrives, the output V_RS of the RS latch circuit is set, and when the rising edge of the V_PWM arrives, the output V_RS of the RS latch circuit is reset;
the digital LOGIC operation circuit LOGIC outputs N from the output end Q by performing LOGIC operation on the V_RS and CLK signals H Tube, N L And control signals V_ H, V _L and V_C for the Nc pipe, when V_RS is low, V_H is high when the falling edge of CLK comes, N is turned on H A tube; when V_RS is low, V_C is high when the rising edge of CLK arrives, and an Nc pipe is opened; when CLK is low and V_L is high when the rising edge of V_RS arrives, N will be turned on L A tube;
the level conversion circuit converts the V_H voltage into a logic voltage V with the same level as the BOOST High ；
The N is H The tube driving circuit will enhance the driving capability of VHigh, and output can drive N H Logic signals of (a);
the N is L The tube driving circuit will enhance the driving capability of V_L, and output the driving N L Logic signals;
the Nc tube driving circuit enhances the driving capability of CLK and outputs logic signals capable of driving Nc.
The invention has the advantages that the BOOST capacitor can be timely charged before the high-side power tube is opened when the input voltage is input or the input is slowly electrified, so that the BOOST can be ensured to have enough voltage capacity, and the high-side power tube can be normally opened when the LOGIC signal for opening the high-side power tube is sent out by the LOGIC circuit; when the DC-DC is in a light load or no-load state, the main power loss of the chip is the switching loss of the power tube, and the DC-DC BOOST self-charging circuit provided by the invention enters a light load high-efficiency mode in the light load or no-load mode, and the high-side and low-side power tubes are not conducted in each period, so that the switching loss is greatly reduced, and the efficiency of the chip in the light load or no-load state is effectively improved.
Drawings
Fig. 1 is a block diagram of an embodiment of a control circuit of the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
As shown in FIG. 1, a DC-DC BOOST self-charging circuit comprises a sampling resistor Rs, a high-side N-type power tube N H Low side N-type power tube N L And Nc, internal power supply and reference circuit Regulator&Reference, BOOST charge diode D1, error amplifier EA, current sampling circuit comp_is, waveform generator Waveform Generator, PWM modulation comparator circuit pwm_comp, RS latch circuit, digital LOGIC circuit LOGIC, level Shift, N H Tube driving circuit buffer_H, N L Tube driving circuit buffer_l, nc tube driving circuit buffer_c;
one end of the sampling resistor Rs is connected to the input V IN The other end of the sampling resistor Rs is connected to N H The drain end CSN, rs of the tube flows through N by sampling H The current of the tube, the current is converted into the sampling voltage;
the N-type power tube N H Is composed of N H Output drive of tube driving circuit buffer_H and N-type power tube N H Is connected with the SW end of the chip, when N H When conducting, the current is input V IN Flows to SW when N H When turned off, V IN The current path to SW is blocked;
the N-type power tube N L And Nc, N L The grid electrode is composed of N L Output drive of tube drive circuit buffer_L, N L The source electrode is connected with the GND end of the chip, N L The drain end is connected with the SW end of the chip, the Nc grid is driven by the output of the Nc tube driving circuit buffer_C, and the Nc source electrode is connected with the chipThe GND end and the Nc drain end of the chip are connected with the SW end of the chip, when N L When Nc is conducted, the inductor current is freewheeled, when N L When Nc is turned off, the signal passes through N L Parasitic diodes of Nc carry out follow current on the inductance current;
the internal power supply and Reference circuit Regulator and Reference coarse tune the input voltage to generate three paths of internal power supplies VR1, VR2 and VR3 and an internal Reference voltage VREF respectively;
the anode of the BOOST charging diode D1 is connected with the internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the power supply is connected with the power supply at the N H When the tube is conducted, VR3 charges the BOOST capacitor through D1;
the error amplifier EA is connected with an internal reference voltage VREF at the positive input end and an external feedback voltage VFB at the negative input end, amplifies the voltage difference between VREF and VFB and outputs an error amplification voltage V_COMP;
the current sampling circuit COMP_IS IS connected with the input voltage VIN at the positive input end and the CSN node at the negative input end, and amplifies the sampling voltage on the sampling resistor Rs to output the voltage V_IS;
the waveform generator Waveform Generator, when the circuit is operating normally, will generate a row of square waves CLK and a row of sawtooth waves V_SLOPE;
the PWM modulation comparator circuit PWM_COMP IS characterized in that two negative input ends are respectively connected with V_IS and V_SLOPE, the positive input end IS connected with V_COMP voltage, the PWM_COMP generates modulation pulse V_PWM by comparing the sum of the V_COMP voltage which IS input positively and the V_IS and V_SLOPE voltages of the negative input ends, when the V_COMP IS larger than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a high level, and when the V_COMP IS smaller than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a low level;
the input end S of the RS latch circuit is connected with the CLK, the input end R is connected with the V_PWM, when the rising edge of the CLK signal arrives, the output V_RS of the RS latch circuit is set, and when the rising edge of the V_PWM arrives, the output V_RS of the RS latch circuit is reset;
the digital LOGIC operation circuit LOGIC outputs N from the output end Q by performing LOGIC operation on the V_RS and CLK signals H Tube, N L And Nc tubeControl signals V_ H, V _L and V_C, when V_RS is low, V_H is high when the falling edge of CLK arrives, N is turned on H A tube; when V_RS is low, V_C is high when the rising edge of CLK arrives, and an Nc pipe is opened; when CLK is low and V_L is high when the rising edge of V_RS arrives, N will be turned on L A tube;
the Level Shift circuit converts the V_H voltage to a logic voltage VHigh which is the same Level as the BOOST;
the N is H The tube driving circuit buffer_H will enhance the driving capability of VHigh and output the driving N H Logic signals of (a);
the N is L The driving circuit buffer_L will enhance the driving capability of V_L, and output the driving N L Logic signals;
the Nc tube driving circuit buffer_C enhances the driving capability of CLK and outputs a logic signal capable of driving Nc;
the DC-DC converter mainly comprises two parts in fig. 1, namely a DC-DC converter and an output power stage, namely a controller and a power stage;
the output power stage of FIG. 1 filters the SW output voltage to provide a stabilized output voltage Vout via a feedback resistor R H And R is L Dividing and feeding back an output voltage to the FB terminal of the chip, the output power stage including a BOOST capacitor C boost Power inductance L, output capacitance Cout, high side feedback resistance R H Low side feedback resistor R L The method comprises the steps of carrying out a first treatment on the surface of the Power inductances L and C boost One end of each of the two is connected with the SW end of the chip, C boos t is connected with the BOOST end of the chip, and the other end of L is connected with the output Vout, C out And RH are connected to the output Vout, C out The other end of RH and one end of RL are connected to FB, and the other end of RL is grounded; wherein C is boost Is a device for storing energy for normally opening the high-side power tube;
the DC-DC converter shown in FIG. 1 includes a sampling resistor Rs, a high-side N-type power tube N H Low side N-type power tube N L And Nc, internal power and reference circuits, BOOST charge diode D1, error amplifier EA, current sampling circuit comp_is, waveform generator Waveform Generator, PWM modulation comparator circuitPWM_COMP, RS latch circuit, digital LOGIC operation circuit LOGIC, level Shift circuit Level Shift, N H Tube driving circuit buffer_H, N L Tube driving circuit buffer_l and Nc tube driving circuit buffer_c.
The sampling resistor Rs depicted in FIG. 1 is connected to inputs VIN and N H The drain end CSN, rs of the tube flows through N by sampling H The current of the tube, the current is converted into the sampling voltage;
n-type power tube N shown in FIG. 1 H The grid is driven by the output of buffer_H, the source is connected with the SW end of the chip, when N H When turned on, current flows from input VIN to SW, when N H When turned off, VIN flows to SW current path is blocked;
n-type power tube N shown in FIG. 1 L And Nc, N L The grid electrode is driven by the output of buffer_L, the source electrode is connected with the GND end of the chip, the drain electrode is connected with the SW end of the chip, the Nc grid electrode is driven by the output of buffer_L, the source electrode is connected with the GND end of the chip, the drain electrode is connected with the SW end of the chip, and when N is L When Nc is conducted, the inductor current is freewheeled, when N L When Nc is turned off, the signal passes through N L Parasitic diodes of Nc carry out follow current on the inductance current;
the internal power supply and Reference circuit Regulator & Reference shown in fig. 1 will perform coarse adjustment on the output voltage to generate three internal power supplies VR1, VR2, VR3 and an internal Reference voltage VREF;
the BOOST charge diode D1 shown in FIG. 1 has an anode connected to the internal power supply VR3 and a cathode connected to the BOOST terminal of the chip, and is shown in N H When the tube is conducted, VR3 charges the BOOST capacitor through D1;
the error amplifier EA shown in fig. 1 has a positive input terminal connected to the internal reference voltage VREF, a negative input terminal connected to the external feedback voltage VFB, and amplifies the voltage difference between VREF and VFB to output an error amplified voltage v_comp;
in the current sampling circuit comp_is shown in fig. 1, the positive input terminal IS connected with the input voltage VIN, the negative input terminal IS connected with the CSN node, the comp_is amplifies the sampling voltage on the sampling resistor, and the voltage v_is IS output;
the waveform generator Waveform Generator of FIG. 1 will generate a row of square waves CLK and a row of sawtooth waves V_SLOPE during normal operation of the circuit;
the PWM modulation comparator circuit pwm_comp shown in fig. 1 has two negative input terminals connected to v_is and v_slope, respectively, and a positive input terminal connected to v_comp voltage, where pwm_comp generates a modulated pulse v_pwm by comparing the sum of v_comp and v_is, v_slope voltages, where v_pwm IS high when v_comp IS greater than the sum of v_is, v_slope voltages, and v_pwm IS low when v_comp IS less than the sum of v_is, v_slope voltages;
in the RS latch circuit shown in fig. 1, the input terminal S is connected to CLK, the input terminal R is connected to v_pwm, when the rising edge of the CLK signal arrives, the output v_rs of the RS latch will be set, and when the rising edge of the v_pwm arrives, the output v_rs of the RS latch will be reset;
the digital LOGIC operation circuit LOGIC shown in FIG. 1 outputs on or off N by performing LOGIC operation on signals such as V_RS and CLK H Tube, N L Control signals v_ H, V _l and v_c for the pipes and Nc pipes;
the Level Shift circuit of FIG. 1 converts the V_H voltage to a higher Level logic voltage VHigh;
n is described in FIG. 1 H The tube driving circuit buffer_H will enhance the driving capability of VHigh and output the driving N H Logic signals of (a);
n is described in FIG. 1 L The tube driving circuit buffer_L will enhance the driving capability of V_L, and output the driving N L Logic signals of (a);
the Nc tube driving circuit buffer_c shown in fig. 1 will enhance the driving capability of CLK, and output logic signals capable of driving Nc;
in the circuit shown in FIG. 1, when Vfb is lower than VREF, V_COMP is raised, V_RS is set when the rising edge of CLK arrives, and the LOGIC module sends out the high-side power transistor N H The signal is converted by a level_shift circuit and driven by Buffer enhancement to open a high-side power tube, current flows from an input VIN to an output LC filter to generate an output voltage Vout, the Vout generates a feedback voltage Vfb through RH and RL voltage division, and a sampling resistor Rs flows through N through sampling H The current of the tube, converting the current into a sampled voltage, when the sum of the sampled voltages V_IS and V_SLOPE IS greater than VWhen_comp, v_pwm outputs a low level signal, v_rs is reset, LOGIC signals for turning off the high-side power transistor and turning on the low-side power transistor are sent by the LOGIC circuit of the LOGIC circuit, at this time, the high-side power transistor is turned off and the low-side power transistor is turned on by the internal circuit of the chip, the inductor current is freewheeled by the low-side power transistor, and during this time, the capacitor Cboost is charged by the internal power supply VR3 through D1. The switching period of DC-DC is determined by the internal CLK signal, the CLK signal is a square wave with a small positive duty cycle, the power tube Nc shown in FIG. 1 is turned on when CLK is high, the SW voltage is pulled down to ground, the internal power supply VR3 charges the capacitor Cboost through D1, and therefore under N-load, light-load or heavy-load conditions H Before the power tube is opened, the Nc power tube is opened in advance for a short period of time, and a certain margin is required to be reserved for the positive duty cycle of the CLK signal in order to ensure that the energy charged by the Cboost is enough to open the upper tube in the period of time; the circuit shown in FIG. 1 is in a light load high efficiency mode, i.e. N under no load light load H The tube can be conducted once to supplement enough energy for output, so that VFB will be higher than VREF in a longer time, and N is higher than VREF in no-load or light-load conditions H 、N L Rather than turning on each cycle to power the output, the Nc power tube is turned on again after detecting a certain value below VREF H The circuit effectively reduces the switching loss, so that the circuit provides the charging function for the Cboost and simultaneously gives consideration to the efficiency of no-load and light-load.

Claims (1)

1. A DC-DC BOOST self-charging circuit comprises a sampling resistor Rs, a high-side N-type power tube N H Low side N-type power tube N L And Nc, internal power supply and reference circuit, BOOST charge diode D1, error amplifier EA, current sampling circuit, waveform generator, PWM modulation comparator circuit, RS latch circuit, digital logic operation circuit, level conversion circuit, N H Tube driving circuit, N L Tube driving circuit, nc tube driving circuit, its characterized in that:
the DC-DC BOOST self-charging circuit has one end of a sampling resistor Rs connected to the input V IN The other end of the sampling resistor Rs is connected withTo N H The drain end CSN, rs of the tube flows through N by sampling H The current of the tube, the current is converted into the sampling voltage;
the N-type power tube N H Is composed of N H Output drive of tube drive circuit, N-type power tube N H Is connected with the SW end of the chip, when N H When conducting, the current is input V IN Flows to SW when N H When turned off, V IN The current path to SW is blocked;
the N-type power tube N L And Nc, N L The grid electrode is composed of N L Output drive of tube driving circuit, N L The source electrode is connected with the GND end of the chip, N L The drain terminal is connected with the SW end of the chip, the Nc grid is driven by the output of the Nc tube driving circuit, the Nc source electrode is connected with the GND end of the chip, the Nc drain terminal is connected with the SW end of the chip, and when N is L When Nc is conducted, the inductor current is freewheeled, when N L When Nc is turned off, the signal passes through N L Parasitic diodes of Nc carry out follow current on the inductance current;
the internal power supply and the reference circuit are used for carrying out coarse adjustment on input voltage to respectively generate three paths of internal power supplies VR1, VR2 and VR3 and an internal reference voltage VREF;
the anode of the BOOST charging diode D1 is connected with the internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the power supply is connected with the power supply at the N H When the tube is conducted, VR3 charges the BOOST capacitor through D1;
the error amplifier EA is connected with an internal reference voltage VREF at the positive input end and an external feedback voltage VFB at the negative input end, amplifies the voltage difference between VREF and VFB and outputs an error amplification voltage V_COMP;
the current sampling circuit COMP_IS IS connected with the input voltage VIN at the positive input end and the CSN node at the negative input end, and amplifies the sampling voltage on the sampling resistor Rs to output the voltage V_IS;
the waveform generator generates a row of square waves CLK and a row of sawtooth waves V_SLOPE when the circuit works normally;
the PWM modulation comparator circuit PWM_COMP IS characterized in that two negative input ends are respectively connected with V_IS and V_SLOPE, the positive input end IS connected with V_COMP voltage, the PWM_COMP generates modulation pulse V_PWM by comparing the sum of the V_COMP voltage which IS input positively and the V_IS and V_SLOPE voltages of the negative input ends, when the V_COMP IS larger than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a high level, and when the V_COMP IS smaller than the sum of the V_IS and V_SLOPE voltages, the V_PWM IS in a low level;
the input end S of the RS latch circuit is connected with the CLK, the input end R is connected with the V_PWM, when the rising edge of the CLK signal arrives, the output V_RS of the RS latch circuit is set, and when the rising edge of the V_PWM arrives, the output V_RS of the RS latch circuit is reset;
the digital LOGIC operation circuit LOGIC outputs N from the output end Q by performing LOGIC operation on the V_RS and CLK signals H Tube, N L And control signals V_ H, V _L and V_C for the Nc pipe, when V_RS is low, V_H is high when the falling edge of CLK comes, N is turned on H A tube; when V_RS is low, V_C is high when the rising edge of CLK arrives, and an Nc pipe is opened; when CLK is low and V_L is high when the rising edge of V_RS arrives, N will be turned on L A tube;
the level conversion circuit converts the V_H voltage into a logic voltage V with the same level as the BOOST High ；
The N is H The tube driving circuit will enhance the driving capability of VHigh, and output can drive N H Logic signals of (a);
the N is L The tube driving circuit will enhance the driving capability of V_L, and output the driving N L Logic signals;
the Nc tube driving circuit enhances the driving capability of CLK and outputs logic signals capable of driving Nc.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102801317A (en) * 2012-08-16 2012-11-28 电子科技大学 Adaptive sectional driving DC-DC converter
CN103856014A (en) * 2012-11-30 2014-06-11 西安智海电力科技有限公司 Sampling BOOST circuit with output protection
US9800164B1 (en) * 2016-07-20 2017-10-24 Suzhou Poweron IC Design Co., Ltd Compensation circuit for constant output voltage
CN107546964A (en) * 2017-08-22 2018-01-05 成都芯辰微电子技术有限公司 A kind of loop control system and control method of DC DC converters
CN210111854U (en) * 2019-04-28 2020-02-21 西安拓尔微电子有限责任公司 DC-DC BOOST self-charging circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6278188B2 (en) * 2013-09-24 2018-02-14 サンケン電気株式会社 DC / DC converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102801317A (en) * 2012-08-16 2012-11-28 电子科技大学 Adaptive sectional driving DC-DC converter
CN103856014A (en) * 2012-11-30 2014-06-11 西安智海电力科技有限公司 Sampling BOOST circuit with output protection
US9800164B1 (en) * 2016-07-20 2017-10-24 Suzhou Poweron IC Design Co., Ltd Compensation circuit for constant output voltage
CN107546964A (en) * 2017-08-22 2018-01-05 成都芯辰微电子技术有限公司 A kind of loop control system and control method of DC DC converters
CN210111854U (en) * 2019-04-28 2020-02-21 西安拓尔微电子有限责任公司 DC-DC BOOST self-charging circuit

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