CN210111854U - DC-DC BOOST self-charging circuit - Google Patents
DC-DC BOOST self-charging circuit Download PDFInfo
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- CN210111854U CN210111854U CN201920603012.1U CN201920603012U CN210111854U CN 210111854 U CN210111854 U CN 210111854U CN 201920603012 U CN201920603012 U CN 201920603012U CN 210111854 U CN210111854 U CN 210111854U
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Abstract
The utility model provides a DC-DC BOOST self-charging circuit, when defeated pressure, low pressure input or input are gone up slowly, charge for the BOOST electric capacity before the high side power tube is opened, when guaranteeing that BOOST has sufficient voltage ability and sending the LOGIC signal of opening the high side power tube at LOGIC circuit, can normally open the high side power tube; DC-DC is in when underloading or idle state, and the main power loss of chip is the switching loss of power tube, the utility model discloses when underloading or idle mode, the chip is inside will get into underloading high-efficient mode, and high side and low side power tube will not all switch on in every cycle, have reduced switching loss greatly to the efficiency of chip when underloading or idle has effectively been promoted.
Description
Technical Field
The invention relates to the field of power supply management, in particular to a self-charging circuit.
Background
The direct current-to-direct current conversion chip (DC-DC converter chip) has the advantages of high integration, high driving, high efficiency, etc., the DC-DC converter chip is a very important functional module in the power management chip, and with the wide application of portable electronic products, higher requirements are also provided for the performance of the DC-DC converter chip: higher integration, higher efficiency, better transient response, etc.
The DC-DC converter chip can be divided into low-voltage, medium-high voltage, and high-voltage DC-DC according to the input voltage, and in the non-low-voltage DC-DC, the power tube usually adopts a double N-tube design method, i.e., both the high-side and low-side power tubes adopt N-type MOSFETs. When the high-side MOSFET is turned on, the source terminal voltage of the high-side MOSFET is ideally close to the input power supply voltage, therefore, the gate voltage of the high-side MOSFET must be greater than the power supply voltage to turn on the high-side MOSFET, and for faster turn-on speed and higher efficiency, the gate and source voltages of the MOSFET should be designed to be sufficiently large, and in medium-high voltage applications, the gate-source voltage of the MOSFET is generally designed to be about 5V or higher. However, under the condition of outputting high voltage and outputting no load, that is, when the output voltage is 5V or higher, the DC-DC chip may have a phenomenon that the output cannot be established, that is, the output voltage eventually cannot reach the set value.
According to research, the BOOST voltage is obtained by charging a capacitor connected between the BOOST and the SW through a diode by a fixed voltage in the DC-DC, and the main reason of the above phenomenon is that when the input is slowly powered on or the input is low voltage, the BOOST voltage cannot be charged because the input and output voltages are very close in the starting stage, so that the gate-source voltage of the DC-DC high-side MOSFET is too low to turn on the upper tube, and therefore, the output energy cannot be supplemented, and when the output is in idle load, the output is maintained in a state of a fixed value but less than a normal set value.
The researchers have designed BOOST self-charging circuits that force the low-side MOSFET of the DC-DC converter to turn on at a fixed duty cycle for each switching cycle of the DC-DC switching converter, and when the low-side MOSFET is turned on, the voltage of SW is zero voltage, and the BOOST voltage is less than the internal supply voltage, during which time the internal supply will charge the BOOST capacitor through the diode. The method can well solve the problem that the output cannot be started when the low-voltage input or the slow power-on occurs, but because the low-side MOSFET is conducted according to the fixed duty ratio in each period, the efficiency of the DC-DC is extremely poor when the power is no-load or light-load.
Disclosure of Invention
The invention provides a DC-DC BOOST self-charging circuit, which aims to overcome the defects of the prior art and solve the problems of low-voltage input, incapability of starting output during slow power-on and poor no-load light-load efficiency. The circuit can charge the BOOST in time when outputting high voltage, inputting low voltage or inputting slow power-on, and the circuit can not forcibly open the lower tube in each period when in light load or no load, so that energy loss can not exist in each period, and the efficiency of the DC-DC in no load or light load is greatly improved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a DC-DC BOOST self-charging circuit comprises a sampling resistor Rs and a high-side N-type power tube NHLow side N-type power tube NLNc, internal power supply and reference circuit, BOOST charging diode D1, error amplifier EA, current sampling circuit, waveform generator, PWM modulation comparator circuit, RS latch circuit, digital logic operation circuit, level conversion circuit, NHTube driver circuit, NLA tube driving circuit, Nc tube driving circuit;
one end of the sampling resistor Rs is connected to the input VINThe other end of the sampling resistor Rs is connected to NHThe discharge end of the tube CSN, Rs flows through N by samplingHThe current of the tube is converted into sampling voltage;
the N-type power tube NHIs formed by NHOutput drive of tube driving circuit, N-type power tube NHSource of (2) is connected to SW terminal of the chip, when N isHWhen conducting, the current is input by VINFlows to SW when NHWhen turned off, VINThe current path to SW is blocked;
the N-type power tube NLAnd Nc, NLGrid is formed by NLOutput drive of the tube drive circuit, NLSource connected to GND terminal of chip, NLThe drain is connected with the SW end of the chip, and the Nc grid is driven by the Nc tubeThe output of the circuit is driven, the source of Nc is connected with GND end of chip, the drain of Nc is connected with SW end of chip, when N isLNc, when it is conducted, it will freewheel the inductive current, when N isLNc is turned off, N will be passedLThe parasitic diode of Nc carries out follow current on the inductive current;
the internal power supply and the reference circuit perform coarse adjustment on input voltage to respectively generate three internal power supplies VR1, VR2, VR3 and an internal reference voltage VREF;
the anode of the BOOST charging diode D1 is connected with an internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the voltage is measured at NHWhen the tube is conducted, VR3 charges the BOOST capacitor through D1;
the positive input end of the error amplifier EA is connected with an internal reference voltage VREF, the negative input end of the error amplifier EA is connected with an external feedback voltage VFB, and the error amplifier EA amplifies the voltage difference value of the VREF and the VFB and outputs an error amplification voltage V _ COMP voltage;
the positive input end of the current sampling circuit COMP _ IS IS connected with the input voltage VIN, the negative input end of the current sampling circuit COMP _ IS IS connected with the CSN node, and the sampling voltage on the sampling resistor Rs IS amplified by the current sampling circuit COMP _ IS to output a V _ IS voltage;
the waveform generator generates a column of square wave CLK and a column of sawtooth wave V _ SLOPE when the circuit works normally;
the PWM modulation comparator circuit PWM _ COMP IS characterized in that two negative input ends are respectively connected with V _ IS and V _ SLOPE, a positive input end IS connected with V _ COMP voltage, the PWM _ COMP generates modulation pulse V _ PWM by comparing the sum of the V _ COMP voltage of the positive input end and the V _ IS and V _ SLOPE voltage of the negative input end, when the V _ COMP IS greater than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a high level, and when the V _ COMP IS less than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a low level;
in the RS latch circuit, an input end S is connected with CLK, an input end R is connected with V _ PWM, when the rising edge of a CLK signal comes, the output V _ RS of the RS latch is set, and when the rising edge of the V _ PWM comes, the output V _ RS of the RS latch is reset;
the digital LOGIC operation circuit LOGIC performs LOGIC operation on V _ RS and CLK signals to output N from an output end QHPipe, NLAnd control signals V _ H, V _ L and V _ C of Nc tube, when V _ RS is low, V _ H is high when falling edge of CLK comes, N is openedHA tube; when V _ RS is low and the rising edge of CLK arrives, V _ C is high, and the Nc pipe is opened; when CLK is low, V _ RS rises and V _ L goes high, N will be turned onLA tube;
the level conversion circuit converts the V _ H voltage into a logic voltage V at the same level as the BOOSTHigh；
Said N isHThe tube driving circuit can enhance the driving capability of VHigh and output can drive NHThe logic signal of (1);
said N isLThe tube driving circuit can enhance the driving capability of V _ L, and the output can drive NLA logic signal;
the Nc tube driving circuit enhances the driving capability of CLK and outputs a logic signal capable of driving Nc.
The invention has the advantages that when the voltage is input, the low-voltage input or the input is slowly electrified, the BOOST capacitor can be charged in time before the high-side power tube is opened, so that the BOOST has enough voltage capability, and the high-side power tube can be normally opened when the LOGIC circuit sends out a LOGIC signal for opening the high-side power tube; when the DC-DC is in a light load or no-load state, the main power loss of the chip is the switching loss of the power tube, when the DC-DC BOOST self-charging circuit provided by the invention is in the light load or no-load mode, the interior of the chip enters a light load high-efficiency mode, the high-side power tube and the low-side power tube are not conducted in each period, the switching loss is greatly reduced, and the efficiency of the chip in the light load or no-load state is effectively improved.
Drawings
FIG. 1 is a block diagram of an embodiment of a control circuit according to the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in FIG. 1, a DC-DC BOOST self-charging circuit comprises a sampling resistor Rs, a high-side N-type power tube NHLow side N-type power tube NLAnd Nc, internal power supply and reference circuit Regulator&Reference, BOOST chargerA diode D1, an error amplifier EA, a current sampling circuit COMP _ IS, a Waveform Generator, a PWM modulation comparator circuit PWM _ COMP, an RS latch circuit, a digital LOGIC operation circuit LOGIC, a Level conversion circuit Level Shift, NHTube driving circuit Buffer _ H, NLA tube driving circuit Buffer _ L and an Nc tube driving circuit Buffer _ C;
one end of the sampling resistor Rs is connected to the input VINThe other end of the sampling resistor Rs is connected to NHThe discharge end of the tube CSN, Rs flows through N by samplingHThe current of the tube is converted into sampling voltage;
the N-type power tube NHIs formed by NHOutput drive of tube drive circuit Buffer _ H, N-type power tube NHSource of (2) is connected to SW terminal of the chip, when N isHWhen conducting, the current is input by VINFlows to SW when NHWhen turned off, VINThe current path to SW is blocked;
the N-type power tube NLAnd Nc, NLGrid is formed by NLOutput drive of the tube drive circuit Buffer _ L, NLSource connected to GND terminal of chip, NLDrain terminal is connected with SW terminal of chip, Nc grid is driven by output of Nc tube driving circuit Buffer _ C, Nc source is connected with GND terminal of chip, Nc drain terminal is connected with SW terminal of chip, when N isLNc, when it is conducted, it will freewheel the inductive current, when N isLNc is turned off, N will be passedLThe parasitic diode of Nc carries out follow current on the inductive current;
the internal power supply and Reference circuit Regulator & Reference coarsely adjusts the input voltage to respectively generate three internal power supplies VR1, VR2, VR3 and an internal Reference voltage VREF;
the anode of the BOOST charging diode D1 is connected with an internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the voltage is measured at NHWhen the tube is conducted, VR3 charges the BOOST capacitor through D1;
the positive input end of the error amplifier EA is connected with an internal reference voltage VREF, the negative input end of the error amplifier EA is connected with an external feedback voltage VFB, and the error amplifier EA amplifies the voltage difference value of the VREF and the VFB and outputs an error amplification voltage V _ COMP voltage;
the positive input end of the current sampling circuit COMP _ IS IS connected with the input voltage VIN, the negative input end of the current sampling circuit COMP _ IS IS connected with the CSN node, and the sampling voltage on the sampling resistor Rs IS amplified by the current sampling circuit COMP _ IS to output a V _ IS voltage;
the Waveform Generator generates a row of square wave CLK and a row of sawtooth waves V _ SLOPE when the circuit works normally;
the PWM modulation comparator circuit PWM _ COMP IS characterized in that two negative input ends are respectively connected with V _ IS and V _ SLOPE, a positive input end IS connected with V _ COMP voltage, the PWM _ COMP generates modulation pulse V _ PWM by comparing the sum of the V _ COMP voltage of the positive input end and the V _ IS and V _ SLOPE voltage of the negative input end, when the V _ COMP IS greater than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a high level, and when the V _ COMP IS less than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a low level;
in the RS latch circuit, an input end S is connected with CLK, an input end R is connected with V _ PWM, when the rising edge of a CLK signal comes, the output V _ RS of the RS latch is set, and when the rising edge of the V _ PWM comes, the output V _ RS of the RS latch is reset;
the digital LOGIC operation circuit LOGIC performs LOGIC operation on V _ RS and CLK signals to output N from an output end QHPipe, NLAnd control signals V _ H, V _ L and V _ C of Nc tube, when V _ RS is low, V _ H is high when falling edge of CLK comes, N is openedHA tube; when V _ RS is low and the rising edge of CLK arrives, V _ C is high, and the Nc pipe is opened; when CLK is low, V _ RS rises and V _ L goes high, N will be turned onLA tube;
the Level conversion circuit Level Shift converts the V _ H voltage to a logic voltage VHigh at the same Level as the BOOST;
said N isHThe driving capability of VHigh is enhanced by the tube driving circuit Buffer _ H, and N can be driven by the outputHThe logic signal of (1);
said N isLThe driving circuit Buffer _ L will enhance the driving capability of V _ L, and the output can drive NLA logic signal;
the Nc tube driving circuit Buffer _ C can enhance the driving capability of CLK and output a logic signal capable of driving Nc;
fig. 1 mainly includes two parts, namely a DC-DC converter and an output power stage, namely a controller and a power stage;
the output power stage shown in fig. 1 will filter the SW output voltage to provide a stable output voltage Vout through a feedback resistor RHAnd RLThe output voltage is divided and fed back to the FB terminal of the chip, and the output power stage comprises a BOOST capacitor CboostPower inductor L, output capacitor Cout, high side feedback resistor RHLow side feedback resistor RL(ii) a Power inductors L and CboostOne terminal of each of the first and second terminals is connected to the SW terminal, C of the chipboosthe other end of t is connected with the BOOST end of the chip, the other end of L is connected with the output Vout, CoutAnd RH are connected at one end to the output Vout, CoutThe other side of the RH is grounded, the other end of the RH and one end of the RL are both connected with the FB, and the other side of the RL is grounded; wherein C isboostThe device is used for storing energy for normally opening the high-side power tube;
the DC-DC converter shown in FIG. 1 comprises a sampling resistor Rs, a high-side N-type power tube NHLow side N-type power tube NLNc, an internal power supply and reference circuit, a BOOST charging diode D1, an error amplifier EA, a current sampling circuit COMP _ IS, a Waveform Generator, a PWM modulation comparator circuit PWM _ COMP, an RS latch circuit, a digital LOGIC operation circuit LOGIC, a Level conversion circuit Level Shift, NHTube driving circuit Buffer _ H, NLA tube driving circuit Buffer _ L, and an Nc tube driving circuit Buffer _ C.
The sampling resistor Rs of FIG. 1 is connected to the inputs VIN and NHThe discharge end of the tube CSN, Rs flows through N by samplingHThe current of the tube is converted into sampling voltage;
FIG. 1 shows an N-type power tube NHThe grid is driven by the output of Buffer _ H, the source is connected with the SW end of the chip, when N isHWhen turned on, current flows from input VIN to SW when N isHWhen the switch is turned off, VIN flows to the SW current path and is blocked;
FIG. 1 shows an N-type power tube NLAnd Nc, NLThe gate is driven by the output of Buffer _ L, the source is connected with GND terminal of the chip, and the drain is connected with SW of the chipEnd, Nc grid driven by the output of Buffer _ L, source connected to GND end of chip, drain connected to SW end of chip, when N is less than NLNc, when it is conducted, it will freewheel the inductive current, when N isLNc is turned off, N will be passedLThe parasitic diode of Nc carries out follow current on the inductive current;
the internal power supply and Reference circuit Regulator & Reference of FIG. 1 will coarsely adjust the output voltage to produce three internal power supplies VR1, VR2, VR3 and an internal Reference voltage VREF;
the BOOST charging diode D1 shown in FIG. 1 has its anode connected to the internal power supply VR3 and its cathode connected to the BOOST terminal of the chip at NHWhen the tube is conducted, VR3 charges the BOOST capacitor through D1;
in the error amplifier EA shown in fig. 1, a positive input terminal is connected to an internal reference voltage VREF, a negative input terminal is connected to an external feedback voltage VFB, and the error amplifier EA amplifies a voltage difference between VREF and VFB to output an error amplification voltage V _ COMP voltage;
in the current sampling circuit COMP _ IS shown in fig. 1, a positive input end IS connected with an input voltage VIN, a negative input end IS connected with a CSN node, and the COMP _ IS amplifies a sampling voltage on a sampling resistor to output a V _ IS voltage;
the Waveform Generator shown in FIG. 1 will generate a row of square wave CLK and a row of sawtooth wave V _ SLOPE when the circuit is working normally;
the PWM modulation comparator circuit PWM _ COMP of fig. 1, two negative input terminals are respectively connected to V _ IS and V _ SLOPE, a positive input terminal IS connected to V _ COMP voltage, PWM _ COMP generates a modulation pulse V _ PWM by comparing V _ COMP with the sum of V _ IS and V _ SLOPE voltages, V _ PWM IS high when V _ COMP IS greater than the sum of V _ IS and V _ SLOPE voltages, and V _ PWM IS low when V _ COMP IS less than the sum of V _ IS and V _ SLOPE voltages;
the RS latch circuit of FIG. 1 has an input terminal S connected with CLK and an input terminal R connected with V _ PWM, when the rising edge of CLK signal comes, the output V _ RS of RS latch will be set, when the rising edge of V _ PWM comes, the output V _ RS of RS latch will be reset;
the LOGIC circuit LOGIC of FIG. 1 outputs ON or OFF by performing LOGIC operation on V _ RS and CLK signalsClosed NHPipe, NLTube and Nc tube control signals V _ H, V _ L and V _ C;
the Level Shift circuit Level Shift of fig. 1 converts the V _ H voltage to a higher Level logic voltage VHigh;
FIG. 1 depicts NHThe driving capability of VHigh is enhanced by the tube driving circuit Buffer _ H, and N can be driven by the outputHThe logic signal of (1);
FIG. 1 depicts NLThe driving capability of the V _ L is enhanced by the tube driving circuit Buffer _ L, and the output can drive NLThe logic signal of (1);
the Nc tube driving circuit Buffer _ C in FIG. 1 will enhance the driving capability of CLK and output a logic signal capable of driving Nc;
in the circuit shown in FIG. 1, when the Vfb voltage is lower than the VREF voltage, the voltage of V _ COMP rises, when the rising edge of CLK comes, V _ RS is set, and the LOGIC module sends out a high-side power tube NHThe signal is converted by a Level _ Shift circuit and is driven by Buffer enhancement to open a high-side power tube, current flows from an input VIN to an output LC filter to generate an output voltage Vout, the Vout generates a feedback voltage Vfb by dividing the voltage by RH and RL, and a sampling resistor Rs flows through N by samplingHThe current of the tube IS converted into a sampling voltage, when the sum of the voltages of the sampling voltages V _ IS and V _ SLOPE IS greater than V _ COMP, V _ PWM outputs a low level signal, V _ RS IS reset, the LOGIC circuit sends out LOGIC signals for closing a high-side power tube and opening a low-side power tube, at the moment, the chip internal circuit closes the high-side power tube and opens the low-side power tube, the low-side power tube freewheels the inductive current, and in the moment, the internal power supply VR3 charges the capacitor Cboost through D1. The switching period of the DC-DC is determined by the internal CLK signal, which is a square wave with a small positive duty cycle, and the power transistor Nc shown in fig. 1 is turned on when CLK is high, at which time the SW voltage is pulled low to ground, and the internal power supply VR3 charges the capacitor Cboost through D1, so that under no-load, light-load or heavy-load conditions, N is the sameHThe Nc power transistor is turned on a short time ahead of the power transistor, and the CLK signal needs to be asserted to ensure that the Cboost is charged enough to turn on the upper transistor during the short timeA certain margin is reserved for the positive duty ratio; the circuit of fig. 1 is set in a light-load high-efficiency mode, i.e. in no-load and light-load conditions, NHThe tube is conducted once to supplement enough energy for output, so that VFB is higher than VREF in a longer time, and N is higher than VREF in no-load or light-load conditionsH、NLNc power tube is not conducted to provide energy for output in every period, but N is turned on after detecting a certain value lower than VREFHThis is effective in reducing switching losses, so that the circuit provides a charging function for Cboost while giving consideration to no-load and light-load efficiency.
Claims (1)
1. A DC-DC BOOST self-charging circuit comprises a sampling resistor Rs and a high-side N-type power tube NHLow side N-type power tube NLNc, internal power supply and reference circuit, BOOST charging diode D1, error amplifier EA, current sampling circuit, waveform generator, PWM modulation comparator circuit, RS latch circuit, digital logic operation circuit, level conversion circuit, NHTube driver circuit, NLA tube driving circuit, Nc tube driving circuit, characterized in that:
one end of a sampling resistor Rs of the DC-DC BOOST self-charging circuit is connected to an input VINThe other end of the sampling resistor Rs is connected to NHThe discharge end of the tube CSN, Rs flows through N by samplingHThe current of the tube is converted into sampling voltage;
the N-type power tube NHIs formed by NHOutput drive of tube driving circuit, N-type power tube NHSource of (2) is connected to SW terminal of the chip, when N isHWhen conducting, the current is input by VINFlows to SW when NHWhen turned off, VINThe current path to SW is blocked;
the N-type power tube NLAnd Nc, NLGrid is formed by NLOutput drive of the tube drive circuit, NLSource connected to GND terminal of chip, NLDrain terminal is connected with SW terminal of chip, Nc grid is driven by output of Nc tube driving circuit, Nc source terminal is connected with GND terminal of chip, Nc drain terminal is connected with SW terminal of chipLNc, when conducting, will be current to the inductorFollow current when NLNc is turned off, N will be passedLThe parasitic diode of Nc carries out follow current on the inductive current;
the internal power supply and the reference circuit perform coarse adjustment on input voltage to respectively generate three internal power supplies VR1, VR2, VR3 and an internal reference voltage VREF;
the anode of the BOOST charging diode D1 is connected with an internal power supply VR3, the cathode is connected with the BOOST end of the chip, and the voltage is measured at NHWhen the tube is conducted, VR3 charges the BOOST capacitor through D1;
the positive input end of the error amplifier EA is connected with an internal reference voltage VREF, the negative input end of the error amplifier EA is connected with an external feedback voltage VFB, and the error amplifier EA amplifies the voltage difference value of the VREF and the VFB and outputs an error amplification voltage V _ COMP voltage;
the positive input end of the current sampling circuit COMP _ IS IS connected with the input voltage VIN, the negative input end of the current sampling circuit COMP _ IS IS connected with the CSN node, and the sampling voltage on the sampling resistor Rs IS amplified by the current sampling circuit COMP _ IS to output a V _ IS voltage;
the waveform generator generates a column of square wave CLK and a column of sawtooth wave V _ SLOPE when the circuit works normally;
the PWM modulation comparator circuit PWM _ COMP IS characterized in that two negative input ends are respectively connected with V _ IS and V _ SLOPE, a positive input end IS connected with V _ COMP voltage, the PWM _ COMP generates modulation pulse V _ PWM by comparing the sum of the V _ COMP voltage of the positive input end and the V _ IS and V _ SLOPE voltage of the negative input end, when the V _ COMP IS greater than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a high level, and when the V _ COMP IS less than the sum of the V _ IS and V _ SLOPE voltages, the V _ PWM IS at a low level;
in the RS latch circuit, an input end S is connected with CLK, an input end R is connected with V _ PWM, when the rising edge of a CLK signal comes, the output V _ RS of the RS latch is set, and when the rising edge of the V _ PWM comes, the output V _ RS of the RS latch is reset;
the digital LOGIC operation circuit LOGIC performs LOGIC operation on V _ RS and CLK signals to output N from an output end QHPipe, NLAnd control signals V _ H, V _ L and V _ C of Nc tube, when V _ RS is low, V _ H is high when falling edge of CLK comes, N is openedHA tube; when V _ RS is low, CLK rising edge comesV _ C is high, and the Nc tube is opened; when CLK is low, V _ RS rises and V _ L goes high, N will be turned onLA tube;
the level conversion circuit converts the V _ H voltage into a logic voltage V at the same level as the BOOSTHigh；
Said N isHThe tube driving circuit can enhance the driving capability of VHigh and output can drive NHThe logic signal of (1);
said N isLThe tube driving circuit can enhance the driving capability of V _ L, and the output can drive NLA logic signal;
the Nc tube driving circuit enhances the driving capability of CLK and outputs a logic signal capable of driving Nc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920603012.1U CN210111854U (en) | 2019-04-28 | 2019-04-28 | DC-DC BOOST self-charging circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920603012.1U CN210111854U (en) | 2019-04-28 | 2019-04-28 | DC-DC BOOST self-charging circuit |
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| Publication Number | Publication Date |
|---|---|
| CN210111854U true CN210111854U (en) | 2020-02-21 |
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|---|---|---|---|
| CN201920603012.1U Withdrawn - After Issue CN210111854U (en) | 2019-04-28 | 2019-04-28 | DC-DC BOOST self-charging circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110048602A (en) * | 2019-04-28 | 2019-07-23 | 西安拓尔微电子有限责任公司 | A kind of DC-DC BOOST self-charging circuit |
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2019
- 2019-04-28 CN CN201920603012.1U patent/CN210111854U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110048602A (en) * | 2019-04-28 | 2019-07-23 | 西安拓尔微电子有限责任公司 | A kind of DC-DC BOOST self-charging circuit |
| CN110048602B (en) * | 2019-04-28 | 2024-02-13 | 拓尔微电子股份有限公司 | DC-DC BOOST self-charging circuit |
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