CN110034174A - High electron mobility transistor epitaxial wafer and preparation method thereof - Google Patents
High electron mobility transistor epitaxial wafer and preparation method thereof Download PDFInfo
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- CN110034174A CN110034174A CN201910150363.6A CN201910150363A CN110034174A CN 110034174 A CN110034174 A CN 110034174A CN 201910150363 A CN201910150363 A CN 201910150363A CN 110034174 A CN110034174 A CN 110034174A
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- 239000000758 substrate Substances 0.000 claims abstract description 72
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- 238000005036 potential barrier Methods 0.000 claims abstract description 18
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract 11
- 238000000034 method Methods 0.000 claims description 44
- 230000012010 growth Effects 0.000 claims description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 19
- 239000012298 atmosphere Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
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- 230000008021 deposition Effects 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
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- 239000007792 gaseous phase Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 22
- 229910002601 GaN Inorganic materials 0.000 description 127
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 127
- 239000000463 material Substances 0.000 description 48
- 230000008569 process Effects 0.000 description 25
- 239000013078 crystal Substances 0.000 description 15
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 11
- 208000037656 Respiratory Sounds Diseases 0.000 description 10
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
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- 238000010586 diagram Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
The invention discloses a kind of high electron mobility transistor epitaxial wafers and preparation method thereof, belong to high electron mobility transistor field.The high electron mobility transistor epitaxial wafer includes: the buffer layer of substrate and stacked above one another over the substrate, GaN channel layer, AlGaN potential barrier, and GaN cap, the buffer layer includes N layers of the first low temperature AI and stress release layer, the stress release layer is between N layers of first low temperature AI and the GaN channel layer, the stress release layer includes the composite layer of several stackings, the composite layer includes AlN sublayer, AlGaN sublayer and GaN sublayer, the AlGaN sublayer is between the AlN sublayer and the GaN sublayer, in the same composite layer, the AlN sublayer is than the GaN sublayer closer to N layers of first low temperature AI.
Description
Technical field
The present invention relates to high electron mobility transistor field, in particular to a kind of high electron mobility transistor epitaxial wafer
And preparation method thereof.
Background technique
Based on AlGaN (aluminium gallium nitride alloy)/GaN (gallium nitride) heterojunction structure HEMT (High Electron Mobility
Transistor, high electron mobility transistor) there is high current density, disruptive critical voltage and electron mobility, micro-
Wave power and high-temperature electronic devices field have highly important application value.HEMT generally includes chip and on chip
Source electrode, drain and gate.Chip is obtained by epitaxial wafer.The structure of epitaxial wafer generally comprises, and substrate and stacked above one another are on substrate
GaN channel layer, AlGaN potential barrier and GaN cap.
It is raw in high temperature due to, there are biggish thermal mismatching, will lead between Si and GaN when substrate uses Si (silicon) substrate
In temperature-fall period after long GaN material, GaN material will bear very big tensile stress, and the epitaxial wafer generation being prepared will be tight
Weight warpage even generates fine crack, seriously affects GaN device characteristic.
Summary of the invention
The embodiment of the invention provides a kind of high electron mobility transistor epitaxial wafers and preparation method thereof, can reduce Si
Tensile stress between substrate and GaN material improves the crystal quality of electron mobility transistor epitaxial wafer.The technical solution is such as
Under:
In a first aspect, a kind of high electron mobility transistor epitaxial wafer is provided, outside the high electron mobility transistor
Prolonging piece includes:
Buffer layer, GaN channel layer, AlGaN potential barrier and the GaN cap of substrate and stacked above one another over the substrate,
The buffer layer includes N layer of the first low temperature AI and stress release layer, the stress release layer be located at N layers of first low temperature AI and
Between the GaN channel layer, the stress release layer includes the composite layer of several stackings, the composite layer include AlN sublayer,
AlGaN sublayer and GaN sublayer, the AlGaN sublayer are same described compound between the AlN sublayer and the GaN sublayer
In layer, the AlN sublayer is than the GaN sublayer closer to N layers of first low temperature AI.
Optionally, the weight ratio of Al component is 10~30wt% in the AlGaN sublayer.
Optionally, the AlN sublayer with a thickness of 1~5nm, the AlGaN sublayer with a thickness of 2~8nm, the GaN
Sublayer with a thickness of 2~8nm, the quantity of the composite layer is 10~20.
Optionally, the buffer layer further includes N layers of the second low temperature AI, N layers of first low temperature AI be located at the substrate with
Between N layers of second low temperature AI.
Optionally, N layers of first low temperature AI with a thickness of 20~50nm, N layers of second low temperature AI with a thickness of 20
~100nm, the stress release layer with a thickness of 100~300nm.
Second aspect provides a kind of preparation method of high electron mobility transistor epitaxial wafer, which comprises
Substrate is provided；
Buffer layer over the substrate, the buffer layer includes N layers of the first low temperature AI and stress release layer, described to answer
For power releasing layer between N layers of first low temperature AI and the GaN channel layer, the stress release layer includes several stackings
Composite layer, the composite layer include AlN sublayer, AlGaN sublayer and GaN sublayer, and the AlGaN sublayer is located at the AlN sublayer
Between the GaN sublayer, in the same composite layer, the AlN sublayer is than the GaN sublayer closer to first low temperature
AlN layers；
GaN channel layer, AlGaN potential barrier and GaN cap are sequentially deposited on the buffer layer.
Optionally, the buffer layer over the substrate, comprising:
Deposit N layers of first low temperature AI over the substrate using magnetically controlled sputter method, N layers of first low temperature AI
Growth atmosphere is N2, Ar and O2Mixed atmosphere；
The stress release layer is deposited on N layers of first low temperature AI.
It is optionally, described to deposit the stress release layer on N layers of first low temperature AI, comprising:
With NH3It is gallium source and using TMAl as silicon source for nitrogen source, using TMGa or TEGa, sinks on the first low temperature AI N layer
The product stress release layer, wherein when growing the AlN sublayer, for interval time period to be passed through institute at the first time
State NH3, it is passed through the NH every time3Time it is identical and be passed through the NH every time3Time and first time between ratio be 1
~4.
Optionally, the buffer layer further includes N layers of the second low temperature AI, N layers of first low temperature AI be located at the substrate with
Between N layers of second low temperature AI, before depositing the stress release layer on N layers of first low temperature AI, the method is also
Include:
The substrate for depositing N layers of first low temperature AI is placed into the anti-of metallo-organic compound chemical gaseous phase deposition equipment
It answers in room；
TMAl is passed through to the reaction chamber and NH as interval time period is passed through using the second time3, described
N layers of second low temperature AI is grown in one N layers of low temperature AI, wherein is passed through the NH every time3Time it is identical and be passed through every time
The NH3Time and the second time between ratio be 1~5.
Optionally, the growth temperature of N layers of second low temperature AI is 550~750 DEG C, the life of N layers of second low temperature AI
Long pressure is 50~200torr, and the growth temperature of N layers of second low temperature AI is higher than the growth temperature of N layers of first low temperature AI
Degree.
Technical solution provided in an embodiment of the present invention has the benefit that by N layers of the first low temperature AI and GaN ditch
Stress release layer is set between channel layer, and stress release layer is AlN/AlGaN/GaN superlattice structure, due to the lattice constant of AlN
The lattice constant of minimum, GaN is maximum, and the lattice constant of AlGaN is between AlN and GaN, therefore, AlN/AlGaN/GaN single-revolution
In phase structure, lattice constant is gradually increased, and forms pressure, and superlattice structure is conducive to form biggish pressure；And it is raw in extension
In growth process, the lattice constant of substrate, such as the lattice constant of Si substrate or SiC are greater than the lattice constant of GaN, this leads
There are biggish tensile stress in cause epitaxial process；Simultaneously because there are biggish thermal mismatchings between Si and GaN, this be will lead to
In the temperature-fall period after high growth temperature GaN material, GaN material will bear very big tensile stress；It is applied by stress release layer
Plus-pressure, pressure is cancelled out each other with the tensile stress in epitaxial process and in temperature-fall period, to play stress regulation and control
Effect, effectively reduces the tensile stress and warpage in epitaxial process, is conducive to plane stress during subsequently epitaxial growing
Release, reduce the crackle and defect concentration of epitaxial process, the crackle during subsequently epitaxial growing avoided to generate, can
Increase substantially the performance of the GaN epitaxy material prepared on Si base substrate.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of stress release layer provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention；
Fig. 4 is a kind of process of the preparation method of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention
Figure；
Fig. 5 is a kind of process of the preparation method of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention
Figure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Technical solution provided in an embodiment of the present invention for ease of understanding introduces on a si substrate directly growth first
The problem of causing when GaN material, specifically, including following five problems.
The first, (0001) of GaN Wurzite structure and the lattice mismatch of Si (111) substrate of diamond lattic structure is
20.4%, lattice mismatch, which will lead to, generates a large amount of dislocations in GaN material, influences the crystal quality of GaN material.
The second, the thermal mismatching between GaN and Si is up to 56%, and thermal mismatching will lead to after high growth temperature GaN material
In temperature-fall period, GaN material will bear very big tensile stress, and the epitaxial wafer being prepared occurs serious warpage or even generates micro-
Crackle seriously affects GaN device characteristic.
Third, the nitrogen source of GaN material generally use NH3, NH3It is easy to react with Si and form amorphous in substrate surface
The SiN of state influences the growth quality of GaN.
4th, there are very strong chemical reactions between metal Ga and substrate Si, can cause back dissolving to substrate, to destroy lining
Bottom interface it is smooth.
5th, in high growth temperature GaN material, the Si in substrate can diffuse to GaN material, it will influence the growth of GaN
Mode, to destroy crystal quality.
Fig. 1 shows a kind of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention.Referring to Fig. 1, the height
Electron mobility transistor epitaxial wafer include: substrate 1 and the buffer layer being sequentially deposited on substrate 12, GaN channel layer 3,
AlGaN potential barrier 4 and GaN cap 5.Buffer layer 2 includes the first low temperature AI N layer 21 and stress release layer 23.Stress release layer
23 between the first low temperature AI N layer 21 and GaN channel layer 3.Referring to fig. 2, stress release layer 23 includes the compound of several stackings
Layer 230.Composite layer 230 includes AlN sublayer 230a, AlGaN sublayer 230b and GaN sublayer 230c.AlGaN sublayer 230b is located at
Between AlN sublayer 230a and GaN sublayer 230c.In same composite layer 230, AlN sublayer 230a ratio GaN sublayer 230c is closer to
One low temperature AI N layer 21.
By the way that stress release layer, stress release layer AlN/ are arranged between GaN channel layer at N layers of the first low temperature AI
AlGaN/GaN superlattice structure, since the lattice constant of AlN is minimum, the lattice constant of GaN is maximum, and the lattice constant of AlGaN is situated between
Between AlN and GaN, therefore, in AlN/AlGaN/GaN monocycle structure, lattice constant is gradually increased, and forms pressure, and super
Lattice structure is conducive to form biggish pressure；And in epitaxial process, the lattice constant of substrate, such as Si substrate or
The lattice constant of SiC is greater than the lattice constant of GaN, this causes in epitaxial process, and there are biggish tensile stress；Simultaneously
Since there are biggish thermal mismatchings between Si and GaN, this be will lead in the temperature-fall period after high growth temperature GaN material, GaN
Material will bear very big tensile stress；By stress release layer application pressure, in pressure and epitaxial process and cooled down
Tensile stress in journey is cancelled out each other, to play the role of stress regulation and control, effectively reduce tensile stress in epitaxial process and
Warpage is conducive to the release of plane stress during subsequently epitaxial growing, and crackle and the defect for reducing epitaxial process are close
Degree avoids the crackle during subsequently epitaxial growing from generating, can increase substantially the GaN epitaxy material prepared on Si base substrate
Performance.
Wherein, other than Si substrate, substrate 1 can also be SiC (silicon carbide) substrate.
Optionally, referring to Fig. 3, buffer layer 2 further includes the second low temperature AI N layer 22, and the first low temperature AI N layer 21 is located at substrate 1
Between the second low temperature AI N layer 22.
Wherein, the first low temperature AI N layer 21 is used for, and AlN nucleus point is formed on substrate 1, and raw with higher crystalline quality
Long several AlN crystalline substances island；Second low temperature AI N layer 22 is used for, and the lateral growth from each AlN crystalline substance island makes adjacent brilliant island connect, directly
Integrally tend to epitaxial surface smooth.
When substrate uses Si (silicon) substrate, due between Si and GaN there are biggish lattice mismatch, served as a contrast in Si
On bottom when direct growth GaN material, a large amount of dislocation defects can be generated in GaN material, influence the crystal quality of GaN material.It is logical
The buffer layer that AlN material is set between substrate and GaN channel layer is crossed, when substrate is Si substrate and grows GaN material on substrate
When material, since the lattice of AlN is between Si and GaN, buffer layer can alleviate the crystalline substance between Si substrate and GaN material
Lattice mismatch, additionally it is possible to solve there is very strong chemical reaction between the two when metal Ga is directly contacted with substrate Si, it can be to substrate
The problem of causing back dissolving；Therebetween due to AlN material thermal expansion coefficient, buffer layer can also alleviate Si substrate
Thermal mismatching between GaN material improves the crystal quality of GaN material.In the present embodiment, two layers of AlN buffer layer is set, i.e.,
N layers of first N layers of low temperature AI and the second low temperature AI, two layers of AlN buffer layer is for the crystal quality for improving GaN material, also, the
Two N layers of low temperature AIs are mainly to alleviate the lattice mismatch issue of N layers of GaN material and the first low temperature AI, while more one layers grow, and second
The surface that N layers of low temperature AI can reach atomically flating, conducive to the high-quality growth of subsequent GaN material.In addition, the first low temperature
AlN layers of nitrogen source can be made using magnetron sputtering physical deposition methods, not need NH3, to avoid using NH3When as nitrogen source
It is easy to react with Si and form amorphous SiN in substrate surface, improves the crystal quality of GaN material.Moreover, first is low
Warm AlN layers is all made of low-temperature epitaxy with N layers of the second low temperature AI, can diffuse under the high temperature conditions to avoid the Si in substrate slow
It rushes layer surface and destroys the growth quality of GaN material, and then improve crystal quality.
In stress release layer 23, illustratively, the weight ratio of Al component is 10~30wt% in AlGaN sublayer 230b.
Illustratively, AlN sublayer 230a with a thickness of 1~5nm, AlGaN sublayer 230b with a thickness of 2~8nm, GaN
Layer 230c with a thickness of 2~8nm, the quantity of composite layer 230 is 10~20.
Illustratively, the first low temperature AI N layer 21 with a thickness of 20~50nm, the second low temperature AI N layer 22 with a thickness of 20~
100nm, stress release layer 23 with a thickness of 100~300nm.Preferably, the first low temperature AI N layer 21 with a thickness of 35nm, second
Low temperature AI N layer 22 with a thickness of 60nm, stress release layer 23 with a thickness of 200nm.At this moment, epitaxial growth can be greatly reduced
The crackle and defect concentration of journey.
Wherein, the forbidden bandwidth of GaN material is 3.4eV, disruptive field intensity 3.3MV/cm, forms two with AlGaN material
The mobility of dimensional electron gas, two-dimensional electron gas is greater than 2000cm2/Vs.Illustratively, GaN channel layer 3 with a thickness of 5000
~10000nm, the thickness of AlGaN potential barrier 4 can be 30~100nm.
Illustratively, the weight ratio of Al component can be greater than, be less than or equal to AlGaN sublayer 230b in AlGaN potential barrier 4
The weight ratio of middle Al component.Preferably, the weight ratio of Al component can be greater than Al in AlGaN sublayer 230b in AlGaN potential barrier 4
The weight ratio of component.Specifically, the weight ratio of Al component can be 20~50wt% in AlGaN potential barrier 4.
Wherein, GaN cap 5 is mainly as the electrode of the Ohmic contact of Deep trench termination.Illustratively, GaN cap
5 thickness can be 10~50nm.
Fig. 4 shows a kind of preparation method of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention.Ginseng
See Fig. 4, this method process includes the following steps.
Step 101 provides substrate.
Step 102, on substrate buffer layer.
Wherein, buffer layer includes N layers of the first low temperature AI and stress release layer, and stress release layer is located at N layers of the first low temperature AI
Between GaN channel layer, stress release layer includes the composite layer of several stackings, composite layer include AlN sublayer, AlGaN sublayer and
GaN sublayer, AlGaN sublayer is between AlN sublayer and GaN sublayer, in same composite layer, AlN sublayer ratio GaN sublayer closer to
First N layers of low temperature AI.
Step 103 is sequentially deposited GaN channel layer, AlGaN potential barrier and GaN cap on the buffer layer.
Wherein it is possible to which high electron mobility transistor shown in Fig. 1 or Fig. 3 is prepared using the method shown in Fig. 4
Epitaxial wafer.
Stress release layer, stress release is arranged by N layers in the first low temperature AI in the embodiment of the present invention between GaN channel layer
Layer is AlN/AlGaN/GaN superlattice structure, and since the lattice constant of AlN is minimum, the lattice constant of GaN is maximum, the crystalline substance of AlGaN
Lattice constant is between AlN and GaN, and therefore, in AlN/AlGaN/GaN monocycle structure, lattice constant is gradually increased, and forms pressure
Power, and superlattice structure is conducive to form biggish pressure；And in epitaxial process, the lattice constant of substrate, such as Si lining
The lattice constant of bottom or SiC are greater than the lattice constant of GaN, this causes in epitaxial process, and there are biggish to answer
Power；Simultaneously because there are biggish thermal mismatchings between Si and GaN, this will lead to the cooling after high growth temperature GaN material
Cheng Zhong, GaN material will bear very big tensile stress；Apply pressure by stress release layer, in pressure and epitaxial process, with
And the tensile stress in temperature-fall period is cancelled out each other, to play the role of stress regulation and control, is effectively reduced in epitaxial process
Tensile stress and warpage are conducive to the release of plane stress during subsequently epitaxial growing, reduce the crackle of epitaxial process
And defect concentration, it avoids the crackle during subsequently epitaxial growing from generating, the GaN prepared on Si base substrate can be increased substantially
The performance of epitaxial material.
Fig. 5 shows a kind of preparation method of high electron mobility transistor epitaxial wafer provided in an embodiment of the present invention.It can
High electron mobility transistor epitaxial wafer shown in Fig. 1 or Fig. 3 is prepared using the method shown in Fig. 5.Referring to Fig. 5,
This method process includes the following steps.
Step 201 provides substrate.
Illustratively, substrate can be Si substrate.
Step 202 deposits N layers of the first low temperature AI using magnetically controlled sputter method on substrate.
Wherein, the growth atmosphere of N layers of the first low temperature AI is N2, Ar and O2Mixed atmosphere.At this moment, since nitrogen source can adopt
Use N2, do not need NH3, to avoid using NH3It is easy to react with Si and form amorphous state in substrate surface when as nitrogen source
SiN, improve the crystal quality of GaN material.
Illustratively, the growth temperature of N layers of the first low temperature AI is 500~700 DEG C, and growth pressure is 3~10mbar.
Specifically, step 202 includes: that substrate is placed into the reaction chamber of Pvd equipment, in reaction chamber
N2, Ar and O2Mixed atmosphere, temperature be 500~700 DEG C, when pressure is 3~10mbar, using the side of Magnetron Sputtered Al target
Face deposits N layers of the first low temperature AI to formula on a si substrate.Wherein, sputtering time can be set according to N layers of the first low temperature AI of thickness,
The thickness of first N layers of low temperature AI can be 20~100nm.
Step 203, to deposit second on the first low temperature AI N layer using metallo-organic compound chemical gaseous phase deposition method low
It is AlN layers warm.
Step 203 includes the following steps.
The substrate for depositing N layers of the first low temperature AI is placed into MOCVD (Metal-organic Chemical by the first step
Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) equipment (model can be Veeco K465i or C4)
Reaction chamber in.
Second step makes annealing treatment substrate.
Illustratively, annealing mode includes: in the reaction chamber of MOCVD device for hydrogen (as carrier gas) atmosphere
Under, high-temperature process substrate 5-6min.Wherein, reaction chamber temperature is 1000~1100 DEG C, and chamber pressure is controlled in 200-
500torr。
It should be noted that N layers of the second low temperature AI and subsequent stress release layer, GaN channel layer in epitaxial layer,
AlGaN potential barrier and GaN cap can be grown using MOCVD method.The temperature and pressure controlled in growth course is real
Refer to the indoor temperature and pressure of the reaction of MOCVD device on border.Specifically, in MOCVD method, using high-purity N H3As N
Source, trimethyl gallium (TMGa) and triethyl-gallium (TEGa) are used as gallium source, and trimethyl aluminium (TMAl) is used as silicon source.
Third step is passed through TMAl to reaction chamber and as interval time period is passed through NH using the second time3, first
N layers of two low temperature AI of growth regulation on low temperature AI N layer.
It is prepared using sputter deposition due to N layers of the first low temperature AI, mainly by negatively charged nitrogen-atoms and positively charged
Al atom, which is combined, generates AlN material, therefore, does not deposit the problem of AlN material lateral transfer is grown.And N layers of the second low temperature AI
It is generated using chemical vapour deposition technique, there are problems that AlN material lateral transfer growth.But AlN material lateral transfer itself
Rate ability is poor, therefore N layers of the second low temperature AI use NH3Pulse is passed through, and is increased the time that the source Al is passed through, can be effectively improved AlN
Ability extending transversely, improve the crystal quality of AlN film in N layer of the second low temperature AI, the crystal matter of final raising GaN epitaxy
Amount, can increase substantially the antistatic effect of the gallium nitride epitaxial materials prepared in silicon base, improve the reliability of device.
Wherein, in third step, it is passed through NH every time3Time it is identical and be passed through NH every time3Time and the second time between
Ratio be 1~5.Illustratively, it is passed through NH every time3Time and the second time between ratio be 1,2,3,4 or 5.When every
It is secondary to be passed through NH3Time and the second time between ratio when being 1, it is meant that logical NH3Time and obstructed NH3Time scale is 1:
1；NH is passed through when each3Time and the second time between ratio when being 2, it is meant that logical NH3Time and obstructed NH3Time ratio
Example is 2:1.Preferably, it is passed through NH every time3Time and the second time between ratio be 3, i.e., logical NH3Time and obstructed NH3When
Between ratio be 3:1.Logical NH3Time and obstructed NH3When time scale is 3:1, the crystal quality of the second N layers of low temperature AI is best.
Illustratively, the growth temperature of N layers of the second low temperature AI is 550~750 DEG C, the growth pressure of the second N layers of low temperature AI
For 50~200torr.
Preferably, the growth temperature of N layers of the second low temperature AI is higher than the growth temperature of N layers of the first low temperature AI.
Specifically, third step includes: the reaction chamber of MOCVD device is nitrogen atmosphere, temperature is 550 DEG C~750 DEG C, anti-
Chamber pressure is answered to be passed through TMAl as group III source, NH under conditions of 50torr-200torr3As group V source, the V/III ratio is taken to be
50~1000, on N layers of the first low temperature AI, grow N layers of the second low temperature AI of 20~50nm.Wherein, N layers of two low temperature AI of growth regulation
Shi Caiyong TMAl is constant to be passed through reaction chamber, NH3Pulse mode is passed through the mode of reaction chamber.Illustratively, N layers of the second low temperature AI is adopted
It is grown with 10~30 dutycycle modes.
Step 204, in N layers of deposition stress releasing layer of the second low temperature AI.
Wherein, stress release layer is located at N layers of the second low temperature AI between GaN channel layer, and stress release layer includes several layers
Folded composite layer, composite layer include AlN sublayer, AlGaN sublayer and GaN sublayer, and AlGaN sublayer is located at AlN sublayer and GaN sublayer
Between, in same composite layer, AlN sublayer ratio GaN sublayer is closer to N layers of the second low temperature AI.
The growth pattern of stress release layer includes: with NH3It is gallium source and using TMAl as aluminium for nitrogen source, using TMGa or TEGa
Source, the deposition stress releasing layer on the second low temperature AI N layer.
Wherein, in growing AIN sublayer, to be passed through NH at the first time for interval time period3, it is passed through NH every time3's
Time is identical and is passed through NH every time3Time and first time between ratio be 1~4.Due to MOCVD method growing AIN
When, AlN material lateral transfer rate ability itself is poor, therefore AlN sublayer also uses NH3Pulsed growth, NH3Pulsed growth can have
Effect improves the ability extending transversely of AlN, improves the crystal quality of AlN film in AlN sublayer, the final crystal for improving GaN epitaxy
Quality can increase substantially the antistatic effect of the gallium nitride epitaxial materials prepared in silicon base, improve the reliability of device.
Illustratively, in growing AIN sublayer, it is passed through NH every time3Time and the second time between ratio be 1,2,3 or 4.When
It is passed through NH every time3Time and the second time between ratio when being 1, it is meant that logical NH3Time and obstructed NH3Time scale is
1:1；NH is passed through when each3Time and the second time between ratio when being 2, it is meant that logical NH3Time and obstructed NH3Time
Ratio is 2:1.Preferably, it is passed through NH every time3Time and the second time between ratio be 3, i.e., logical NH3Time and obstructed NH3
Time scale is 3:1.Logical NH3Time and obstructed NH3When time scale is 3:1, the crystal quality of AlN sublayer is best.
Illustratively, the growth temperature of stress release layer be 1050~1100 DEG C, growth pressure be 75~200torr.
Specifically, step 204 include: the mixed atmosphere of hydrogen and nitrogen, temperature be 1050 DEG C~1100 DEG C, reaction chamber
Under conditions of pressure is 75torr-200torr, TMAl, TMGa are passed through as group III source, NH3As group V source, V/III ratio is taken
It is 100~4000, grows the stress release layer of 10-20 period AlN/AlGaN/GaN composite layer.Wherein, AlN sublayer also uses
NH3Pulse mode growth, TMAl is constant to be passed through reaction chamber, NH3Pulse mode is passed through reaction chamber.
Step 205 deposits GaN channel layer on stress release layer.
Specifically, step 205 includes: in nitrogen/hydrogen atmosphere, 1000 DEG C of temperature~1200 DEG C, chamber pressure
Under conditions of 100torr-500torr, TMGa is passed through as group III source, NH3As group V source, take V/III ratio be 5000~
10000, grow GaN channel layer, GaN channel layer with a thickness of 5000~10000nm.
Step 206 deposits AlGaN potential barrier on GaN channel layer.
Specifically, step 206 includes: in hydrogen atmosphere, 950 DEG C~1000 DEG C of temperature, chamber pressure 100torr-
Under conditions of 200torr, TMGa, TMAl are passed through as group III source, NH3As group V source, taking V/III ratio is 5000~10000,
Grow AlGaN potential barrier, AlGaN potential barrier with a thickness of 30~100nm, the weight ratio of Al component is 20 in AlGaN potential barrier
~50wt%.
Step 207 deposits GaN cap in AlGaN potential barrier.
Specifically, step 207 includes: in nitrogen/hydrogen atmosphere, 1000 DEG C of temperature~1200 DEG C, chamber pressure
Under conditions of 100torr-500torr, TMGa is passed through as group III source, NH3As group V source, take V/III ratio be 5000~
10000, grow GaN cap, GaN cap with a thickness of 10~50nm.
Illustratively, after epitaxial growth, the reaction room temperature of MOCVD device is reduced, is moved back in nitrogen atmosphere
Fire processing, annealing temperature section are 650~800 DEG C, make annealing treatment 5 to 15 minutes, are down to room temperature, complete epitaxial growth.
Stress release layer, stress release is arranged by N layers in the first low temperature AI in the embodiment of the present invention between GaN channel layer
Layer is AlN/AlGaN/GaN superlattice structure, and since the lattice constant of AlN is minimum, the lattice constant of GaN is maximum, the crystalline substance of AlGaN
Lattice constant is between AlN and GaN, and therefore, in AlN/AlGaN/GaN monocycle structure, lattice constant is gradually increased, and forms pressure
Power, and superlattice structure is conducive to form biggish pressure；And in epitaxial process, the lattice constant of substrate, such as Si lining
The lattice constant of bottom or SiC are greater than the lattice constant of GaN, this causes in epitaxial process, and there are biggish to answer
Power；Simultaneously because there are biggish thermal mismatchings between Si and GaN, this will lead to the cooling after high growth temperature GaN material
Cheng Zhong, GaN material will bear very big tensile stress；Apply pressure by stress release layer, in pressure and epitaxial process, with
And the tensile stress in temperature-fall period is cancelled out each other, to play the role of stress regulation and control, is effectively reduced in epitaxial process
Tensile stress and warpage are conducive to the release of plane stress during subsequently epitaxial growing, reduce the crackle of epitaxial process
And defect concentration, it avoids the crackle during subsequently epitaxial growing from generating, the GaN prepared on Si base substrate can be increased substantially
The performance of epitaxial material.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of high electron mobility transistor epitaxial wafer, which is characterized in that the high electron mobility transistor epitaxial wafer packet
It includes:
Buffer layer, GaN channel layer, AlGaN potential barrier and the GaN cap of substrate and stacked above one another over the substrate, it is described
Buffer layer includes N layers of the first low temperature AI and stress release layer, the stress release layer be located at N layers of first low temperature AI with it is described
Between GaN channel layer, the stress release layer includes the composite layer of several stackings, and the composite layer includes AlN sublayer, AlGaN
Sublayer and GaN sublayer, the AlGaN sublayer is between the AlN sublayer and the GaN sublayer, in the same composite layer,
The AlN sublayer is than the GaN sublayer closer to N layers of first low temperature AI.
2. epitaxial wafer according to claim 1, which is characterized in that the weight ratio of Al component is 10 in the AlGaN sublayer
~30wt%.
3. epitaxial wafer according to claim 1, which is characterized in that the AlN sublayer with a thickness of 1~5nm, it is described
AlGaN sublayer with a thickness of 2~8nm, the GaN sublayer with a thickness of 2~8nm, the quantity of the composite layer is 10~20.
4. epitaxial wafer according to claim 1, which is characterized in that the buffer layer further includes N layers of the second low temperature AI, described
First N layers of low temperature AI is between N layers of the substrate and second low temperature AI.
5. epitaxial wafer according to claim 4, which is characterized in that N layers of first low temperature AI with a thickness of 20~50nm,
N layers of second low temperature AI with a thickness of 20~100nm, the stress release layer with a thickness of 100~300nm.
6. a kind of preparation method of high electron mobility transistor epitaxial wafer, which is characterized in that the described method includes:
Substrate is provided；
Buffer layer over the substrate, the buffer layer include N layers of the first low temperature AI and stress release layer, and the stress is released
Layer is put between N layers of first low temperature AI and the GaN channel layer, the stress release layer includes the compound of several stackings
Layer, the composite layer includes AlN sublayer, AlGaN sublayer and GaN sublayer, and the AlGaN sublayer is located at the AlN sublayer and institute
It states between GaN sublayer, in the same composite layer, the AlN sublayer is than the GaN sublayer closer to the first low temperature AI N
Layer；
GaN channel layer, AlGaN potential barrier and GaN cap are sequentially deposited on the buffer layer.
7. according to the method described in claim 6, it is characterized in that, the buffer layer over the substrate, comprising:
Deposit N layers of first low temperature AI, the growth of N layers of first low temperature AI over the substrate using magnetically controlled sputter method
Atmosphere is N2, Ar and O2Mixed atmosphere；
The stress release layer is deposited on N layers of first low temperature AI.
8. the method according to the description of claim 7 is characterized in that described answer described in deposition on the first low temperature AI N layer
Power releasing layer, comprising:
With NH3It is gallium source and using TMAl as silicon source for nitrogen source, using TMGa or TEGa, deposits institute on N layers of first low temperature AI
State stress release layer, wherein described to be passed through at the first time for interval time period when growing the AlN sublayer
NH3, it is passed through the NH every time3Time it is identical and be passed through the NH every time3Time and first time between ratio be 1~
4。
9. the method according to the description of claim 7 is characterized in that the buffer layer further includes N layers of the second low temperature AI, described
One N layers of low temperature AI is between N layers of the substrate and second low temperature AI, on the first low temperature AI N layer described in deposition
Before stress release layer, the method also includes:
The substrate for depositing N layers of first low temperature AI is placed into the reaction chamber of metallo-organic compound chemical gaseous phase deposition equipment
In；
TMAl is passed through to the reaction chamber and NH as interval time period is passed through using the second time3, in first low temperature
N layers of second low temperature AI is grown on AlN layers, wherein be passed through the NH every time3Time it is identical and be passed through the NH every time3
Time and the second time between ratio be 1~5.
10. according to the method described in claim 9, it is characterized in that, the growth temperature of N layers of second low temperature AI be 550~
750 DEG C, the growth pressure of N layers of second low temperature AI is 50~200torr, and the growth temperature of N layers of second low temperature AI is high
In N layers of growth temperature of first low temperature AI.
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