CN110034098A

CN110034098A - Semiconductor structure and forming method thereof

Info

Publication number: CN110034098A
Application number: CN201810029861.0A
Authority: CN
Inventors: 舒强
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2019-07-19
Anticipated expiration: 2038-01-12
Also published as: CN110034098B

Abstract

A kind of semiconductor structure and forming method thereof, method includes: offer substrate, and the substrate includes device side, and the device side includes device region and mark zone；The first device architecture, the second device architecture are formed in the device region, and mark structure is formed in the mark zone, the mark structure includes the first rotation center, the mark structure is around perpendicular to the device side and after the straight line of first rotation center rotates first angle, it is formed by structure to be overlapped with the mark structure, the first angle is greater than zero and is less than or equal to 180 degree；Patterned first graph layer is formed on the device region, and forms test badge in the mark zone.The forming method can improve the performance of semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical field

The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.

Background technique

In existing semiconductor fabrication process, it usually needs form figure on stratified film, have centainly to form The semiconductor devices of function.There is certain aligned relationship between the figure of different film layers, be usually taken on wafer and form set The method of fiducial mark note, is realized by the register mark and is aligned.

Conventionally, as in photoetching process the factors such as wafer offset vector or focusing accuracy influence, light can be made Photoresist during exposure, the figure after leading to exposure shift vector, rotation, scaling or it is orthogonal etc. the problem of. Therefore, it during forming semiconductor structure, needs using photoetching alignment mark to being formed in same layer photoresist not It is measured with the exposure error between cellular zone, to guarantee alignment precision.

However, the forming method of the semiconductor structure of the prior art is more complex.

Summary of the invention

Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can simplify semiconductor structure Forming method.

To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described Substrate includes device side, and the device side includes device region and mark zone；The first device architecture, second are formed in the device region Device architecture, and mark structure is formed in the mark zone, the mark structure includes the first rotation center, the mark structure Around perpendicular to the device side and by the straight line of first rotation center rotate first angle after, be formed by structure with The mark structure is overlapped, and the first angle is greater than zero and is less than or equal to 180 degree, and the mark structure includes multiple labels Portion, multiple labeling sections are uniformly distributed around first rotation center, and the labeling section includes branch's group, and branch's group is in institute Stating projecting figure in device side is bar shaped, and branch's group includes the first branch and the second branch, first branch and the Two branches are parallel to projection of the branch's group in the device side in the orientation of the projecting figure in the device side The extending direction of figure forms first branch during forming first device architecture, is forming described second During device architecture, second label is formed；It is formed after the mark structure, and is forming first graph layer During in the mark zone form test badge, form the test during forming first graph layer and mark Note, the test badge the projecting figure center of the device side relative to first rotation center device side projection With the first offset vector.

Optionally, in each labeling section branch's group number be it is multiple, each branch's group is arranged in parallel.

Optionally, the number of branch's group is 5~15；The distance between adjacent branch's group center be 0.9 μm~ 1.1μm；The width of branch's group is 0.45 μm~0.55 μm.

Optionally, the number of each branch's group is one, and branch's group is rectangle, a length of 18 μm of branch's group~ 22μm；The width of branch's group is 0.9 μm~11 μm.

Optionally, first branch is rectangle, and second branch is rectangle, in first branch and the second branch Adjacent edge lengths are equal.

Optionally, it is formed before first graph layer and the test badge, further includes: form the in the device region Four device structure；Each branch's group further include: third branch, the third branch of each branch's group is for marking the four device knot Structure；The orientation of first branch, the projecting figure of the second branch and third branch in device side is parallel to the branch The extending direction of projecting figure of portion's group in device side.

Optionally, the number of third branch described in single branch's group is 1~3.

Optionally, first device architecture is located in the device region substrate, and first branch is located at the substrate In；Or first device architecture is located on the substrate, first branch is located on the substrate；Second device Structure is located in the device region substrate, and second branch is located in the substrate；Or second device architecture is located at On the substrate, second branch is located on the substrate.

Optionally, the distance at the top of first branch to the device side, which is equal at the top of second branch, arrives the device The distance in part face.

Optionally, first branch is located in the mark zone substrate, and second branch is located at mark zone lining In bottom；Alternatively, being formed before the mark structure, further includes: form the first functional layer over the substrate；First branch For the first opening in first functional layer；Second branch is the second opening in first functional layer.

Optionally, the line of the labeling section center and first rotation center is perpendicular to branch's group extension side To；Alternatively, the line of the labeling section center and first rotation center is parallel to branch's group extending direction；Alternatively, The line and branch's group extending direction of the labeling section center and first rotation center have acute angle.

Optionally, the test badge includes the second rotation center, the test badge around perpendicular to the device side and After the straight line of second rotation center rotates second angle, it is formed by structure and is overlapped with the test badge, it is described Second angle is greater than zero and is less than or equal to 180 degree, and the test badge includes multiple test departments, and the test department is around described second Rotation center is uniformly distributed, and each test department includes one or more test branches.

Optionally, the number of labeling section is equal in the number with single marking structure of test department in single test badge, respectively Test department is corresponded with each labeling section respectively；The number and single marking Bu Zhong branch group of branch are tested in single test department Number is equal, and it is corresponding with each branch's group respectively that branch is respectively tested in mutual corresponding test department and labeling section；The test branch Extending direction for bar shaped, the test branch is parallel to the extending direction of corresponding branch's group.

Optionally, it is formed after the test badge and first graph layer, further includes: on the device region substrate Patterned first graph layer is formed, and forms test badge on the mark zone substrate；Detect the test badge center With first rotation center in the first offset vector on the direction for being parallel to the device side；According to first offset Vector obtains the second offset vector of first graph layer；Remove first graph layer and test badge；Remove described After one graph layer and test badge, the first graph layer is formed on the device region substrate according to second offset vector； Using the second graph layer as exposure mask, third device architecture is formed in the device region；It is formed after the third device architecture, Remove the second graph layer.

Optionally, the second functional layer is formed on the functional areas and device region substrate；First graph layer, the second figure Shape layer and first label are located in second functional layer；The step of forming the third device architecture includes: with described Second graph layer is that exposure mask is processed second functional layer, and third device junction is formed on the device region substrate Structure；Alternatively, it is exposure mask to the device region substrate that the step of forming the third device architecture, which includes: using the second graph layer, It is processed, forms third device architecture in the device region substrate.

Optionally, the technique of the working process includes: etching technics or ion implantation technology.

Optionally, the number of the mark structure is greater than or equal to three；At least there are three labels in multiple mark structures First rotation center of structure is not conllinear.

Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include device side, the device Part face includes device region and mark zone；Positioned at the first device architecture and the second device architecture of the device region；Positioned at the mark Remember that the mark structure in area, the mark structure include the first rotation center, the mark structure bypasses first rotation center And be overlapped perpendicular to the straight line of device side rotation first angle with itself, the first angle is greater than zero and is less than or equal to 180 Degree, the mark structure includes multiple labeling sections, and the labeling section includes branch's group, and branch's group is in the device side Projecting figure is bar shaped, and each branch's group includes the first branch and the second branch, and first branch and the second branch are in the device The orientation of projecting figure on part face is parallel to the extending direction of projecting figure of the branch's group in the device side, First branch of each branch's group is for marking first device architecture, and the second branch of each branch's group is for marking described second Device architecture；Test badge positioned at the substrate mark zone, the test badge is at the projecting figure center of the device side Projection relative to first rotation center in device side has the first offset vector；Positioned at the first of the substrate devices area Graph layer.

Optionally, further includes: positioned at the four device structure of the device region；Each branch's group further include: third branch, respectively The third branch of branch's group is for marking the four device structure；First branch, the second branch and third branch are in institute The orientation for stating the projecting figure in device side is parallel to the extension of projecting figure of the branch's group in the device side Direction.

Compared with prior art, technical solution of the present invention has the advantage that

In the forming method for the semiconductor structure that technical solution of the present invention provides, formed the first graph layer and test badge it Before, mark structure is formed in the mark zone.The first all branches is for marking first device in the mark structure Structure, the second all branches is for marking second device architecture in the mark structure, due to the mark structure packet The first branch and the second branch are included, then the first rotation center of the mark structure can mark first device architecture and The position of two device architectures.Therefore, it by measuring offset vector of the test badge relative to the first rotation center, can obtain Take first graph layer relative to the combined information of the first device architecture and the second device architecture offset vector, so as to letter Change the method for making the third device architecture be aligned with the first device architecture, and be aligned with the second device architecture, and then being capable of letter Change the forming method of semiconductor structure.

Further, the distance at the top of first branch to the device side, which is equal at the top of second branch, arrives the device The distance in part face.During forming the second graph layer, need by detection test badge and the mark structure it Between offset vector.It is equal at the top of second branch at the top of first branch to the distance of the device side and arrives the device The distance in face does not have semiconductor material then perpendicular on the direction of the device side between first branch and the second branch Material to be not easy to influence the detection of offset vector between test-object note and the mark structure, and then can be improved detection accuracy.

Detailed description of the invention

Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；

Fig. 4 to Figure 13 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the invention；

Figure 14 to Figure 16 is the structural schematic diagram of each step of another embodiment of forming method of semiconductor structure of the invention；

Figure 17 is the structural schematic diagram of one embodiment of semiconductor structure of the invention；

Figure 18 is the structural schematic diagram of another embodiment of semiconductor structure of the invention.

Specific embodiment

As stated in the background art, the alignment precision for the semiconductor structure that the prior art is formed is lower.

Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure.

Referring to FIG. 1, providing substrate 100, the substrate 100 includes device region B and mark zone A；It is served as a contrast in the device region B The first active area 101 is formed in bottom 100, and forms the first label 11 in the mark zone A substrate, and first label 11 is used In label first active area 101；The second active area 102 is formed in the device region B substrate 100, and in the label The second label 12 is formed in area's A substrate 100, second label is for marking second active area 102.

Please refer to Fig. 2 and Fig. 3, Fig. 3 be Fig. 2 along cutting line C-C ' shape on the device region B and mark zone A substrate 100 At grid layer 110；Photoresist layer is formed on the device region B and mark zone A grid layer 110；The photoresist layer is exposed Processing, forms patterned photoresist 111, and the shape on the mark zone A grid layer on the device region B grid layer 110 At third label 20.

It is subsequent that the grid layer 110 is performed etching for exposure mask with the photoresist 111, form gate structure.

Wherein, the third label 20 is formed with the photoresist 111 by same exposure-processed, the photoresist 111 As the exposure mask for forming gate structure, therefore, the third label 20 can be used in marking the position of the gate structure, pass through The positional relationship for detecting the third label 20 and the first label 11 can obtain the gate structure and the first active area 101 Between positional relationship；By detecting the positional relationship between the third label 20 and the second label 12, can obtain described Positional relationship between gate structure and the second active area 102, so as to reduce the offset vector of gate structure.

Before being performed etching to the grid layer 110, the forming method further include: detect in the third label 20 First offset vector of the heart relative to the center of first label 11；Detect the center relatively described of the third label 20 Second offset vector at the center of two labels 12；The third mark is obtained according to first offset vector and the second offset vector The third offset vector of note 20；The position of the photoresist 111 is adjusted according to the third offset vector.It can be seen that described Forming method needs to measure the first offset vector and the second offset vector, could obtain the third offset vector, Cause the forming method of the semiconductor structure more complex.

To solve the above-mentioned problems, the present invention provides a kind of forming method of semiconductor structure, comprising: in the device region The first device architecture, the second device architecture are formed, and forms mark structure in the mark zone, the mark structure includes first Rotation center, the mark structure rotate first angle around first rotation center and perpendicular to the shaft of the device side It is overlapped with itself.The forming method can improve the performance of formed semiconductor structure.

To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Fig. 4 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the invention.

Referring to FIG. 4, providing substrate 200, the substrate 200 includes device side, and the device side includes device region N and mark Remember area M.

The material of the substrate 200 is silicon, germanium, SiGe, silicon-on-insulator, germanium on insulator or sige-on-insulator etc. half Conductor structure.

It is subsequent to form the first device architecture and the second device architecture in the device region N, and formed and marked in the mark zone M Remember structure, the mark structure includes the first rotation center, and the mark structure is around perpendicular to described in the device side and process After the straight line rotation first angle of first rotation center, it is formed by structure and is overlapped with the mark structure, the first angle It is less than or equal to 180 degree greater than zero, the mark structure includes multiple labeling sections, and multiple labeling sections are in first rotation The heart is uniformly distributed, and the labeling section includes branch's group, projecting figure of the branch's group in the device side be bar shaped, each Portion's group includes the first branch and the second branch, the row of the projecting figure of first branch and the second branch in the device side Column direction is parallel to the extending direction of projecting figure of the branch's group in the device side, is forming first device junction First branch is formed during structure, during forming second device architecture, forms second label.

In the present embodiment, the step of forming first device architecture, the second device architecture and mark structure such as Fig. 5 are to scheming Shown in 8.

Fig. 5 and Fig. 6 are please referred to, Fig. 6 is the top view of Fig. 5, and Fig. 5 is sectional view of the Fig. 6 along cutting line 1-2, and Fig. 5 is to scheme Subsequent step schematic diagram on the basis of 4 forms first device architecture 201 in the 200 device region N of substrate, and described 200 mark zone M of substrate forms the first branch 211.

In the present embodiment, first device architecture 201 is used as the active area of semiconductor structure.First device architecture 201 are located in the device region N substrate 200.In other embodiments, first device architecture is used as the grid of semiconductor structure Pole, first device architecture are located on the substrate.

In the present embodiment, the first branch 211 in multiple labeling sections constitutes the first label.First label is used for Mark the position of first device architecture 201.

If the number of the labeling section in the mark structure is very few, it is unfavorable in the rotation for determining the mark structure The heart；If the number of the labeling section in the mark structure is excessive, it is easy to increase technology difficulty.The label in mark structure The number in portion is 3~12.

Specifically, the number of the labeling section in the mark structure is four, the first beans in the present embodiment It is 90 degree.Four labeling sections are centrosymmetric distribution.In other embodiments, the number of the labeling section in mark structure is Other values, such as 3,6,8 or 12.

In the present embodiment, the number of the first branch 211 is one in each labeling section.In other embodiments, each labeling section Number can be multiple.

In the present embodiment, first branch 211 is rectangle.In other embodiments, first branch can be Square.

If the length for being wider than big or described first branch 211 of first branch 211 is excessive, it is easily reduced integrated Degree；If the length for being wider than small or described first branch 211 of first branch 211 is too small, it is easy to increase subsequent measurement the The difficulty of one offset vector.Specifically, in the present embodiment, the width of first branch 211 is 0.9 μm~11 μm, described the The length of one branch 211 is 4.5 μm~5.5 μm.

In the present embodiment, described first labeled as the opening being located in the substrate 200.In other embodiments, described First label can also be for positioned at the protrusion of the substrate surface.

The step of forming first device architecture 201 and the first label includes: to be formed graphically on the substrate 200 The first mask layer, first mask layer exposes part of devices area N device face and part mark zone M device side；With institute Stating the first mask layer is that exposure mask carries out the first ion implanting to the device region N substrate 200, and the is injected in the substrate 200 One ion forms the first device architecture 201；The is carried out to the second mark zone M substrate using first mask layer as exposure mask One etching, forms the first branch 211 in the device region N substrate 200.

The step of forming the mask layer includes: that the first original mask layer is formed on the substrate 200；Described first Patterned first photoresist is formed on original mask layer；It is exposure mask to the first original mask layer using first photoresist It performs etching, forms the first mask layer.

Before first ion implanting, further includes: the first graphic films are formed on the mark zone M substrate 200, it is described First ion implanting is also using first graphic films as exposure mask；After first ion implanting, first graphic films are removed.

Before first etching, further includes: the formation second graph film in the device region N substrate 200, described first Etching is also using the second graph film as exposure mask；After first etching, the second graph film is removed.

In the present embodiment, the technique of first etching includes dry etch process.Dry etch process has good Line width control action can accurately control the size of figure in first mask layer.

First ion implanting in substrate 200 for injecting the first ion, to increase the conduction of the substrate 200 Performance.In the present embodiment, first ion is P-type ion, such as: boron ion or BF₂ ⁺Ion；Alternatively, first ion For N-type ion, such as phosphonium ion or arsenic ion.

In other embodiments, the grid is located on the substrate.The step of forming first device architecture include: The first functional layer is formed in the lining；First functional layer is performed etching, forms first in the substrate devices area Device architecture.First device architecture is used to form grid.

Alternatively, first device architecture can also be the first doped layer in the substrate.First doping Source region or the drain region of MOS transistor are used to form in layer；Or first doped layer is used to form the anode or negative of diode Pole；Or first doped layer is used to form base stage, collector or the emitter of triode.First device can also be The first isolation structure in the substrate, first isolation structure for realizing between different zones in device region every From.

In other embodiments, first branch is located on the substrate, and first device architecture is located at the lining On bottom.The step of forming first label and the first device architecture includes: to form the first device layer over the substrate；To institute It states the first device layer to perform etching, the first device layer of part of devices area is removed, and remove the first device layer of part mark zone, in institute It states and forms the first device architecture on device region substrate, and form the first label on the mark zone substrate.

Alternatively, being formed before the mark structure, the forming method further include: form the first function over the substrate Layer；First branch is the first opening in first functional layer.Form the mark structure, the first device architecture Include: to be performed etching to first functional layer with the step of the second device architecture, forms first on the device region substrate Device architecture, and the first branch is formed in first functional layer of mark zone.First functional layer of mark zone is carved Also first functional layer of device region is performed etching during erosion, removes the first functional layer of part of devices area, forms first Device architecture.First device architecture is used as the grid of formed semiconductor structure.

Fig. 7 and Fig. 8 are please referred to, Fig. 8 is the top view of Fig. 7, and Fig. 7 is sectional view of the Fig. 8 along cutting line 3-4, and Fig. 7 is to scheme Subsequent step schematic diagram on the basis of 5 forms the second device architecture 202 in the device region N, and marks in the substrate 200 Area M forms the second branch 212, and the orientation of the first branch 211 and the second branch 212 in same branch's group is parallel to described The extending direction of branch's group.

In the present embodiment, second device architecture 202 is located in the 200 device region N of substrate, second device junction Structure 202 is used as the active area of formed semiconductor structure.In other embodiments, second device architecture may be located on institute It states on substrate.

The step of forming the second device architecture 202 includes: that patterned second photoetching is formed on the substrate 200 Glue, second photoresist expose part of devices area N device face；It is exposure mask to the substrate 200 using second photoresist The second ion implanting is carried out, the second ion is injected in the substrate 200, forms the second device architecture 202.

Second ion implanting in substrate 200 for injecting the second ion, to increase the conduction of the substrate 200 Performance.In the present embodiment, second ion is P-type ion, such as: boron ion or BF₂ ⁺Ion；Alternatively, second ion For N-type ion, such as phosphonium ion or arsenic ion.

In other embodiments, the grid is located on the substrate.The step of forming second device architecture include: The second functional layer is formed over the substrate；Second functional layer is performed etching, forms in the substrate devices area Two device architectures.Second device architecture is used to form grid.

Alternatively, second device architecture can also be the second doped layer in the substrate.Second doping Source region or the drain region of MOS transistor are used to form in layer；Or second doped layer is used to form the anode or negative of diode Pole；Or the doped layer is used to form base stage, collector or the emitter of triode.Second device can also for positioned at The second isolation structure in the substrate, second isolation structure is for realizing the isolation between different zones in device region.

In the present embodiment, second device architecture 202 is contacted with first device architecture 201.In other embodiments In, second device architecture can not be contacted with first device architecture.

In the present embodiment, the second branch 212 in the mark structure in all labeling sections constitutes the second label.Described Two mark the position for marking second device architecture 202.

In the present embodiment, marked and the second mark during forming second device architecture 202 by making described first Capable alignment is remembered into, to control the position of second device architecture 202.

In the present embodiment, the number of the second branch 212 is one in single marking portion.In other embodiments, single mark The number of the second branch can be multiple in note portion.

In the present embodiment, second branch 212 is rectangle.In other embodiments, second branch can be Square.

In the present embodiment, second branch 212 contacts with first branch 211.In other embodiments, described Two branches do not contact with the first branch.

In the present embodiment, the line of the labeling section center and first rotation center extends perpendicular to branch's group Direction.Specifically, in the present embodiment, the single labeling section includes branch's group, then branch's group center and described the The line of one rotation center is perpendicular to branch's group extending direction.

In other embodiments, the line of the labeling section center and first rotation center is parallel to branch's group Extending direction；Alternatively, the labeling section center and the line of first rotation center have with branch's group extending direction Acute angle, such as: it is described label branch center and first rotation center line and branch's group extending direction it Between angle be 45 °, 30 ° or 60 °.

In the present embodiment, the length direction of second branch 212 is parallel to the extending direction of branch's group.The branch Portion's group extends along the sum of the length that the size on direction is the first branch 211 and the second branch 212.

If the length that branch's group extends along oversized or described second branch 212 on direction is excessive, hold Easily reduce integrated level；If branch's group extends along growing for undersized or described second branch 212 on direction It is small, it is easy to increase the difficulty of the first offset vector of subsequent measurement.Specifically, in the present embodiment, branch's group side of extending along Upward size is 9 μm~11 μm.

If the length for being wider than big or described second branch 212 of second branch 212 is excessive, it is easily reduced integrated Degree；If the length for being wider than small or described second branch 212 of second branch 212 is too small, it is easy to increase subsequent measurement the The difficulty of one offset vector.Specifically, in the present embodiment, the width of second branch 212 is 0.9 μm~11 μm, described the The length of two branches 212 is 4.5 μm~5.5 μm.

In the present embodiment, described second labeled as the opening being located in the substrate 200.In other embodiments, described Second label can also be for positioned at the protrusion of the substrate surface.

The step of forming second device architecture 202 and the second label includes: to be formed graphically on the substrate 200 The second mask layer, second mask layer exposes part of devices area N device face and part mark zone M device side；With institute Stating the second mask layer is that exposure mask carries out the second ion implanting to the device region N substrate 200, and the is injected in the substrate 200 Two ions form the second device architecture 202；Second is carried out to the mark zone M substrate 200 using second mask layer as exposure mask Etching, forms the second branch 212 in the device region N substrate 200.

The step of forming the mask layer includes: that the second original mask layer is formed on the substrate 200；Described second Patterned second photoresist is formed on original mask layer；It is exposure mask to the second original mask layer using second photoresist It performs etching, forms the second mask layer.

In the present embodiment, the technique of second etching includes dry etch process.Dry etch process has good Line width control action can accurately control the size of figure in second mask layer.

In other embodiments, second branch is located on the substrate, and second device architecture is located at the lining On bottom.The step of forming second label and the second device architecture includes: to form the second device layer over the substrate；To institute It states the second device layer to perform etching, the second device layer of part of devices area is removed, and remove the second device layer of part mark zone, in institute It states and forms the second device architecture on device region substrate, and form the second label on the mark zone substrate.

Alternatively, being formed before the mark structure, the forming method further include: form the first function over the substrate Layer；Second branch is the second opening in first functional layer.Specifically, forming the second branch and the second device The step of structure includes: to perform etching to first functional layer, forms the second branch in first functional layer of mark zone, And the first functional layer of part of devices area is removed, the second device architecture is formed on the device region substrate.To first function Layer also performs etching first functional layer of device region during performing etching, and removes the first functional layer of part of devices area shape At the second device architecture.Second device architecture is used as the grid of formed semiconductor structure.

In the present embodiment, pushed up to the distance of the device side equal to second branch 212 at the top of first branch 211 Distance of the portion to the device side.It is equal to second branch 212 to the distance of the device side at the top of first branch 211 It then states the first branch 211 and the second branch 212 is located at in semi-conductor layer, then rear to the distance of the device side in top During the first offset vector of continuous measurement, the semiconductor material between first branch 211 and the second branch 212 is not easy Measurement result is influenced, so as to increase measurement accuracy.

The number of the mark structure is greater than or equal to three, and at least there are three the of mark structure in multiple mark structures One rotation center is not conllinear.

The number of the mark structure is greater than or equal to three, and at least there are three the of mark structure in multiple mark structures One rotation center is not conllinear, then the first rotation center of multiple mark structures can determine putting for figure in subsequent second graph layer Greatly, it reduces, rotation and edge are parallel to the upward translation of either described device side.

In other embodiments, it is formed before first graph layer and the test badge, further includes: in the device Area forms four device structure；Each branch's group further include: third branch, the third branch of each branch's group is for marking the described 4th Device architecture；The orientation of first branch, the second branch and third branch is parallel to branch's group in device side The extending direction of projecting figure.The number of third branch described in each branch's group is 1~3.

In the present embodiment, the first angle is 90 °, and the mark structure is right centered on the projecting figure in device side Claim figure.In other embodiments, the first angle is 30 °, 45 °, 60 ° or 120 °.

Referring to FIG. 9, forming the second functional layer 220 on the substrate 200.

Second functional layer 220 is for being subsequently formed third device architecture.

In the present embodiment, the third device architecture being subsequently formed is located on the substrate 200, then is subsequently formed described first Before graph layer and third label, further includes: form the second functional layer 220 on the substrate 200.In other embodiments, The third device architecture may be located in the substrate, and the forming method does not include forming the step of second functional layer Suddenly.

In the present embodiment, the material of second functional layer 220 is polysilicon or metal.

Figure 10 and Figure 11 are please referred to, described Figure 10 is sectional view of the Figure 11 along cutting line 5-6, and Figure 11 is the vertical view of Figure 10 Figure, Figure 10 is subsequent step schematic diagram on the basis of Fig. 8, has ignored functional layer 220 in Figure 11, the shape on the device region N At patterned first graph layer 230, and is formed and surveyed in the mark zone M during forming the first graph layer 230 Test-object note 213, the test badge 213 is at the projecting figure center of the device side relative to first rotation center in device Part face has the first offset vector.

By making the test badge 213 at the projecting figure center of the device side relative to first rotation center In the first offset vector of device side, it can determine first graph layer 230 to for the first device architecture 201 and the second device The position of part structure 202, so as to make the third device architecture 240 and first device architecture 201 and the second device Structure 202 is aligned, so as to improve the performance of formed semiconductor structure.

It should be noted that the first branch 211 all in the mark structure is for marking first device architecture 201, the second all branches 212 is for marking second device architecture 202 in the mark structure, due to label knot Structure includes the first branch 211 and the second branch 212, then the first rotation center of the mark structure can mark first device The position of part and the second device.Therefore, it by measuring the offset vector of the test structure and the first rotation center, can obtain Combined information of first graph layer 230 relative to 202 offset vector of the first device architecture 201 and the second device architecture, from And can simplify is directed at the third device architecture 240 with the first device architecture 201, and is aligned with the second device architecture 202 Method, and then the forming method of semiconductor structure can be simplified.

In the present embodiment, first graph layer 230 is located on the substrate 200；The test badge 213 is located at described On substrate 200.

It is formed after first graph layer 230 and test badge 213, the forming method further include: detect the survey Examination mark center and first rotation center are in the first offset vector on the direction for being parallel to the device side；According to institute State the second offset vector that the first offset vector obtains the graphic films；Remove first graph layer 230 and test badge；It goes After first graph layer 230 and test badge, according to second offset vector in the device region N substrate 200 Form second graph layer.

In other embodiments, during forming the second graph layer, correction is formed on the mark zone M substrate Test badge, the correction test badge is at the projecting figure center of the device side relative to first rotation center in device The offset vector of the projection in part face is less than the permitted error amount of design requirement.It is formed before second graph layer, further includes repeating The step of forming first graph layer and test surfaces is gradually reduced second offset vector to the second offset vector and is less than Or it is equal to the permitted error amount of design requirement, the first graph layer when second offset vector is less than or equal to preset value For second graph layer, test badge is correction test badge.

The step of forming first graph layer 230 and test badge includes: to form initial graphics on the substrate 200 Film；The first exposure-processed is carried out to the initial graphics film by light shield, removes part mark zone M initial graphics film and part device N initial graphics film in part area forms the first graph layer and test badge.

The test badge 213 is formed with first graph layer 230 by same exposure-processed, the test badge 213 for detecting offset vector of first graph layer 230 relative to the first device architecture and the second device architecture, therefore institute State the position that test badge 213 is capable of the third device architecture of mark successive formation.

In the present embodiment, the test badge 213 is remaining on the mark zone M to be located at after the second exposure-processed Initial graphics film.In other embodiments, the third device architecture being subsequently formed is in second functional layer or substrate Third opening, then the test badge be in the mark zone initial graphics layer the 4th opening.

The number of the test badge 213 is identical as the number of mark structure.

In the present embodiment, by the first rotation center of multiple mark structures and corresponding 213 center of test badge it Between multiple first offset vectors, the second offset vector of the first graph layer 230 can be obtained, if second offset vector Greater than the permitted error amount of design requirement, then the method for second graph layer is formed further include: removal first graph layer 230；After removing first graph layer 230, formed in the device region N substrate 200 according to second offset vector Second graph layer.It is wrapped the step of forming second graph layer in the device region N substrate 200 according to second offset vector It includes: forming initial graphics layer on the substrate 200；According to second offset vector, the position of the light shield is adjusted；It adjusts After the position of the light shield, the second exposure-processed is carried out to the initial graphics layer by the light shield, forms second graph Layer and correction test badge.

If second offset vector is less than the permitted error amount of design requirement, first graph layer 230 is For the second graph layer.

The number of the mark structure is more than or equal to 3, passes through the first rotation center and phase of multiple mark structures Multiple first offset vectors between 213 center of test badge are answered, can determine that figure is described along being parallel in the graphic films Translation, rotation, amplification and diminution in device side either direction.Second offset vector includes the translation, rotation, amplification And diminution.

In the present embodiment, the third test badge 213 is similar fitgures with the mark structure.

Specifically, the test badge 213 includes the second rotation center, the test badge 213 is around perpendicular to the device Part face and by the straight line of second rotation center rotate second angle after, be formed by structure and the test badge 213 It is overlapped, the second angle is greater than zero and is less than or equal to 180 degree, and the test badge 213 includes multiple test departments, the test Portion is uniformly distributed around second rotation center, and each test department includes one or more test branches.

The number of the test department is 3~8, specifically, in the present embodiment, test department in the test badge 213 Number be four.

In the present embodiment, the number that branch is tested in each test department is one.

In the present embodiment, the test branch is rectangle.The test branch is identical as the shape and size of branch's group. In other embodiments, the test branch is not identical as the shape and size of branch group.

The number of test department is equal with the number of labeling section in single marking structure in single test badge 213, each to test Portion is corresponded with each labeling section respectively；In mutual corresponding test badge and labeling section, branch is tested in single test department Number is equal with the number of single marking Bu Zhong branch group, and each test branch is corresponding with each branch's group respectively.

The mark zone includes multiple sub- mark zones, and any sub- mark zone is around perpendicular to the device side and mistake label The straight line rotation first angle of district center is overlapped with another sub- mark zone.In the number of the sub- mark zone and the mark structure The number of labeling section is identical.Multiple labeling sections in mark structure are located at the multiple sub- mark zone；In test badge Multiple test departments are located at multiple sub- mark zones；Each test department refers to each labeling section one-to-one correspondence mutual corresponding respectively Labeling section and test position are in same sub- mark zone.

Branch is corresponding with each branch's group respectively refers to for test in mutual corresponding test department and labeling section: mutual corresponding Test branch and branch's group are located at same sub- mark zone.In the present embodiment, the test branch is bar shaped, the test branch Extending direction is parallel to the extending direction of corresponding branch's group.In other embodiments, the extension side of the test branch There is angle to the extension of corresponding branch's group.

In the present embodiment, the second angle is 90 °, and projecting figure of the test in device side is center symmetric graph Shape.In other embodiments, the second angle is 30 °, 45 °, 60 ° or 120 °.

Please refer to Figure 12 and Figure 13, Figure 12 is sectional view of the Figure 13 along cutting line 7-8, Figure 12 be on the basis of Figure 10 after Continuous step schematic diagram forms third device architecture 240 in the device region N using the second graph layer as exposure mask.

In the present embodiment, the third device architecture 240 is used as the grid of transistor.In other embodiments, described One device architecture is the first doped layer, and second device architecture is the second doped layer；Alternatively, first device architecture is position The first active area in the substrate；Second device architecture is used to form the grid on substrate；The third device Part is the third opening in second functional layer, third opening for accommodating plug, the plug for realizing First device and the second device are electrically connected with external circuit.

In the present embodiment, the forming method further include: third label 214 is formed on the 200 mark zone M of substrate, The third label 214 is for marking the third device architecture 240.

It forms third device architecture 240 and the step of third label 214 includes: with the second graph layer 230 and described Correction test badge is that exposure mask performs etching the functional layer, forms the third device architecture 240 and third label 214.

2 and Figure 13 are continued to refer to figure 1, are formed after the third device architecture 240, the second graph layer is removed and are rectified Positive test badge.

The technique for removing the graph layer 230 and correction test badge 213 includes cineration technics.

The forming method further include: formed and cover the substrate, the first device architecture, the second device architecture, third device The dielectric layer of part structure and mark structure；Contact hole is formed in the dielectric layer, the contact hole bottom-exposed goes out described Three device architectures；Device plug is formed in the contact hole.

The device plug is electrically connected for realizing the third device architecture and external circuit.

It during forming the contact hole, is marked by the third, makes the contact hole and the third device Structure alignment.

Figure 14 to Figure 17 is the structural schematic diagram of another embodiment of forming method of semiconductor structure of the present invention.

The something in common of the present embodiment and Fig. 4 to embodiment illustrated in fig. 13 does not repeat herein, the difference is that:

Figure 14 is please referred to, forms the first branch 211 in the mark zone M；The first device architecture is formed in the device region N 201。

In the present embodiment, the labeling section includes multiple branch's groups.The multiple branch's group is along perpendicular to branch's group Extending direction arrangement.

The number of branch's group is 5~15 in each labeling section.Specifically, being propped up in each labeling section in the present embodiment The number of portion's group is 10.

If the distance between adjacent branch's group center is excessive or width of branch's group is excessive, it is easily reduced to be formed The integrated level of semiconductor structure；If the distance between adjacent branch's group center is too small or width of branch's group is too small, it is easy Increase the technology difficulty of the first etching and the second etching.Specifically, the distance between adjacent branch's group is 0.9 μ in the present embodiment M~1.1 μm；The width of branch's group is 0.45 μm~0.55 μm.

In the present embodiment, each first branch, 211 center is conllinear in single marking portion, and each first branch in single marking portion The center that the extended line of 211 lines of centres is marked without described first.In other embodiments, each first branch center The center that the extended line of line is marked by described first.

In the present embodiment, the extension side of the line and branch's group at first mark center and single marking portion center To with acute angle, specifically, the line and first branch at first mark center and single marking portion center Angle between extending direction is 45 °.In other embodiments, the line of first mark center and single marking portion center Angle between the extending direction of first branch is 30 °, 60 ° or other angles；First mark center and single The line at labeling section center is vertical with the extending direction of branch's group；Alternatively, first mark center and single marking portion The line at center is parallel with the extending direction of branch's group.

Figure 15 is please referred to, forms the second branch 212 in the mark zone M；The second device architecture is formed in the device region N 202。

In the present embodiment, second branch 212 be rectangle, first branch 211 be rectangle, described first The longitudinal direction in portion 211 is parallel to the extending direction of branch's group, and the longitudinal direction of second branch 212 is parallel to described The extending direction of branch's group.

The width of second branch 212 is equal with the width of first branch 211.

Second branch 212 is identical as the number of the first branch 211.

In the present embodiment, the shape and size of labeling section Zhong Ge branch group are identical.In other embodiments, the mark The shape or size of Ji Buzhong branch group are not identical.Such as: the size of the long side of branch's group is not identical in the labeling section.

In the present embodiment, the shape and size phase of the shape and size of second branch 212 and first branch 211 Together.In other embodiments, the shape and size for stating the second branch are not identical as the shape and size of first branch.Example Such as, along branch's group extending direction, the size of first branch is less than the size of the second branch or first branch Size be greater than the second branch size.

In the present embodiment, the line and branch's group extension side of the label branch center and first rotation center There is acute angle between.Specifically, the line and the branch of the label branch center and first rotation center Angle between group extending direction is 45 °.

In other embodiments, the label branch center and the line of first rotation center prolong with branch's group The angle stretched between direction can also be 30 ° or 60 °；Alternatively, the line at the labeling section center and first rotation center It is parallel to branch's group extending direction；Alternatively, the line and the branch of the labeling section center and first rotation center Portion's group extending direction has acute angle.

Figure 16 is please referred to, forms patterned first graph layer 230 on the device region N, and in the mark zone M shape At test badge 213, the test badge 213 is for marking first graph layer 230, and the test badge 213 is described The projecting figure center of device side has the first offset vector in device side relative to first rotation center.

In the present embodiment, the number that branch is tested in single test department is identical as the number of single marking Bu Zhong branch group. In other embodiments, the number that branch is tested in single test department is less than the number of single marking Bu Zhong branch group；Alternatively, single The number that branch is tested in a test department is greater than the number of single marking Bu Zhong branch group.

In the present embodiment, the number of the test department is identical as the number of the labeling section.Specifically, single test badge The number of test department is four in 213.Each test department is corresponding with each labeling section respectively；In mutual corresponding test department and labeling section It is corresponding with each branch's group respectively to test branch.

Each test department is corresponding with each labeling section respectively to be referred to: mutual corresponding labeling section and test position are in same sub- mark Remember area.Branch is corresponding with each branch's group respectively refers to: mutual corresponding survey for test in mutual corresponding test department and labeling section Examination branch and branch's group are located at same sub- mark zone, and the center of test branch and branch's group line of centres are parallel to the branch The extending direction of group.

Continue to refer to figure 10 and Figure 11, it includes: substrate 200 that the embodiment of the present invention, which also provides a kind of semiconductor structure, described Substrate 200 includes device side, and the device side includes device region N and mark zone M；

Positioned at the first device architecture 201 and the second device architecture 202 of the device region N；

Positioned at the mark structure of the mark zone M, the mark structure includes the first rotation center, the mark structure around It crosses first rotation center and is overlapped perpendicular to the straight line of device side rotation first angle with itself, the first angle It is less than or equal to 180 degree greater than zero, the mark structure includes multiple labeling sections, and the labeling section includes branch's group, the branch Projecting figure of portion's group in the device side is bar shaped, and branch's group includes the first branch 211 and the second branch 212, institute The orientation for stating the projecting figure of the first branch 211 and the second branch 212 in the device side is parallel to branch's group First branch 211 of the extending direction of the projecting figure in the device side, branch's group of each branch's group is described for marking First device architecture 201, the second branch 212 of each branch's group is for marking second device architecture 202；Positioned at the substrate The test badge of 200 mark zone M, the test badge is at the projecting figure center of the device side relative to first rotation Center has the first offset vector in the projection of device side；Positioned at the first graph layer 230 of the 200 device region N of substrate.

In the present embodiment, pushed up to the distance of the device side equal to second branch 212 at the top of first branch 211 Distance of the portion to the device side.

The forming method of semiconductor structure embodiment as shown in Fig. 4 to Figure 11 in the present embodiment is formed, herein seldom It repeats.

Figure 17 is the structural schematic diagram of one embodiment of semiconductor structure of the present invention.

Please refer to Figure 17, the something in common of semiconductor structure shown in the semiconductor structure and Figure 13 of the present embodiment, herein not It repeats, the difference is that:

The semiconductor structure further include: positioned at the four device structure 303 of the device region N；Each branch's group further include: Third branch 313, the third branch 313 of each branch's group is for marking the four device structure 303；First branch 211, The orientation of the projecting figure of second branch 212 and third branch 313 in the device side is parallel to branch's group and exists The extending direction of projecting figure in the device side.

In the present embodiment, the four device structure 303 is located in the substrate 200.Specifically, in the present embodiment, institute Stating four device structure 303 is the third active area in the substrate 200, and the third active area is for increasing substrate 200 electric conductivity.In other embodiments, the four device structure can also be the third doping in the substrate Area, the third doped region are used to form source region or the drain region of MOS transistor, base stage, collector or the emitter of triode, or The anode and cathode of person's diode.

Correspondingly, branch's group further includes third branch 313, the third branch 313 in each branch's group is for marking institute State four device structure 303.

The four device can also be that the opening or the four device in second functional layer are used for shape At the grid of MOS transistor.

In the present embodiment, the number of the four device is 1~3, such as 2.Correspondingly, described in each branch's group The number of third branch 313 is 1~3.

The center of the projecting figure of the third branch 313, the second branch 212 and the first branch 211 in device side is total Line, the third branch 313, the second branch 212 are parallel with the orientation of projecting figure of first branch 211 in device side In the extending direction of branch's group projecting figure in device side.

In the present embodiment, the third branch 313, the second branch 212 and the first branch 211 are respectively positioned in the substrate.

In the present embodiment, the number of single marking Bu Zhong branch group is one.Single branch's group is in device side The line of centres and branch's group extending direction at the center of projecting figure and projecting figure of the mark structure in device side Vertically.In other embodiments, the center of single projecting figure of the branch's group in device side and the mark structure exist The line of centres of projecting figure in device side and branch's group extending direction have acute angle.

Figure 18 is the structural schematic diagram of another embodiment of semiconductor structure of the present invention.

Please refer to Figure 18, the semiconductor that the forming method of semiconductor structure shown in the present embodiment and Figure 14 to Figure 16 is formed The something in common of structure, this will not be repeated here.The difference is that:

In the present embodiment, the semiconductor structure further include: positioned at the four device structure 303 of the device region N；Each Portion's group further include: third branch 413, the third branch 413 of each branch's group is for marking the four device structure 303；It is described The orientation of the projecting figure of first branch 211, the second branch 212 and third branch 413 in the device side is parallel to The extending direction of projecting figure of the branch's group in the device side.

In the present embodiment, the third branch 413, the second branch 212 and the first branch 211 are respectively positioned on the substrate 200 In.

In the present embodiment, the center of the third branch 413, the second branch 212 and the first branch 211 is conllinear, and described The orientation of three branches 413, the second branch 212 and the first branch 211 is parallel to the extending direction of branch's group.

In the present embodiment, the number of single marking Bu Zhong branch group is multiple.

Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of forming method of semiconductor structure characterized by comprising

Substrate is provided, the substrate includes device side, and the device side includes device region and mark zone；

The first device architecture, the second device architecture are formed in the device region, and forms mark structure in the mark zone, it is described Mark structure includes the first rotation center, and the mark structure is around perpendicular to the device side and by first rotation After the straight line rotation first angle of the heart, it is formed by structure and is overlapped with the mark structure, the first angle is greater than zero and is less than Or it is equal to 180 degree, the mark structure includes multiple labeling sections, and multiple labeling sections are uniformly divided around first rotation center Cloth, the labeling section include branch's group, and projecting figure of the branch's group in the device side is bar shaped, branch's group packet Include the first branch and the second branch, the orientation of the projecting figure of first branch and the second branch in the device side It is parallel to the extending direction of projecting figure of the branch's group in the device side, in the mistake for forming first device architecture First branch is formed in journey, during forming second device architecture, forms second label；

It is formed after the mark structure, forms patterned first graph layer on the device region, and forming described the Test badge is formed in the mark zone during one graph layer, the test badge is in the projecting figure of the device side Projection of the heart relative to first rotation center in device side has the first offset vector.

2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of branch's group in each labeling section To be multiple, each branch's group is arranged in parallel.

3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of branch's group is 5 ~15；The distance between adjacent branch's group center is 0.9 μm~1.1 μm；The width of branch's group is 0.45 μm~0.55 μ m。

4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of each branch's group is one, Branch's group be rectangle, a length of 18 μm~22 μm of branch's group；The width of branch's group is 0.9 μm~11 μm.

5. the forming method of semiconductor structure as described in claim 1, which is characterized in that first branch is rectangle, institute Stating the second branch is rectangle, and first branch is equal with edge lengths adjacent in the second branch.

6. the forming method of semiconductor structure as described in claim 1, which is characterized in that form first graph layer and institute Before stating test badge, further includes: form four device structure in the device region；Each branch's group further include: third branch, respectively The third branch of branch's group is for marking the four device structure；First branch, the second branch and third branch are in device The orientation of projecting figure on part face is parallel to the extending direction of projecting figure of the branch's group in device side.

7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that third branch described in single branch group The number in portion is 1~3.

8. the forming method of semiconductor structure as described in claim 1, which is characterized in that first device architecture is located at institute It states in device region substrate, first branch is located in the substrate；Or first device architecture is located on the substrate, First branch is located on the substrate；

Second device architecture is located in the device region substrate, and second branch is located in the substrate；

Or second device architecture is located on the substrate, second branch is located on the substrate.

9. the forming method of semiconductor structure as described in claim 1, which is characterized in that described at the top of first branch The distance of device side is equal to the distance that the device side is arrived at the top of second branch.

10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that first branch is located at described In mark zone substrate, second branch is located in the mark zone substrate；

Alternatively, being formed before the mark structure, further includes: form the first functional layer over the substrate；

First branch is the first opening in first functional layer；Second branch is positioned at first functional layer In second opening.

11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the labeling section center with it is described The line of first rotation center is perpendicular to branch's group extending direction；Alternatively, the labeling section center and first rotation The line at center is parallel to branch's group extending direction；Alternatively, the company at the labeling section center and first rotation center Line and branch's group extending direction have acute angle.

12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the test badge includes second Rotation center, the test badge is around perpendicular to the device side and by the straight line of second rotation center rotation second It after angle, is formed by structure and is overlapped with the test badge, the second angle is greater than zero and is less than or equal to 180 degree, described Test badge includes multiple test departments, and the test department is uniformly distributed around second rotation center, and each test department includes one Or multiple test branches.

13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that test department in single test badge Number it is equal with the number of labeling section in single marking structure, each test department respectively with each labeling section correspond；It is single to survey The number that branch is tested in examination portion is equal with the number of single marking Bu Zhong branch group, in mutual corresponding test department and labeling section Each test branch is corresponding with each branch's group respectively；The test branch is bar shaped, and the extending direction of the test branch is parallel to The extending direction of corresponding branch's group.

14. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the test badge and institute After stating the first graph layer, further includes: form patterned first graph layer on the device region substrate, and in the label Test badge is formed on area's substrate；It detects the test badge center and first rotation center and is parallel to the device on edge The first offset vector on the direction in face；The second offset arrow of first graph layer is obtained according to first offset vector Amount；Remove first graph layer and test badge；After removing first graph layer and test badge, according to described second Offset vector forms the first graph layer on the device region substrate；Using the second graph layer as exposure mask, in the device region Form third device architecture；It is formed after the third device architecture, removes the second graph layer.

15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that in the functional areas and device region The second functional layer is formed on substrate；First graph layer, second graph layer and first label are located at second function On layer；

The step of forming the third device architecture includes: to carry out using the second graph layer as exposure mask to second functional layer Working process forms third device architecture on the device region substrate；

Alternatively, the step of forming the third device architecture includes: to serve as a contrast using the second graph layer as exposure mask to the device region Bottom is processed, and third device architecture is formed in the device region substrate.

16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the technique packet of the working process It includes: etching technics or ion implantation technology.

17. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of the mark structure is big In or equal to three；The first rotation center in multiple mark structures at least there are three mark structure is not conllinear.

18. a kind of semiconductor structure characterized by comprising

Substrate, the substrate include device side, and the device side includes device region and mark zone；

Positioned at the first device architecture and the second device architecture of the device region；

Mark structure positioned at the mark zone, the mark structure include the first rotation center, and the mark structure bypasses institute It states the first rotation center and is overlapped perpendicular to the straight line of device side rotation first angle with itself, the first angle is greater than Zero is less than or equal to 180 degree, and the mark structure includes multiple labeling sections, and the labeling section includes branch's group, and branch's group exists Projecting figure in the device side is bar shaped, and each branch's group includes the first branch and the second branch, first branch and the Two branches are parallel to projection of the branch's group in the device side in the orientation of the projecting figure in the device side The extending direction of figure, the first branch of each branch's group is for marking first device architecture, the second branch of each branch's group For marking second device architecture；

Test badge positioned at the substrate mark zone, the test badge the projecting figure center of the device side relative to First rotation center has the first offset vector in the projection of device side；

The first graph layer positioned at the substrate devices area.

19. semiconductor structure as claimed in claim 18, which is characterized in that the device side at the top of first branch Distance is equal to the distance that the device side is arrived at the top of second branch.

20. semiconductor structure as claimed in claim 18, which is characterized in that further include: positioned at the 4th device of the device region Part structure；Each branch's group further include: third branch, the third branch of each branch's group is for marking the four device structure；Institute The orientation for stating the projecting figure of the first branch, the second branch and third branch in the device side is parallel to the branch The extending direction of projecting figure of the group in the device side.