JPH05136480A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide manufacturing method for reducing the offset voltage of a magnetic detector device. CONSTITUTION:An N-type epitaxial layer is formed on a P-type substrate 1, and an oxide film is formed on the N-type epitaxial layer 2. Then, the N-type epitaxial layer is arranged as a section in the prescribed range, and a mask 52 is arranged on the oxide film 3 to form optionally an N<+>-type diffused layer 5 film on the epitaxial layer. As a result, a through hole 4 is formed by removing the oxide film. From the through hole formed on the surrounding part of the epitaxial layer in the prescribed range, boron is injected in the N-type epitaxial layer, and is diffused to get to the P-type substrate. Next, another mask is arranged, and the N-type epitaxial layer is coated optionally with a resist film 9 except for the portion around the through hole. A large quantity of N-type impurities are doped into the N-type epitaxial layer 26 from the through hole, and the N<+>-type diffused layer is formed. Then, an aluminum electrode 6 for contacting with the hole is formed in the portion of the through hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, it relates to a method for manufacturing a magnetic detection device.

[0002]

2. Description of the Related Art There are various magnetic detection devices at present. One of them is a Hall element, which can be easily formed on a semiconductor substrate. It has excellent properties such as detection of DC magnetic field.

A conventional method of manufacturing a Hall element will be described with reference to FIGS.

23 and 24 are plan views showing a mask used for manufacturing the present Hall element. A mask 50 shown in FIG. 23 is a mask whose central portion is not patterned, and a mask 51 shown in FIG. 24 is a mask which is patterned so as to cover a region other than a diffusion layer described later.

First, as shown in FIG. 17, an N type epitaxial layer 2 is grown on the surface of a P type substrate 1 in which silicon is doped with P type impurities, and an oxide film 3 is further formed on the entire surface of the N type epitaxial layer 2. Form.

Then, a negative type resist is applied on the entire surface of the oxide film 3, a mask 50 is placed on the resist, and then exposure is performed to render the irradiated portion (photosensitive portion) insoluble. Next, the resist in the non-irradiated portion is removed, and then the oxide film 3 in the portion where the resist is removed is removed by etching.
Further, when the resist of the insoluble portion is removed, it becomes as shown in FIG. The oxide film 3 is thinly formed on the portion where the oxide film 3 is removed, because the surface of the N-type epitaxial layer 2 is oxidized over time to form the thin oxide film 3. Also, in the following steps and the embodiments of the present invention, the oxide films 3 and 11 may be thinly formed in the portions where the oxide films 3 and 11 are removed, but they are appropriately removed as necessary.

Next, P-type impurities are doped into the N-type epitaxial layer 2 from the thin portion of the oxide film 3 by a method such as ion implantation, and thermal diffusion is performed until the P-type substrate 1 is reached. As shown in the range of epitaxial layers 25
Is formed.

Then, the mask 51 is aligned with the semiconductor substrate on which the pattern of the mask 50 is patterned to cover the oxide film 3, and the oxide film 3 in a portion not covered by the mask 51 is removed by photoetching. The through hole 4 is formed. (FIG. 20) Next, as shown in FIG. 21, a large amount of N-type impurities such as phosphorus are injected and diffused from the through hole 4 portion to form an N ⁺ -type diffusion layer 5 on the surface of the N-type epitaxial layer 2.

Finally, the oxide film 3 formed in the through hole 4 portion and a part of the oxide film 3 on the P-type substrate 1 are removed to form contact holes for making contact with each region. The aluminum electrode 6 is formed on the portion to complete the Hall element as shown in FIG.

The operation of this Hall element will be described with reference to FIG.

FIG. 25 is a plan view showing the Hall element shown in FIG. 22, and the aluminum electrode 6 is omitted for ease of viewing. Further, since the manufacturing method described with reference to FIGS. 17 to 22 has been described with reference to the cross-sectional views, the description and illustration of the two N ⁺ type diffusion layers 30 are omitted, but in reality, two sets of N ⁺ type diffusion layers 5 and 3 are formed.
0s are formed facing each other on the surface of the N-type epitaxial layer 2.

When a voltage is applied to the two N ⁺ type diffusion layers 5 and a magnetic field is applied in a direction perpendicular to the plane of the drawing, the electrons flowing in the N type epitaxial layer 2 receive Lorentz force and proceed in the direction perpendicular to the flow. The force to try is generated. As a result, two N
A potential difference proportional to the applied magnetic field is generated between the ⁺ type layers 30,
A magnetic field can be detected.

Although the above description has been made on the Hall element using the N-type epitaxial layer 2, the Hall element can also be constructed by using the P-type epitaxial layer having the opposite polarity.

[0014]

However, in the method of manufacturing a magnetic detection device as described above, the pattern of the first mask is patterned on the semiconductor substrate, and the second mask is aligned and arranged on this semiconductor substrate. Then, since the pattern of the second mask is patterned on the semiconductor substrate, a patterning error on the semiconductor substrate occurs due to this alignment error, and the relative position between the electrode and the epitaxial layer is displaced, resulting in an electrical error. The lines of force were disturbed and an offset voltage was generated.

Further, since the above-described semiconductor substrate / mask alignment work is performed by a machine, there is a problem in that the offset voltage generated for each wafer to be processed also varies.

An object of the present invention is to provide a manufacturing method for reducing the offset voltage of a magnetic detection device.

[0017]

According to the present invention, the first
A step of forming a second conductivity type epitaxial layer on the surface of the conductivity type semiconductor substrate, a step of forming an oxide film on the epitaxial layer, and a first region having at least predetermined opposite side portions in the oxide film, In a region other than the first region, a step of simultaneously removing a plurality of second regions that are isolated from each other to form a through hole, and a step of forming a through hole in the first region from a first conductive layer. A step of introducing a type impurity to partition the epitaxial layer, and using a second mask that covers some of the plurality of second regions, from the second region that is not covered by the second mask. The step of introducing a second conductivity type impurity to form a second conductivity type diffusion layer on the surface of the epitaxial layer is constituted.

[0018]

With the above structure, regardless of the conductivity type of the region formed on the surface of the semiconductor substrate, the oxide film on the outer portion of the epitaxial layer and the region where the diffusion layer is formed can be removed simultaneously with the first mask. Therefore, in order to remove the oxide film on the portion where a region of different conductivity type is to be formed on the semiconductor substrate as in the conventional case, it is necessary to separately remove the oxide film by using a plurality of masks depending on the conductivity type of the region. Therefore, there is no displacement between the regions due to the misalignment between the semiconductor substrate and the mask.

[0019]

Embodiments will be described below with reference to the drawings.

2 and 3 are plan views of the mask used in this embodiment. The mask 52 shown in FIG. 2 is a mask in which the pattern of the mask 50 shown in FIG. 23 and the pattern shown in FIG. 24 are reversed. FIG. 3 is a view showing the mask 53 in which only the central portion is patterned,
The pattern portion is patterned so as to cover the N + type diffusion layer 5 as shown by the chain line in FIG.

FIG. 1 is a diagram showing a method of manufacturing a magnetic detection device.

As shown in FIG. 1A, first, an N type epitaxial layer 2 is grown on a P type substrate 1, and an oxide film 3 is formed on the entire surface of the N type epitaxial layer 2.

Next, the oxide film 3 is selectively removed by photoetching using the mask 52 to form the through hole 4 as shown in FIG. 1 (b).

Next, the resist film 7 formed on the entire surface is masked.
Using 53, patterning is performed as shown in FIG. Then, a P-type impurity 8 such as boron is added to the N-type epitaxial layer 2 not covered with the oxide film 3 and the resist film 7.
Is implanted by an ion implantation method or the like.

Next, as shown in FIG. 1D, the P-type impurity 8 implanted into the N-type epitaxial layer 2 is thermally diffused until it reaches the P-type substrate 1, and the P-type substrate 1 and the P-type substrate 1 are electrically spread within a predetermined range. The separated N-type epitaxial layer 2 is formed. After that, the resist film 7 is removed.

Next, a negative resist film 9 is applied on the entire surface, and the resist film 9 is removed using a mask 53 so that the through holes 4 of each contact portion are opened as shown in FIG. 1 (e). To do. Then, N-type impurities are injected from the through holes 4 by the ion implantation method or the like, and are thermally diffused to form the N ⁺ -type diffusion layer 5 serving as a contact region.

Finally, as shown in FIG. 1 (f), the through hole 4 portion and a part of the oxide film 3 on the P-type substrate 1 are removed to form a contact hole, and an aluminum electrode 6 is formed to form a hole. The element is completed.

As described above, the N ⁺ type diffusion layer 5 and the oxide film 3 on the P type substrate 1 portion can be removed with one mask 52. Further, in order to perform operations such as etching and impurity implantation only on the P-type substrate 1, it suffices to cover the N ⁺ -type diffusion layer 5 portion with the mask 53, and the allowable range of deviation when aligning the mask 53 with the semiconductor substrate. Is large, no error occurs due to mask misalignment during manufacturing. Therefore, it is possible to prevent the generation of the offset voltage due to the positional deviation.

Next, a second embodiment will be described.

FIG. 4 is a plan view showing a drift base type magnetic transistor, and the aluminum electrode is omitted for ease of viewing. FIG. 5 is a view showing a cross-sectional view taken along the line AA in FIG. 4, and FIG. 5 shows a contact hole for making contact with the P-type substrate 1 and an aluminum electrode 6.

Reference numeral 1 is a P-type substrate, and an N-type epitaxial layer 2 is formed on the surface of the central portion thereof so as to be electrically separated from the P-type substrate 1. N ⁺ type drift base regions 22 are formed near the left and right ends on the surface of the N type epitaxial layer 2, and a P type emitter region 20 and two P type collectors are provided between the two N ⁺ type drift base regions 22. Region 21 is formed.

In this embodiment, a mask 54 having a pattern drawn so as to cover the N ⁺ type drift base region 22, the P type emitter region 20, the P type collector region 21 and the P type substrate 1 as shown in FIG. , A mask 55 drawn so as to cover the N ⁺ type drift base region 22, the P type emitter region 20 and the P type collector region 21 (indicated by the dashed line in FIG. 6) as shown in FIG. 7, and shown in FIG. The drift-based magnetic field shown in FIG. 4 is obtained by using three masks 56, which are drawn so as to cover the P-type emitter region 20 and the P-type collector region 21 (inside the chain double-dashed line in FIG. 6). Form a transistor.

The manufacturing method will be briefly described. The P-type substrate 1
A positive type resist film is formed on the upper oxide film 3, and a mask 54 is arranged on this resist film to form an N ⁺ type drift base region 22, a P type emitter region 20, a P type collector region 21 and a P type substrate 1. The oxide film 3 on the region is removed, and then the mask
55 where N is not covered by the mask 55
P-type impurities are injected and diffused into the epitaxial layer 2.
Next, a positive type resist is formed on the entire surface, a mask 56 is arranged on this resist film, and N type impurities are implanted into the N type drift base region 22. Next, a negative type resist film is formed on the entire surface, a mask 56 is arranged on this resist film, and P
P type impurities are implanted into the type emitter region 20 and the P type collector region 21. In this way, each region is formed, and finally the aluminum electrode 6 is formed.

Also in this embodiment, one mask 54 can remove the N-type drift base region 22, the P-type collector region 21, the P-type emitter region 20, and the oxide film 3 on the P-type substrate 1 portion. In addition, the N-type drift base regions 22 and P of the semiconductor substrate
The type collector region 21 and the P type emitter region 20 are masked 55, P
Since the type collector region 21 and the P-type emitter region 20 are covered with the mask 56, the masks 55 and 56 only have to cover those parts, and a large allowable range of misalignment when the mask 55 and the mask 56 are aligned with the semiconductor substrate. Therefore, a mask deviation error in manufacturing does not occur. Therefore, it is possible to prevent the generation of the offset voltage due to the positional deviation.

Next, a third embodiment will be described with reference to FIGS.

FIG. 14 shows a mask 57 used in this embodiment.
Two sets of uncovered portions are patterned so as to face each other to form a contact region described later.

The manufacturing method of this embodiment will be described below with reference to FIGS. Also, the manufacturing method shown in FIGS.
FIG. 6 is a diagram showing a cross-sectional view of the mask 57 taken along line BB in FIG.

An oxide film 11 is formed on the N-type substrate 10, and a resist film 12 is formed on the entire surface of the oxide film 11. Next, the mask 57 is placed on the resist film 12, and the resist film 12 is selectively removed. (FIG. 9) Next, the oxide film 11 is selectively etched by photoetching to form a through hole 18. Next, the P-type impurity 13 is injected from the through hole 18 by an ion implantation method or the like. (FIG. 10) Next, the implanted P-type impurities 13 are thermally diffused until they overlap each other to form a P-type diffusion layer 14. (FIG. 11) Next, a large amount of P-type impurity is injected from the through hole 18 to form a P ⁺ -type contact region 15. (FIG. 12) Finally, the aluminum electrode 16 is formed in the through hole 18 to complete the Hall element. (FIG. 13) Actually, in order to make contact with the N-type substrate 10 as shown in the plan view of FIG. 15 and FIG. 16 which is a sectional view taken along the line CC of FIG. part by implanting N-type impurities to form the N ⁺ -type contact region 17, further an oxide film 11 on the N ⁺ -type contact region 17 is opened to form the aluminum electrode 16.

[0039]

According to the present invention, the step of forming the second conductive type epitaxial layer on the surface of the first conductive type semiconductor substrate, the step of forming an oxide film on the epitaxial layer, and the oxide film In a first region having at least predetermined both side portions and an inner region other than the first region,
A step of simultaneously removing a plurality of second regions that are isolated from each other to form a through hole, and introducing a first conductivity type impurity from the through hole formed in the first region to perform the epitaxial Using a step of defining a layer and a second mask covering some of the plurality of second regions,
It is formed on the semiconductor substrate because it comprises a step of introducing a second conductivity type impurity from the second region not covered with the second mask to form a second conductivity type diffusion layer on the surface of the epitaxial layer. Regardless of the conductivity type of the area,
Since the oxide film on the outer portion of the epitaxial layer and the region where the diffusion layer is formed can be removed simultaneously with the first mask, it is possible to form regions of different conductivity type on the semiconductor substrate as in the conventional case. It is not necessary to use a plurality of masks to separately remove the oxide film on the portion to be removed depending on the conductivity type of the region. Therefore, the displacement of the regions from one region to another due to the misalignment between the semiconductor substrate and the mask. Does not occur. Further, in order to form the diffusion layer with the second mask, it is sufficient to cover the vicinity of the necessary diffusion layer region of the semiconductor substrate, so that there is a large allowable range when aligning the second mask with the semiconductor substrate. No mask misalignment error occurs.

As described above, the offset voltage due to the positional deviation between the mask and the semiconductor substrate can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a mask pattern diagram used in the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a mask pattern diagram used in the manufacturing process of the first embodiment of the present invention.

FIG. 4 is a plan view of a second embodiment of the present invention.

FIG. 5 is a sectional view of a second embodiment of the present invention.

FIG. 6 is a mask pattern diagram used in a manufacturing process of a second embodiment of the present invention.

FIG. 7 is a mask pattern diagram used in a manufacturing process of a second embodiment of the present invention.

FIG. 8 is a mask pattern diagram used in a manufacturing process of a second embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of a third embodiment of the present invention.

FIG. 10 is a view showing a manufacturing process of the third embodiment of the present invention.

FIG. 11 is a view showing a manufacturing process of the third embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of a third embodiment of the present invention.

FIG. 13 is a view showing a manufacturing process of the third embodiment of the present invention.

FIG. 14 is a mask pattern diagram used in a manufacturing process of a third embodiment of the present invention.

FIG. 15 is a plan view of a third embodiment of the present invention.

FIG. 16 is a sectional view of a third embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of a conventional magnetic detection device.

FIG. 18 is a diagram showing a manufacturing process of a conventional magnetic detection device.

FIG. 19 is a view showing a manufacturing process of a conventional magnetic detection device.

FIG. 20 is a view showing a manufacturing process of a conventional magnetic detection device.

FIG. 21 is a view showing a manufacturing process of a conventional magnetic detection device.

FIG. 22 is a view showing a manufacturing process of a conventional magnetic detection device.

FIG. 23 is a mask pattern diagram used in a manufacturing process of a conventional magnetic detection device.

FIG. 24 is a mask pattern diagram used in a manufacturing process of a conventional magnetic detection device.

FIG. 25 is an operation explanatory view of a conventional magnetic detection device.

[Explanation of symbols]

1 ... P-type substrate 2, 25, 26 ... N-type epitaxial layer 3, 11 ... Oxide film 4, 18 ... Through hole 5, 30 ... N ⁺ type diffusion layer 6, 16 ... Aluminum electrode 7, 9, 12 ... Resist film 10 ... N type substrate 8, 13 ... P type impurity 14 ... P type diffusion layer 15 ... P ⁺ type contact region 17 ... N ⁺ type contact region 20 ... P type emitter region 21 ... P type collector region 22 ... N ⁺ type drift Base area 50-57… Mask

Claims (1)

[Claims] 1. A step of forming an epitaxial layer of a second conductivity type on a surface of a semiconductor substrate of a first conductivity type, a step of forming an oxide film on the epitaxial layer, and at least a predetermined side portion of the oxide film. Forming a through hole by simultaneously removing a first region having a space and a plurality of second regions separated from each other in an inner region other than the first region; Introducing impurities of the first conductivity type from the through holes to partition the epitaxial layer, and using a second mask that covers some of the plurality of second regions, and is covered with the second mask. Forming a diffusion layer of the second conductivity type on the surface of the epitaxial layer by introducing an impurity of the second conductivity type from the second region which has not been formed.