JP2013120883A - Lateral diffusion width evaluation method of diffusion region formed in semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral diffusion width evaluation method of a diffusion region formed in a semiconductor device, which can measure a lateral diffusion width at a predetermined depth from a surface of a diffusion region at a depth of approximately 100 μm with high accuracy, and which can measure an in-plane distribution of a lateral diffusion width on a wafer with high efficiency.SOLUTION: A lateral diffusion width evaluation method comprises grinding to a predetermined depth T1, a rear face 1a of a wafer 1 in which a deep diffusion region 2 is formed; polishing or etching the rear face 1a of the wafer 1 to expose the diffusion region 2; stain-etching the exposed diffusion region 2; and subsequently, measuring a lateral diffusion width W1 of the stain-etched diffusion region 2. In this way, the lateral diffusion width W1 at the predetermined depth T1 can be measured with high accuracy.

Description

  The present invention is formed in a semiconductor device capable of accurately measuring the width of a lateral diffusion layer at a predetermined depth from the surface in a deep diffusion region of about 100 μm and efficiently measuring the in-plane distribution of the lateral diffusion width. The present invention relates to a method for evaluating the lateral diffusion width of a diffused region.

  RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is an element that forms a deep diffusion region of about 100 μm from the front surface of a semiconductor substrate (wafer).

  6A and 6B are configuration diagrams of the RB-IGBT. FIG. 6A is a plan view of the main part, and FIG. 6B is a cross-sectional view of the main part taken along line XX of FIG. A p well region 52 is disposed on the surface layer of one main surface (front surface) of n semiconductor substrate 51, and n emitter region 53 is disposed on the surface layer of p well region 52. A gate electrode 55 is disposed on the p well region 52 sandwiched between the n emitter region 53 and the n semiconductor substrate 51 via a gate insulating film 54, and the n emitter region 53 is disposed on the gate insulating film 55 via an interlayer insulating film 56. In addition, an emitter electrode 57 electrically connected to the p-well region 52 is disposed. Hereinafter, the p well region 52, the n emitter region 53, the gate insulating film 54, and the gate electrode 55 refer to the interlayer insulating film 56 and the emitter electrode 57 as the surface structure, and overlapping descriptions and illustrations are omitted.

  A p collector region 58 is disposed on the surface layer of the other main surface (back surface) of n semiconductor substrate 51, and a collector electrode 59 electrically connected to p collector region 58 is disposed. A p diffusion region 2 connected to the front surface of the n semiconductor substrate 51 and the p collector region 58 is disposed on the side wall surface when the n semiconductor substrate 51 is divided into RB-IGBT chips. Are formed by deep diffusion through the n semiconductor substrate 51. In addition, since the p diffusion region 2 is formed so as to surround the surface structure 60, the p diffusion region is exposed over the entire circumference on the side wall surface when separated into RB-IGBT chips. A pn junction 7 is formed at each boundary between n semiconductor substrate 51 and p collector region 58 and between n semiconductor substrate 51 and p diffusion region 2. The reverse breakdown voltage of the RB-IGBT is ensured by the pn junction 7. That is, the deep p diffusion region 2 is a region necessary for ensuring the reverse breakdown voltage of the RB-IGBT. Further, a portion where each diffusion region is not formed in the n semiconductor substrate is an n drift region 51a, and reference numeral 8a is a side wall of the dicing line.

  FIG. 7 is a diagram illustrating a manufacturing process of the RB-IGBT illustrated in FIG. 6, and FIGS. 7A to 7C are main part manufacturing process cross-sectional views illustrated in the order of processes. Here, processes related to the deep p diffusion region 2 will be described.

  In FIG. 6A, a mask 65 is used to form a deep p diffusion region 2 having a diffusion depth T2 of more than 100 μm from the front surface of a thick n silicon wafer (hereinafter simply referred to as n wafer 1) having a thickness Q1 of about 500 μm. It forms using. The opening width Wo of the mask 65 is, for example, about 200 μm to 300 μm. The dicing line 8 is located at this location. Subsequently, a surface structure 60 is formed.

  Next, in FIG. 2B, the thick n wafer 1 is polished from the back surface 1a side until reaching the deep p diffusion region 2 to form a thin n wafer 3. Etching may be performed after the polishing step. The thin n wafer 3 has a thickness of, for example, 100 μm. At this time, the depth T1 of the p diffusion region 2 is the same as the thickness Q2 of the thin n wafer 3 and becomes 100 μm, and the p diffusion region 2 has an n thin wafer. 3 is exposed on the back surface.

  Next, in FIG. 3C, a p collector region 58 is formed on the back surface 3a of the thin n wafer 3 in contact with the deep p diffusion region 2 and with a depth of the order of μm. Subsequently, a collector electrode (not shown) is formed on the p collector region 58.

Thereafter, the n wafer 3 is cut along the dicing line 8.
In the step of FIG. 7B, it is necessary to confirm by actual measurement whether the lateral diffusion width W1 at the depth T1 from the front surface side of the deep p diffusion region 2 is as designed. That is, after polishing or etching, the p diffusion region 2 is exposed on the back surface 3a of the n wafer 3 as designed, and it is confirmed by actual measurement whether the lateral diffusion width W1 of the p diffusion region 2 on the exposed surface is as designed. There is a need to.

  FIG. 8 is a diagram illustrating a case where the diffusion depth T2 from the front surface side of the p diffusion region 2 is small. When the diffusion depth T2 is small, when the thick n wafer 1 is polished from the back surface, the p diffusion region 2 is not exposed to the back surface, cannot be connected to the p collector region 8, and the reverse breakdown voltage cannot be secured.

  FIG. 9 is a diagram illustrating a case where the lateral diffusion width W1 at the predetermined depth T1 of the p diffusion region 2 is small. If the lateral diffusion width W1 is small, the connecting portion between the p diffusion region 2 and the p collector region is cut during dicing, and the two are not connected. Alternatively, if a damage 61 such as a crack occurs in the p diffusion region 2 from the dicing line 8 during dicing, and a depletion layer reaches the location of the damage 61, an increase in leakage current and a decrease in reverse breakdown voltage are caused.

  FIG. 10 is a diagram illustrating a case where the lateral diffusion width W1 of the p diffusion region 2 is large. The width of n drift region 51a (the width of active region 62) becomes narrower than the design value, and the on-voltage increases. In addition, the depletion layer 63 extending from a pn junction (not shown) of the p well region 52 and the n drift region 51a reaches the p diffusion region 2 and it becomes difficult to ensure a forward breakdown voltage.

  From the above, in the step of FIG. 7B, the lateral diffusion width W1 of the p diffusion region 2 exposed on the back surface 3a of the thin n wafer 3, that is, the pn junction 7 facing the back surface 3a of the thin n wafer 3 is opposed. The interval W2 is measured, and it is evaluated and verified whether or not the lateral diffusion width W1 at the predetermined depth T1 of the p diffusion region 2 is formed as designed before the wafer is put into the manufacturing process. It will be necessary.

  FIG. 11 is a diagram showing an evaluation process (procedure) for measuring a lateral diffusion width at a predetermined depth of a conventional p diffusion region, and FIG. 11 (a) to FIG. It is principal part evaluation process sectional drawing.

  In FIG. 1A, a thick n wafer 1 having a deep p diffusion region 2 formed therein is cleaved or cut by a dicer at a position where the deepest part of the p diffusion region 2 is exposed. Thereafter, the cross section is polished or etched to perform processing for reducing processing damage in the cross section.

  Next, in FIG. 2B, the cross section is stain-etched to visualize the cross section of the p diffusion region 2 and the cross section of the n wafer 1 as stain-etched surfaces 1d and 2d. At this time, the pn junction 7 is also visualized.

  Next, in FIG. 3C, the visualized stain etching surface 2d of the p diffusion region, the stain etching surface 1d of the n wafer, and the pn junction 7 are converted into a two-dimensional image through an optical microscope. From this two-dimensional image, the lateral diffusion layer width W1 at a predetermined depth T1 of the p diffusion region 2 is measured.

  In addition to the above example, to determine the lateral diffusion in the doped region of the transistor, a test structure including the doped region is formed on the product wafer and the lateral diffusion region of the diffusion region in the test structure is measured. By doing so, it is known to test the lateral steepness of a doped region of a transistor formed at the same time (for example, Patent Document 1 (Abstract)). Note that Patent Document 1 describes a case where the diffusion depth of the diffusion region is as shallow as several μm or less.

  In addition, in order to measure the impurity concentration at a predetermined depth from the surface of the silicon substrate, which is a sample, a hole having a uniform depth is formed from the surface (front surface) of the substrate, and the polishing rate is higher than that of the silicon substrate It is known that a slow thin film is formed on the surface on the side where holes are formed, and the silicon substrate is polished from the back surface side until the thin film is exposed (for example, Patent Document 2 (abstract, paragraphs [0023] to [0023] In polishing from the back surface, the polishing is stopped when the thin film is exposed, and the impurity concentration distribution can be measured with high accuracy by performing SIMS measurement on the back surface of the substrate exposed on the back surface side. .

  In addition, when performing secondary ion mass spectrometry of the silicon layer of the SOI substrate including the silicon layer, the oxide film, and the support substrate, the support substrate is removed from the back surface by mechanical polishing, and the oxide film is removed by etching. It is known to expose a layer and perform secondary ion mass spectrometry from the exposed surface (for example, Patent Document 3 (Abstract)).

Special table 2006-500773 gazette JP 2000-195917 A JP 2002-303595 A

  However, since the measurement of the lateral diffusion width W1 at the predetermined depth T1 of the deep p diffusion region 2 shown in FIG. 11 is performed using an optical microscope, an error occurs. In particular, in the measurement of the predetermined depth T1 with an optical microscope, the entire area of the p diffusion region 2 needs to be taken into view, and the enlargement ratio cannot be set large. For this reason, an error of several μm occurs in the measurement of the predetermined depth T1.

  At a predetermined depth T1 of the p diffusion region 2 where the lateral diffusion width W1 is measured, the measurement location is near the bottom 2c of the p diffusion region 2 (see FIG. 12), and the pn junction 7 is greatly bent. Therefore, the lateral diffusion width W1 greatly depends on the predetermined depth T1, and if there is an error Δ1 of T5 to T6 at the predetermined depth T1 as shown in FIG. 12, the error Δ1 is enlarged and the lateral diffusion width is increased. An error Δ2 of W5 to W6 is generated in W1.

For this reason, even when the error of the predetermined depth T1 is several μm, the error of the lateral diffusion width W1 is enlarged to several tens μm.
Therefore, it becomes difficult to accurately measure the lateral diffusion width W1 from the conventional cross section.

  Further, in the conventional method, when measuring the lateral diffusion width W1 at a predetermined depth T1 of the p diffusion region having a complicated planar shape, it is necessary to perform cutting at all the measurement points, and within the wafer surface. Measuring the distribution takes time and cannot be done efficiently.

  Patent Documents 1, 2, and 3 describe a method of grinding a wafer from the back surface and measuring a lateral diffusion width at a predetermined depth of the diffusion region for a deep diffusion region having a diffusion depth exceeding 100 μm. Not listed.

  The object of the present invention is to solve the above-mentioned problems and to accurately measure the lateral diffusion layer width at a predetermined depth from the front surface in a deep diffusion region of about 100 μm. An object of the present invention is to provide a method for evaluating the lateral diffusion width of a diffusion region formed in a semiconductor device capable of efficiently measuring the wafer in-plane distribution.

  To achieve the above object, according to the first aspect of the present invention, the diffusion of the second conductivity type from the front surface of the semiconductor wafer of the first conductivity type toward the inside of the wafer. Forming a region, grinding the back surface of the semiconductor wafer, and grinding the entire back surface of the semiconductor wafer to remove the processed layer on the ground surface so that the thickness of the semiconductor wafer is less than the diffusion depth of the diffusion region Measuring the distance between two opposing points on the outer periphery of the diffusion region exposed on the back surface of the semiconductor wafer, and performing a chemical treatment on the back surface of the semiconductor wafer to visualize the conductivity type on the back surface of the semiconductor wafer. And measuring the lateral diffusion width at a predetermined depth of the diffusion region. The method for evaluating the lateral diffusion width of the diffusion region formed in the semiconductor device is provided.

  Further, according to the invention of claim 2, in the invention of claim 1, the dimension of the diffusion depth of the diffusion region before grinding of the semiconductor wafer is after grinding of the semiconductor wafer. It may be larger than the thickness dimension of the wafer.

  According to the invention described in claim 3, in the invention described in claim 1 or 2, a two-dimensional image of the diffusion region and the semiconductor substrate is obtained through a microscope. Further, it is preferable to obtain the lateral diffusion width at a predetermined depth of the diffusion region by measuring the lateral diffusion width of the diffusion region of the two-dimensional image at the interval between the opposing pn junctions.

  According to the invention of claim 4, in the invention of any one of claims 1 to 3, a plurality of the diffusion regions are formed in the semiconductor wafer, and the semiconductor wafer In the pn junction formed at the end of the diffusion region exposed on the back surface, the lateral diffusion width at a predetermined depth of the plurality of diffusion regions may be measured for the interval between the opposing pn junctions. .

  Moreover, according to invention of Claim 5 of Claim, in the invention as described in any one of Claims 1-4, the process of removing the process layer by the said grinding following the said thinning process It is good to have.

According to the invention as set forth in claim 6, the step of removing the processed layer in the invention according to claim 5 may use polishing or etching.
According to the invention described in claim 7 of the claims, in the invention described in any one of claims 1 to 6, the chemical treatment may be stain etching.

  According to the present invention, it is possible to accurately measure the width of the lateral diffusion layer at a predetermined depth from the front surface of the substrate in the deep diffusion region, and it is possible to efficiently measure the in-plane distribution of the lateral diffusion width.

It is a figure explaining the evaluation method of the horizontal direction diffusion width of the diffusion area | region formed in the semiconductor device of one Example of this invention, (a)-(d) is principal part process sectional drawing shown to process order. FIG. 3 is a view showing stain etching surfaces 2b and 3b of a p diffusion region 2 and an n wafer 3, respectively. 2 is a view showing a stain etching surface 3b of a thin n wafer 3 provided with a plurality of p diffusion regions 2 and a stain etching surface 2b of a p diffusion region 2. FIG. It is a figure which shows the stain etching surface 3b of the thin n wafer 3 of the location which hits the corner of a semiconductor chip, and the stain etching surface 2b of the p diffusion region 2. It is principal part sectional drawing of RB-IGBT which formed V groove in the back surface. It is a block diagram of RB-IGBT, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). It is a figure explaining the manufacturing method of RB-IGBT of FIG. 6, (a)-(c) is principal part manufacturing process sectional drawing shown to process order. It is a figure explaining the case where the diffusion depth T2 of the p diffusion region 2 is small. It is a figure explaining the case where the horizontal direction diffusion width W1 in the predetermined depth T1 of the p diffusion region 2 is small. It is a figure explaining the case where the horizontal direction diffusion width W1 of the p diffusion area | region 2 is large. It is a figure explaining the evaluation process (procedure) which measures the horizontal direction diffusion width in the predetermined depth of the conventional p diffusion area | region, (a)-(c) is the principal part evaluation process sectional drawing shown to the process order. is there. It is a figure explaining the measurement error about the horizontal direction diffusion width in the predetermined depth of the conventional p diffusion area | region.

Embodiments will be described in the following examples.
<Example>
FIG. 1 is a diagram for explaining a method for evaluating the lateral diffusion width of a diffusion region formed in a semiconductor device according to one embodiment of the present invention. FIG. 1 (a) to FIG. It is principal part process sectional drawing. In the following notation, n indicates that the conductivity type is n-type, and p indicates that the conductivity type is p-type. The evaluation method of FIG. 1 shows a method for measuring the lateral diffusion width W1 at a predetermined depth T1 of the deep p diffusion region 2 of the RB-IGBT. This measurement is performed in order to confirm whether or not the p diffusion region 2 can be performed as designed before putting the wafer into the manufacturing process. Therefore, the p diffusion region 2 is formed in a predetermined pattern on the test wafer, and the lateral diffusion width at a predetermined depth from the front surface of the wafer in the p diffusion region 2 is measured.

  First, as shown in FIG. 2A, a deep p diffusion region 2 having a diffusion depth T2 is formed on the front surface side of a thick n wafer 1 having a thickness Q1. The thickness Q1 of the thick n-wafer 1 is a thickness at the time of entering a wafer manufacturing process used for manufacturing a product.

  Further, the p diffusion region 2 formed in the thickness Q1 of the thick n wafer 1 is for evaluating whether or not the p diffusion region surrounding the outer periphery of the RB-IGBT as a product is formed as designed. Similarly to the p diffusion region 2 of the RB-IGBT (see FIG. 7) to be a product, the opening of the mask 65 may be formed as Wo. Alternatively, p diffusion regions may be formed at a plurality of locations on the n wafer 1 with a mask having a predetermined opening, and the dispersion variation in one wafer may be measured.

Next, as shown in FIG. 2B, grinding is performed from the back surface 1a side of the thick n-wafer 1, and a processed layer by grinding is removed by polishing or etching to form a thin n-wafer 3 having a thickness Q2. Etching is performed using, for example, an aqueous solution of hydrofluoric acid (HF) and nitric acid (HNO ₃ ). The polishing is performed using, for example, a CMP (Chemical Mechanical Polishing) method.

  The thickness Q2 of the thin n wafer 3 corresponds to a predetermined depth T1 of the p diffusion region 2. Therefore, after the thinning process of the thick n wafer 1, when the p diffusion region is not exposed on the back surface of the thin n wafer 3, the p diffusion region 2 has a predetermined depth (T1) as shown in FIG. It will not reach.

  When the p diffusion region 2 reaches a predetermined depth T1 and further reaches a predetermined depth T2 deeper than that, the back surface 2a of the p diffusion region 2 is exposed on the back surface 3a of the thin n wafer 3. The thickness Q2 of the thinned n wafer 3, that is, the accuracy of the thickness of the n wafer thinned by the grinding process (polishing / etching process) is about 1 μm or less. That is, the error of the predetermined depth T1 of the p diffusion region 2 for measuring the lateral diffusion width W1 is about 1 μm or less.

  Here, the thickness Q1 of the thick n wafer is about 500 μm, and the thickness Q2 of the thin n wafer is about 100 μm. In the case of RB-IGBT, the thickness of the n wafer depends on the rated voltage, and becomes thicker as the rated voltage becomes higher. Incidentally, the thickness Q2 is set to 100 μm when the rated voltage is about 600V.

In the above example, the diffusion depth T2 of the deep p diffusion region is about 120 μm, and the predetermined depth T1, that is, the thickness Q2 of the thin n-wafer 3 is about 100 μm, which is about 20 μm smaller.
Next, in FIG. 3C, the thin n wafer 3 is immersed in the stain etching solution 5 to stain the back surface 3a of the n wafer 3, and the back surface 2a of the p diffusion region 2 and the back surface of the n wafer 3 are then etched. 3a is made into the stain etching surfaces 2b and 3b and visualized as shown in FIG.

  In FIG. 2, the difference between the two oblique lines indicates the difference in color between the back surface 2a of the p diffusion region 2 and the back surface 3a of the n wafer 3 (optical microscope image) or the difference in black and white (SEM image) caused by stain etching. It is a two-dimensional image. The boundary between the p diffusion region 2 and the n wafer 3 is a pn junction 7.

  Next, in FIG. 1D, using the visualized two-dimensional image shown in FIG. 2, the interval W2 between the pn junctions 7 facing each other is measured from an optical microscope image 6 or an SEM (electron microscope) image. The region sandwiched between the pn junctions 7 is the p diffusion region 2, and the interval W <b> 2 between the opposing pn junctions 7 is the lateral diffusion width W <b> 1 of the p diffusion region 2. Accordingly, the lateral diffusion width W1 can be obtained by measuring the interval W2 between the opposing pn junctions 7. FIG. 4D shows a diagram measured with the optical microscope 6, and the two-dimensional image shown in FIG. 2 is obtained with the reflected light 6a.

  As described above, the predetermined depth T1 of the p diffusion region 2 is determined by the thickness Q2 of the thin n wafer 3. The error in the thickness Q2 of the thin n wafer 3 is determined by the precision of grinding and polishing or etching, and this precision is extremely high. Therefore, the error of the thickness Q2 of the thin n wafer 3 can be about 1 μm or less, that is, the error of the predetermined depth T1 of the p diffusion region 2 can be 1 μm or less (several μm in the conventional method). As a result, the error in the lateral diffusion width W1 can be reduced to about several μm (ten and several μm in the conventional method), and the lateral diffusion width W1 can be accurately measured.

  Further, as shown in FIG. 3, by providing a number of p diffusion regions 2 on the n wafer 3 and measuring the lateral diffusion width W1 of the p diffusion region 2b exposed on the back surface, the wafer having the lateral diffusion width W1 is measured. The in-plane distribution can be measured efficiently.

  In FIG. 3, since a large number of p diffusion regions are formed in a rectangular pattern, the pn junctions are exposed as opposing sides. Therefore, the lateral diffusion width can be measured by measuring the distance (interval) between the opposing sides. Similarly, measurement can be performed for the other two sides. The same applies to square patterns. The shape of the p diffusion region is not limited to a square, and may be other shapes. For example, a large number of p diffusion regions are formed as a circular or elliptical pattern, and the distance between two opposing points of a circular or elliptical p diffusion region (not shown) exposed on the back surface, that is, the diameter (in the case of an ellipse) May measure the length of the minor axis or the major axis).

  Alternatively, it may be formed as a so-called “mouth” letter-shaped p diffusion region that surrounds the element region in the same manner as the p diffusion region that surrounds the outer periphery of the RB-IGBT to be a product (not shown). The measurement of the distance of the part where the pn junction of the p diffusion region exposed on the back face is the same as the above rectangular pattern.

  Also, as shown in FIG. 4, the measurement of the lateral diffusion width W1 at a predetermined depth at the location B that becomes the corner of the semiconductor chip is more flat than the conventional measurement of the cross section. The measurement at is more suitable because it can measure the whole corner.

  In addition, the evaluation method according to the present invention can be applied not only to the case of the deep p diffusion region 2 of the RB-IGBT as described with reference to FIG. 6, but also to the lateral width of the deep diffusion region at a predetermined depth in other semiconductor devices. It can also be applied when measuring the directional diffusion width.

Furthermore, it is also suitable for measuring a lateral diffusion width at a predetermined depth of a deep diffusion region having a complicated planar pattern as shown in FIG.
Further, in the RB-IGBT having a breakdown voltage of 1200 V class, the thickness of the semiconductor substrate is about 200 μm. FIG. 5 is a cross-sectional view of the main part of the RB-IGBT in which a groove is formed on the back surface, and the breakdown voltage termination structure formed on the collector electrode and the surface layer of the semiconductor substrate is not shown. In the figure, 51a is an n drift region, and 8a is a side surface of the dicing line. The thickness Q3 of the n semiconductor substrate 51 is 200 μm. It is difficult to form a very deep diffusion region that reaches from one surface (front surface) of the semiconductor substrate having such a thickness to the other surface (back surface). Therefore, as shown in FIG. 5, a p diffusion region 2 having a depth T2 (for example, about 120 μm) is formed as in FIG. 1, and a groove 59 reaching the p diffusion region 2 from the back surface 3a of the n semiconductor substrate is formed. . When the trench reaches the p diffusion region 2, the depth of the p diffusion region 2 becomes T1 (for example, 100 μm). A p diffusion layer 59 a connected to the p diffusion region 2 and the p collector region 58 is formed on the side surface of the groove 59. The p diffusion region 2 and the p diffusion layer 59a function as the p diffusion region 2 in FIG.

  Also in this case, it is necessary to accurately grasp the lateral diffusion width W1 at a predetermined depth of the p diffusion region 2, and the present invention can be applied. That is, the p diffusion region 2 is formed in the same manner as in the process shown in FIG. 1, and grinding and polishing (etching) are performed until the groove 59 reaches a depth (the thickness of the n semiconductor substrate). Then, by measuring the interval W1 of the pn junction exposed on the back surface, the lateral diffusion width W1 of the p diffusion region at a predetermined depth from the front surface of the n semiconductor substrate can be measured. That is, it can be evaluated whether or not the trench 59 reaches the p diffusion region 2 and the p diffusion region 2 and the p diffusion layer 59 are securely connected when the RB-IGBT is formed.

  In the case where an RB-IGBT having a breakdown voltage of 1200 V class is formed so that the p diffusion region 2 reaches the back surface 3a without forming the groove 59 as in the 600 V class, the same effect can be obtained by applying the present invention. can get.

  In the above-described embodiment, the case where the lateral diffusion width at a predetermined depth of the p-type diffusion region is measured has been described as an example. According to the present invention, the boundary portion of the np junction that has been ground and exposed on the back surface is targeted for measurement. Therefore, even when an opposite conductivity type, that is, an n-type diffusion region is formed, a predetermined depth of the diffusion region is formed. The lateral diffusion width can be measured.

1 Thick wafer 1d Stain etched surface (cross section of thick wafer 1)
1a, 2a, 3a Back surface 2 p diffusion region 2b stain etching surface (back surface 2a of p diffusion region)
2c Bottom (p diffusion region 2)
2d Stain etched surface (cross section of p diffusion region)
3 Thin wafer 3b Stain etched surface (n wafer back surface 3a)
5 stain etching liquid 6 optical microscope 6a reflected light 7 pn junction 8 dicing line 8a side surface 51 n semiconductor substrate 51a n drift region 52 p well region 53 n emitter region 54 gate insulating film 55 gate electrode 56 interlayer insulating film 57 emitter electrode 58 p Collector region 59 Groove 59a p diffusion layer 60 Surface structure 61 Damage (crack)
62 active region 63 depletion layer 65 mask T1 predetermined depth of p diffusion region T2 diffusion depth of p diffusion region W1 lateral diffusion width at predetermined depth W2 spacing between opposing pn junctions Q1 thickness of thick wafer 1 Q2 Thickness of thin wafer 3 Δ1 Predetermined depth error Δ2 Lateral diffusion width error

Claims (7)

Forming a diffusion region of the second conductivity type from the front surface of the first conductivity type semiconductor wafer toward the inside of the wafer;
Grinding the entire back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to make the thickness of the semiconductor wafer thinner than the diffusion depth of the diffusion region, and removing the processing layer of the ground surface;
Visualizing the conductivity type of the backside of the semiconductor by chemically treating the backside of the semiconductor wafer;
Measuring a lateral diffusion width at a predetermined depth of the diffusion region by measuring an interval between two opposing points on the outer periphery of the diffusion region exposed on the back surface of the semiconductor wafer;
A method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device.   2. The semiconductor device according to claim 1, wherein a dimension of a diffusion depth of the diffusion region before grinding of the semiconductor wafer is larger than a dimension of a thickness of the wafer after grinding of the semiconductor wafer. Evaluation method of lateral diffusion width of diffusion region.   A two-dimensional image of the diffusion region and the semiconductor substrate is obtained through a microscope, and by measuring a lateral diffusion width of the diffusion region of the obtained two-dimensional image at an interval between opposing pn junctions, the diffusion 3. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 1, wherein a lateral diffusion width at a predetermined depth of the region is obtained. Forming a plurality of diffusion regions in the semiconductor wafer;
In the pn junction formed at the end of the diffusion region exposed on the back surface of the semiconductor wafer, the lateral diffusion width at a predetermined depth of the plurality of diffusion regions is set for the interval between the pn junctions facing each other. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to any one of claims 1 to 3, wherein:   5. The lateral diffusion width of the diffusion region formed in the semiconductor device according to claim 1, further comprising a step of removing a processed layer by the grinding following the thinning step. 6. Evaluation method.   6. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 5, wherein the step of removing the processed layer uses polishing or etching. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 1, wherein the chemical treatment is stain etching.

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