JP2013120883A - Lateral diffusion width evaluation method of diffusion region formed in semiconductor device - Google Patents

Lateral diffusion width evaluation method of diffusion region formed in semiconductor device Download PDF

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JP2013120883A
JP2013120883A JP2011268860A JP2011268860A JP2013120883A JP 2013120883 A JP2013120883 A JP 2013120883A JP 2011268860 A JP2011268860 A JP 2011268860A JP 2011268860 A JP2011268860 A JP 2011268860A JP 2013120883 A JP2013120883 A JP 2013120883A
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diffusion
diffusion region
wafer
width
lateral
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Masaaki Ogino
正明 荻野
Reiko Hiruta
玲子 蛭田
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Fuji Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a lateral diffusion width evaluation method of a diffusion region formed in a semiconductor device, which can measure a lateral diffusion width at a predetermined depth from a surface of a diffusion region at a depth of approximately 100 μm with high accuracy, and which can measure an in-plane distribution of a lateral diffusion width on a wafer with high efficiency.SOLUTION: A lateral diffusion width evaluation method comprises grinding to a predetermined depth T1, a rear face 1a of a wafer 1 in which a deep diffusion region 2 is formed; polishing or etching the rear face 1a of the wafer 1 to expose the diffusion region 2; stain-etching the exposed diffusion region 2; and subsequently, measuring a lateral diffusion width W1 of the stain-etched diffusion region 2. In this way, the lateral diffusion width W1 at the predetermined depth T1 can be measured with high accuracy.

Description

この発明は、100μm程度の深い拡散領域について、表面から所定の深さでの横方向拡散層幅を精度よく計測でき、また横方向拡散幅のウェハ面内分布を効率よく計測できる半導体装置に形成された拡散領域の横方向拡散幅の評価方法に関する。   The present invention is formed in a semiconductor device capable of accurately measuring the width of a lateral diffusion layer at a predetermined depth from the surface in a deep diffusion region of about 100 μm and efficiently measuring the in-plane distribution of the lateral diffusion width. The present invention relates to a method for evaluating the lateral diffusion width of a diffused region.

半導体基板(ウェハ)のおもて面から100μm程度の深い拡散領域を形成する素子として、RB−IGBT(Reverse Blocking IGBT:逆阻止型の絶縁ゲート型バイポーラトランジスタ)がある。   RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is an element that forms a deep diffusion region of about 100 μm from the front surface of a semiconductor substrate (wafer).

図6は、RB−IGBTの構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX−X線で切断した要部断面図である。 n半導体基板51の一方の主面(おもて面)の表面層にpウェル領域52が配置され、pウェル領域52の表面層にnエミッタ領域53が配置されている。nエミッタ領域53とn半導体基板51に挟まれたpウェル領域52上にゲート絶縁膜54を介してゲート電極55が配置され、ゲート絶縁膜55上に層間絶縁膜56を介してnエミッタ領域53およびpウェル領域52に電気的に接続するエミッタ電極57が配置されている。以下において、pウェル領域52,nエミッタ領域53,ゲート絶縁膜54,ゲート電極55が,層間絶縁膜56,エミッタ電極57を表面構造と称し、重複する説明や図示を省略する。   6A and 6B are configuration diagrams of the RB-IGBT. FIG. 6A is a plan view of the main part, and FIG. 6B is a cross-sectional view of the main part taken along line XX of FIG. A p well region 52 is disposed on the surface layer of one main surface (front surface) of n semiconductor substrate 51, and n emitter region 53 is disposed on the surface layer of p well region 52. A gate electrode 55 is disposed on the p well region 52 sandwiched between the n emitter region 53 and the n semiconductor substrate 51 via a gate insulating film 54, and the n emitter region 53 is disposed on the gate insulating film 55 via an interlayer insulating film 56. In addition, an emitter electrode 57 electrically connected to the p-well region 52 is disposed. Hereinafter, the p well region 52, the n emitter region 53, the gate insulating film 54, and the gate electrode 55 refer to the interlayer insulating film 56 and the emitter electrode 57 as the surface structure, and overlapping descriptions and illustrations are omitted.

n半導体基板51の他方の主面(裏面)の表面層にpコレクタ領域58が配置され、pコレクタ領域58と電気的に接続するコレクタ電極59が配置されている。n半導体基板51をRB−IGBTのチップに個片化した際の側壁面にはn半導体基板51のおもて面とpコレクタ領域58と接続するp拡散領域2が配置され、p拡散領域2はn半導体基板51を貫通する深い拡散によって形成される。また、p拡散領域2は表面構造60を取り囲むように形成されるため、RB−IGBTのチップに個片化した際の側壁面には、全周に渡ってp拡散領域が露出する。n半導体基板51とpコレクタ領域58およびn半導体基板51とp拡散領域2のそれぞれの境界にはpn接合7が形成される。このpn接合7でRB−IGBTの逆耐圧は確保されている。つまり、深いp拡散領域2は、RB−IGBTの逆耐圧を確保するために必要な領域である。また、n半導体基板で各拡散領域が形成されない箇所はnドリフト領域51aであり符号8aはダイシングラインの側壁である。   A p collector region 58 is disposed on the surface layer of the other main surface (back surface) of n semiconductor substrate 51, and a collector electrode 59 electrically connected to p collector region 58 is disposed. A p diffusion region 2 connected to the front surface of the n semiconductor substrate 51 and the p collector region 58 is disposed on the side wall surface when the n semiconductor substrate 51 is divided into RB-IGBT chips. Are formed by deep diffusion through the n semiconductor substrate 51. In addition, since the p diffusion region 2 is formed so as to surround the surface structure 60, the p diffusion region is exposed over the entire circumference on the side wall surface when separated into RB-IGBT chips. A pn junction 7 is formed at each boundary between n semiconductor substrate 51 and p collector region 58 and between n semiconductor substrate 51 and p diffusion region 2. The reverse breakdown voltage of the RB-IGBT is ensured by the pn junction 7. That is, the deep p diffusion region 2 is a region necessary for ensuring the reverse breakdown voltage of the RB-IGBT. Further, a portion where each diffusion region is not formed in the n semiconductor substrate is an n drift region 51a, and reference numeral 8a is a side wall of the dicing line.

図7は、図6に示したRB−IGBTの製造工程を示す図であり、同図(a)〜同図(c)は工程順に示した要部製造工程断面図である。ここでは深いp拡散領域2に関連する工程について説明する。   FIG. 7 is a diagram illustrating a manufacturing process of the RB-IGBT illustrated in FIG. 6, and FIGS. 7A to 7C are main part manufacturing process cross-sectional views illustrated in the order of processes. Here, processes related to the deep p diffusion region 2 will be described.

同図(a)において、厚さQ1が500μm程度の厚いnシリコンウェハ(以下、単にnウェハ1と称す)のおもて面から拡散深さT2が100μm超の深いp拡散領域2をマスク65を用いて形成する。マスク65開口幅Woは例えば、200μm〜300μm程度である。この箇所にダイシングライン8が位置する。続いて表面構造60を形成する。   In FIG. 6A, a mask 65 is used to form a deep p diffusion region 2 having a diffusion depth T2 of more than 100 μm from the front surface of a thick n silicon wafer (hereinafter simply referred to as n wafer 1) having a thickness Q1 of about 500 μm. It forms using. The opening width Wo of the mask 65 is, for example, about 200 μm to 300 μm. The dicing line 8 is located at this location. Subsequently, a surface structure 60 is formed.

つぎに、同図(b)において、厚いnウェハ1を裏面1a側から深いp拡散領域2に達するまで研磨して薄いnウェハ3にする。研磨工程の後にエッチングを行う場合もある。薄いnウェハ3は例えば100μmの厚さであり、この時点でp拡散領域2の深さT1は薄いnウェハ3の厚さQ2と同じであり100μmとなって、p拡散領域2はn薄いウェハ3の裏面に露出する。   Next, in FIG. 2B, the thick n wafer 1 is polished from the back surface 1a side until reaching the deep p diffusion region 2 to form a thin n wafer 3. Etching may be performed after the polishing step. The thin n wafer 3 has a thickness of, for example, 100 μm. At this time, the depth T1 of the p diffusion region 2 is the same as the thickness Q2 of the thin n wafer 3 and becomes 100 μm, and the p diffusion region 2 has an n thin wafer. 3 is exposed on the back surface.

つぎに、同図(c)において、薄いnウェハ3の裏面3aに深いp拡散領域2に接しμmオーダの深さでpコレクタ領域58を形成する。続いて、pコレクタ領域58上に図示しないコレクタ電極を形成する。   Next, in FIG. 3C, a p collector region 58 is formed on the back surface 3a of the thin n wafer 3 in contact with the deep p diffusion region 2 and with a depth of the order of μm. Subsequently, a collector electrode (not shown) is formed on the p collector region 58.

その後、ダイシングライン8に沿ってnウェハ3を切断する。
前記の図7(b)の工程で、深いp拡散領域2のおもて面側からの深さT1における横方向拡散幅W1が設計通りとなっているかを実測で確認する必要がある。つまり、研磨またはエッチング後にp拡散領域2がnウェハ3の裏面3aに設計通りに露出し、その露出面でのp拡散領域2の横方向拡散幅W1が設計通りになっているかを実測で確認する必要がある。
Thereafter, the n wafer 3 is cut along the dicing line 8.
In the step of FIG. 7B, it is necessary to confirm by actual measurement whether the lateral diffusion width W1 at the depth T1 from the front surface side of the deep p diffusion region 2 is as designed. That is, after polishing or etching, the p diffusion region 2 is exposed on the back surface 3a of the n wafer 3 as designed, and it is confirmed by actual measurement whether the lateral diffusion width W1 of the p diffusion region 2 on the exposed surface is as designed. There is a need to.

図8は、p拡散領域2のおもて面側からの拡散深さT2が小さい場合を説明する図である。拡散深さT2が小さいと、厚いnウェハ1を裏面から研磨した際にp拡散領域2が裏面に露出せず、pコレクタ領域8との接続ができず、また逆耐圧が確保できなくなる。   FIG. 8 is a diagram illustrating a case where the diffusion depth T2 from the front surface side of the p diffusion region 2 is small. When the diffusion depth T2 is small, when the thick n wafer 1 is polished from the back surface, the p diffusion region 2 is not exposed to the back surface, cannot be connected to the p collector region 8, and the reverse breakdown voltage cannot be secured.

図9は、p拡散領域2の所定の深さT1での横方向拡散幅W1が小さい場合を説明する図である。横方向拡散幅W1が小さいと、ダイシング時にp拡散領域2とpコレクタ領域との接続部分が切断されて両者が接続されていない状態となってしまう。あるいは、ダイシング時にダイシングライン8からp拡散領域2内にクラック等の損傷61が生じ、その損傷61の箇所へ空乏層が達すると、漏れ電流の増加や逆耐圧の低下を招く。   FIG. 9 is a diagram illustrating a case where the lateral diffusion width W1 at the predetermined depth T1 of the p diffusion region 2 is small. If the lateral diffusion width W1 is small, the connecting portion between the p diffusion region 2 and the p collector region is cut during dicing, and the two are not connected. Alternatively, if a damage 61 such as a crack occurs in the p diffusion region 2 from the dicing line 8 during dicing, and a depletion layer reaches the location of the damage 61, an increase in leakage current and a decrease in reverse breakdown voltage are caused.

図10は、p拡散領域2の横方向拡散幅W1が大きい場合を説明する図である。nドリフト領域51aの幅(活性領域62の幅)が設計値に比べて狭くなり、オン電圧が増大する。また、pウェル領域52とnドリフト領域51aの図示しないpn接合から伸びる空乏層63がp拡散領域2に達して、順耐圧の確保が困難になる。   FIG. 10 is a diagram illustrating a case where the lateral diffusion width W1 of the p diffusion region 2 is large. The width of n drift region 51a (the width of active region 62) becomes narrower than the design value, and the on-voltage increases. In addition, the depletion layer 63 extending from a pn junction (not shown) of the p well region 52 and the n drift region 51a reaches the p diffusion region 2 and it becomes difficult to ensure a forward breakdown voltage.

前記のことから、図7(b)の工程において、薄いnウェハ3の裏面3aに露出するp拡散領域2の横方向拡散幅W1すなわち、薄いnウェハ3の裏面3aにおいて対向するpn接合7の間隔W2を計測して、製造プロセスにウェハが投入される前に、事前にp拡散領域2の所定の深さT1での横方向拡散幅W1が設計通りに形成されているかを評価、検証することが必要となる。   From the above, in the step of FIG. 7B, the lateral diffusion width W1 of the p diffusion region 2 exposed on the back surface 3a of the thin n wafer 3, that is, the pn junction 7 facing the back surface 3a of the thin n wafer 3 is opposed. The interval W2 is measured, and it is evaluated and verified whether or not the lateral diffusion width W1 at the predetermined depth T1 of the p diffusion region 2 is formed as designed before the wafer is put into the manufacturing process. It will be necessary.

図11は、従来のp拡散領域の所定の深さでの横方向拡散幅を計測する評価工程(手順)を示す図であり、同図(a)〜同図(c)は工程順に示した要部評価工程断面図である。   FIG. 11 is a diagram showing an evaluation process (procedure) for measuring a lateral diffusion width at a predetermined depth of a conventional p diffusion region, and FIG. 11 (a) to FIG. It is principal part evaluation process sectional drawing.

同図(a)において、深いp拡散領域2が形成された厚いnウェハ1を、p拡散領域2の最深部が露出するような位置でへき開またはダイサー切断で断面を露出させる。その後、断面を研磨またはエッチングして、断面での加工ダメージを低減させる処理を行う。   In FIG. 1A, a thick n wafer 1 having a deep p diffusion region 2 formed therein is cleaved or cut by a dicer at a position where the deepest part of the p diffusion region 2 is exposed. Thereafter, the cross section is polished or etched to perform processing for reducing processing damage in the cross section.

つぎに、同図(b)において、断面をステインエッチングして、p拡散領域2の断面とnウェハ1の断面をステインエッチ面1d、2dにして可視化する。このときpn接合7も可視化される。   Next, in FIG. 2B, the cross section is stain-etched to visualize the cross section of the p diffusion region 2 and the cross section of the n wafer 1 as stain-etched surfaces 1d and 2d. At this time, the pn junction 7 is also visualized.

つぎに、同図(c)において、可視化されたp拡散領域のステインエッチング面2d、nウェハのステインエッチング面1dおよびpn接合7を光学顕微鏡を介して二次元画像とする。この二次元画像からp拡散領域2の所定の深さT1における横方向拡散層幅W1を計測する。   Next, in FIG. 3C, the visualized stain etching surface 2d of the p diffusion region, the stain etching surface 1d of the n wafer, and the pn junction 7 are converted into a two-dimensional image through an optical microscope. From this two-dimensional image, the lateral diffusion layer width W1 at a predetermined depth T1 of the p diffusion region 2 is measured.

上記の例のほかに、トランジスタのドーピングされた領域における横方向拡散を判断するのに、ドーピングされた領域を含むテスト構造を製品ウェハに形成し、テスト構造における拡散領域の横方向拡散領域を計測することにより、同時に形成されたトランジスタのドーピングされた領域の横方向の急峻性をテストすることが知られている(例えば、特許文献1(要約))。なお、特許文献1においては、拡散領域の拡散深さが数μm以下と浅い場合が記載されている。   In addition to the above example, to determine the lateral diffusion in the doped region of the transistor, a test structure including the doped region is formed on the product wafer and the lateral diffusion region of the diffusion region in the test structure is measured. By doing so, it is known to test the lateral steepness of a doped region of a transistor formed at the same time (for example, Patent Document 1 (Abstract)). Note that Patent Document 1 describes a case where the diffusion depth of the diffusion region is as shallow as several μm or less.

また、試料であるシリコン基板の表面から所定の深さにおける不純物濃度を測定するために、基板の表面(おもて面)から深さがが均一孔を形成して、研磨速度がシリコン基板より遅い薄膜を孔が形成された側の表面に形成し、シリコン基板を裏面側から前記薄膜が露出するまで研磨することが知られている(例えば、特許文献2(要約、段落[0023]〜[0026])。裏面からの研磨において、前記薄膜が露出した時点で研磨を停止し、裏面側に露出した基板の裏面をSIMS測定することによって、高精度に不純物濃度分布の測定を行うことができる。   In addition, in order to measure the impurity concentration at a predetermined depth from the surface of the silicon substrate, which is a sample, a hole having a uniform depth is formed from the surface (front surface) of the substrate, and the polishing rate is higher than that of the silicon substrate It is known that a slow thin film is formed on the surface on the side where holes are formed, and the silicon substrate is polished from the back surface side until the thin film is exposed (for example, Patent Document 2 (abstract, paragraphs [0023] to [0023] In polishing from the back surface, the polishing is stopped when the thin film is exposed, and the impurity concentration distribution can be measured with high accuracy by performing SIMS measurement on the back surface of the substrate exposed on the back surface side. .

また、シリコン層、酸化膜、支持基板からなるSOI基板のシリコン層の2次イオン質量分析を行う際に、裏面側から支持基板を機械的研磨で除去し、酸化膜をエッチングによって除去してシリコン層を露出させ、露出した面から2次イオン質量分析を行うことが知られている(例えば、特許文献3(要約))。   In addition, when performing secondary ion mass spectrometry of the silicon layer of the SOI substrate including the silicon layer, the oxide film, and the support substrate, the support substrate is removed from the back surface by mechanical polishing, and the oxide film is removed by etching. It is known to expose a layer and perform secondary ion mass spectrometry from the exposed surface (for example, Patent Document 3 (Abstract)).

特表2006−500773号公報Special table 2006-500773 gazette 特開2000−195917号公報JP 2000-195917 A 特開2002−303595号公報JP 2002-303595 A

しかし、前記した図11に示す深いp拡散領域2の所定の深さT1での横方向拡散幅W1の計測は、光学顕微鏡を用いて行うため誤差が生じる。特に、光学顕微鏡での所定の深さT1の計測では、p拡散領域2の全域を視野に入れる必要があり、拡大率を大きく設定することがきない。そのために、所定の深さT1の計測で数μmの誤差が生じてしまう。   However, since the measurement of the lateral diffusion width W1 at the predetermined depth T1 of the deep p diffusion region 2 shown in FIG. 11 is performed using an optical microscope, an error occurs. In particular, in the measurement of the predetermined depth T1 with an optical microscope, the entire area of the p diffusion region 2 needs to be taken into view, and the enlargement ratio cannot be set large. For this reason, an error of several μm occurs in the measurement of the predetermined depth T1.

横方向拡散幅W1を計測するp拡散領域2の所定の深さT1では、計測箇所がp拡散領域2の底部2c付近(図12参照)となり、pn接合7は大きく曲がっている。そのため、横方向拡散幅W1は所定の深さT1に大きく依存し、図12示すように所定の深さT1にT5〜T6の誤差Δ1があると、この誤差Δ1が拡大されて横方向拡散幅W1にW5〜W6の誤差Δ2を生じる。   At a predetermined depth T1 of the p diffusion region 2 where the lateral diffusion width W1 is measured, the measurement location is near the bottom 2c of the p diffusion region 2 (see FIG. 12), and the pn junction 7 is greatly bent. Therefore, the lateral diffusion width W1 greatly depends on the predetermined depth T1, and if there is an error Δ1 of T5 to T6 at the predetermined depth T1 as shown in FIG. 12, the error Δ1 is enlarged and the lateral diffusion width is increased. An error Δ2 of W5 to W6 is generated in W1.

そのため、所定の深さT1の誤差が数μmの場合でも横方向拡散幅W1の誤差は十数μmと拡大される。
そのため、従来の断面から横方向拡散幅W1を精度よく計測することが困難になる。
For this reason, even when the error of the predetermined depth T1 is several μm, the error of the lateral diffusion width W1 is enlarged to several tens μm.
Therefore, it becomes difficult to accurately measure the lateral diffusion width W1 from the conventional cross section.

また、従来の方法では、平面形状が複雑なp拡散領域の所定の深さT1での横方向拡散幅W1を計測する場合には、全ての計測箇所で切断加工する必要があり、ウェハ面内分布を計測するには時間を要し効率的にできない。   Further, in the conventional method, when measuring the lateral diffusion width W1 at a predetermined depth T1 of the p diffusion region having a complicated planar shape, it is necessary to perform cutting at all the measurement points, and within the wafer surface. Measuring the distribution takes time and cannot be done efficiently.

また、特許文献1、2および3には、拡散深さが100μmを超える深い拡散領域について、ウェハを裏面から研削し、拡散領域の所定の深さでの横方向拡散幅を計測する方法については記載されていない。   Patent Documents 1, 2, and 3 describe a method of grinding a wafer from the back surface and measuring a lateral diffusion width at a predetermined depth of the diffusion region for a deep diffusion region having a diffusion depth exceeding 100 μm. Not listed.

この発明の目的は、前記の課題を解決して、100μm程度の深い拡散領域について、おもて面からの所定の深さにおける横方向拡散層幅を精度よく計測でき、また横方向拡散幅のウェハ面内分布を効率よく計測できる半導体装置に形成された拡散領域の横方向拡散幅の評価方法を提供することにある。   The object of the present invention is to solve the above-mentioned problems and to accurately measure the lateral diffusion layer width at a predetermined depth from the front surface in a deep diffusion region of about 100 μm. An object of the present invention is to provide a method for evaluating the lateral diffusion width of a diffusion region formed in a semiconductor device capable of efficiently measuring the wafer in-plane distribution.

前記の目的を達成するために、特許請求の範囲の請求項1に記載の発明によれば、第1導電型の半導体ウェハのおもて面から、ウェハ内部に向かって第2導電型の拡散領域を形成する工程と、前記半導体ウェハの裏面を研削し、前記半導体ウェハの厚さを、前記拡散領域の拡散深さより薄くするため前記半導体ウェハの裏面全域を研削し研削面の加工層を除去する工程と、前記半導体ウェハの裏面に化学的処理をして該ウェハ裏面の導電型を可視化する工程と、前記半導体ウェハの裏面に露出した拡散領域の外周上の対向する2点の間隔を計測することで、前記拡散領域の所定の深さでの横方向拡散幅を計測する工程と、を含む半導体装置に形成される拡散領域の横方向拡散幅の評価方法とする。   To achieve the above object, according to the first aspect of the present invention, the diffusion of the second conductivity type from the front surface of the semiconductor wafer of the first conductivity type toward the inside of the wafer. Forming a region, grinding the back surface of the semiconductor wafer, and grinding the entire back surface of the semiconductor wafer to remove the processed layer on the ground surface so that the thickness of the semiconductor wafer is less than the diffusion depth of the diffusion region Measuring the distance between two opposing points on the outer periphery of the diffusion region exposed on the back surface of the semiconductor wafer, and performing a chemical treatment on the back surface of the semiconductor wafer to visualize the conductivity type on the back surface of the semiconductor wafer. And measuring the lateral diffusion width at a predetermined depth of the diffusion region. The method for evaluating the lateral diffusion width of the diffusion region formed in the semiconductor device is provided.

また、特許請求の範囲の請求項2記載の発明によれば、請求項1に記載の発明において、前記半導体ウェハの研削前の前記拡散領域の拡散深さの寸法が、前記半導体ウェハの研削後の前記ウェハの厚さの寸法より大きいとよい。   Further, according to the invention of claim 2, in the invention of claim 1, the dimension of the diffusion depth of the diffusion region before grinding of the semiconductor wafer is after grinding of the semiconductor wafer. It may be larger than the thickness dimension of the wafer.

また、特許請求の範囲の請求項3記載の発明によれば、請求項1または2に記載の発明において、前記拡散領域と前記半導体基板の二次元画像が顕微鏡を介して得られ、該得られた二次元画像の前記拡散領域の横方向拡散幅を対向するpn接合の間隔で計測することで、前記拡散領域の所定の深さでの横方向拡散幅を得るとよい。   According to the invention described in claim 3, in the invention described in claim 1 or 2, a two-dimensional image of the diffusion region and the semiconductor substrate is obtained through a microscope. Further, it is preferable to obtain the lateral diffusion width at a predetermined depth of the diffusion region by measuring the lateral diffusion width of the diffusion region of the two-dimensional image at the interval between the opposing pn junctions.

また、特許請求の範囲の請求項4記載の発明によれば、請求項1〜3のいずれか一項に記載の発明において、前記拡散領域を前記半導体ウェハに複数個所形成し、前記半導体ウェハの裏面に露出した拡散領域の端部に形成されるpn接合で、対向する前記pn接合同士の間隔について、前記複数の前記拡散領域の所定の深さでの横方向拡散幅をそれぞれについて計測するとよい。   According to the invention of claim 4, in the invention of any one of claims 1 to 3, a plurality of the diffusion regions are formed in the semiconductor wafer, and the semiconductor wafer In the pn junction formed at the end of the diffusion region exposed on the back surface, the lateral diffusion width at a predetermined depth of the plurality of diffusion regions may be measured for the interval between the opposing pn junctions. .

また、特許請求の範囲の請求項5記載の発明によれば、請求項1〜4のいずれか一項に記載の発明において、前記薄くする工程につづいて、前記研削による加工層を除去する工程を有するとよい。   Moreover, according to invention of Claim 5 of Claim, in the invention as described in any one of Claims 1-4, the process of removing the process layer by the said grinding following the said thinning process It is good to have.

また、特許請求の範囲の請求項6記載の発明によれば、請求項5に記載の発明において、前記加工層を除去する工程は、研磨もしくはエッチングを用いるとよい。
また、特許請求の範囲の請求項7記載の発明によれば、請求項1〜6のいずれか一項に記載の発明において、前記化学的処理が、ステインエッチングであるとよい。
According to the invention as set forth in claim 6, the step of removing the processed layer in the invention according to claim 5 may use polishing or etching.
According to the invention described in claim 7 of the claims, in the invention described in any one of claims 1 to 6, the chemical treatment may be stain etching.

この発明によれば、深い拡散領域の基板おもて面からの所定の深さにおける横方向拡散層幅を精度よく計測でき、また横方向拡散幅のウェハ面内分布を効率よく計測できる。   According to the present invention, it is possible to accurately measure the width of the lateral diffusion layer at a predetermined depth from the front surface of the substrate in the deep diffusion region, and it is possible to efficiently measure the in-plane distribution of the lateral diffusion width.

この発明の一実施例の半導体装置に形成された拡散領域の横方向拡散幅の評価方法を説明する図であり、(a)〜(d)は工程順に示した要部工程断面図である。It is a figure explaining the evaluation method of the horizontal direction diffusion width of the diffusion area | region formed in the semiconductor device of one Example of this invention, (a)-(d) is principal part process sectional drawing shown to process order. p拡散領域2およびnウェハ3のそれぞれのステインエッチング面2b、3bを示す図である。FIG. 3 is a view showing stain etching surfaces 2b and 3b of a p diffusion region 2 and an n wafer 3, respectively. 複数のp拡散領域2を設けた薄いnウェハ3のステインエッチング面3bとp拡散領域2のステインエッチング面2bを示す図である。2 is a view showing a stain etching surface 3b of a thin n wafer 3 provided with a plurality of p diffusion regions 2 and a stain etching surface 2b of a p diffusion region 2. FIG. 半導体チップのコーナーに当たる箇所の薄いnウェハ3のステインエッチング面3bとp拡散領域2のステインエッチング面2bを示す図である。It is a figure which shows the stain etching surface 3b of the thin n wafer 3 of the location which hits the corner of a semiconductor chip, and the stain etching surface 2b of the p diffusion region 2. 裏面にV溝を形成したRB−IGBTの要部断面図である。It is principal part sectional drawing of RB-IGBT which formed V groove in the back surface. RB−IGBTの構成図であり、(a)は要部平面図、(b)は(a)のX−X線で切断した要部断面図である。It is a block diagram of RB-IGBT, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). 図6のRB−IGBTの製造方法を説明する図であり、(a)〜(c)は工程順に示した要部製造工程断面図である。It is a figure explaining the manufacturing method of RB-IGBT of FIG. 6, (a)-(c) is principal part manufacturing process sectional drawing shown to process order. p拡散領域2の拡散深さT2が小さい場合を説明する図である。It is a figure explaining the case where the diffusion depth T2 of the p diffusion region 2 is small. p拡散領域2の所定の深さT1での横方向拡散幅W1が小さい場合を説明する図である。It is a figure explaining the case where the horizontal direction diffusion width W1 in the predetermined depth T1 of the p diffusion region 2 is small. p拡散領域2の横方向拡散幅W1が大きい場合を説明する図である。It is a figure explaining the case where the horizontal direction diffusion width W1 of the p diffusion area | region 2 is large. 従来のp拡散領域の所定の深さでの横方向拡散幅を計測する評価工程(手順)を説明する図であり、(a)〜(c)は工程順に示した要部評価工程断面図である。It is a figure explaining the evaluation process (procedure) which measures the horizontal direction diffusion width in the predetermined depth of the conventional p diffusion area | region, (a)-(c) is the principal part evaluation process sectional drawing shown to the process order. is there. 従来のp拡散領域の所定の深さでの横方向拡散幅を計測誤差を説明する図である。It is a figure explaining the measurement error about the horizontal direction diffusion width in the predetermined depth of the conventional p diffusion area | region.

実施の形態を以下の実施例で説明する。
<実施例>
図1は、この発明の一実施例の半導体装置に形成された拡散領域の横方向拡散幅の評価方法を説明する図であり、同図(a)〜同図(d)は工程順に示した要部工程断面図である。以下の表記でnは導電型がn型、pは導電型がp型であることを示す。図1の評価方法は、RB−IGBTの深いp拡散領域2の所定の深さT1での横方向拡散幅W1を計測する方法について示したものである。この計測は製造プロセスにウェハを投入する前に、事前にp拡散領域2が設計通りにできるかどうかを確認するために行うものである。したがって、試験用のウェハに所定パターンでp拡散領域2を形成して、このp拡散領域2のウェハのおもて面から所定の深さにおける横方向の拡散幅を計測するものである。
Embodiments will be described in the following examples.
<Example>
FIG. 1 is a diagram for explaining a method for evaluating the lateral diffusion width of a diffusion region formed in a semiconductor device according to one embodiment of the present invention. FIG. 1 (a) to FIG. It is principal part process sectional drawing. In the following notation, n indicates that the conductivity type is n-type, and p indicates that the conductivity type is p-type. The evaluation method of FIG. 1 shows a method for measuring the lateral diffusion width W1 at a predetermined depth T1 of the deep p diffusion region 2 of the RB-IGBT. This measurement is performed in order to confirm whether or not the p diffusion region 2 can be performed as designed before putting the wafer into the manufacturing process. Therefore, the p diffusion region 2 is formed in a predetermined pattern on the test wafer, and the lateral diffusion width at a predetermined depth from the front surface of the wafer in the p diffusion region 2 is measured.

まず、同図(a)に示すように、厚さQ1の厚いnウェハ1のおもて面側に拡散深さT2の深いp拡散領域2を形成する。この厚いnウェハ1の厚さQ1は、製品を製造する際に用いるウェハの製造プロセスへの投入時の厚さである。   First, as shown in FIG. 2A, a deep p diffusion region 2 having a diffusion depth T2 is formed on the front surface side of a thick n wafer 1 having a thickness Q1. The thickness Q1 of the thick n-wafer 1 is a thickness at the time of entering a wafer manufacturing process used for manufacturing a product.

また、厚いnウェハ1の厚さQ1に形成されるp拡散領域2は、製品となるRB−IGBTの外周を囲むp拡散領域が設計通りに形成されているか否かを評価するものであるので、製品となるRB−IGBT(図7参照)のp拡散領域2と同様にマスク65の開口をWoとして形成するとよい。あるいは、所定の開口のマスクによって、p拡散領域をnウェハ1の複数個所に形成し、1つのウェハ内における、拡散のばらつきを計測するようにしてもよい。   Further, the p diffusion region 2 formed in the thickness Q1 of the thick n wafer 1 is for evaluating whether or not the p diffusion region surrounding the outer periphery of the RB-IGBT as a product is formed as designed. Similarly to the p diffusion region 2 of the RB-IGBT (see FIG. 7) to be a product, the opening of the mask 65 may be formed as Wo. Alternatively, p diffusion regions may be formed at a plurality of locations on the n wafer 1 with a mask having a predetermined opening, and the dispersion variation in one wafer may be measured.

つぎに、同図(b)に示すように、厚いnウェハ1の裏面1a側から研削し、研削による加工層を研磨もしくはエッチングによって除去して、厚さQ2の薄いnウェハ3にする。エッチングは、例えば、フッ酸(HF)と硝酸(HNO3)の水溶液を用いて行う。また、研磨は、例えば、CMP(Chemical Mechanical Polishing)法を用いて行う。 Next, as shown in FIG. 2B, grinding is performed from the back surface 1a side of the thick n-wafer 1, and a processed layer by grinding is removed by polishing or etching to form a thin n-wafer 3 having a thickness Q2. Etching is performed using, for example, an aqueous solution of hydrofluoric acid (HF) and nitric acid (HNO 3 ). The polishing is performed using, for example, a CMP (Chemical Mechanical Polishing) method.

薄いnウェハ3の厚さQ2がp拡散領域2の所定の深さT1に相当する。したがって、厚いnウェハ1の減厚工程後において、薄いnウェハ3の裏面にp拡散領域が露出していない場合は、図8に示すように、p拡散領域2が所定の深さ(T1)に達していないことになる。   The thickness Q2 of the thin n wafer 3 corresponds to a predetermined depth T1 of the p diffusion region 2. Therefore, after the thinning process of the thick n wafer 1, when the p diffusion region is not exposed on the back surface of the thin n wafer 3, the p diffusion region 2 has a predetermined depth (T1) as shown in FIG. It will not reach.

p拡散領域2が所定の深さT1に達し、さらにそれより深い所定の深さT2達している場合は、薄いnウェハ3の裏面3aにはp拡散領域2の裏面2aが露出する。この薄くなったnウェハ3の厚さQ2、すなわち研削工程(研磨・エッチング工程)によって薄化されるnウェハの厚さの精度は1μm程度以下である。つまり、横方向拡散幅W1を計測するp拡散領域2の所定の深さT1の誤差は1μm程度以下になる。   When the p diffusion region 2 reaches a predetermined depth T1 and further reaches a predetermined depth T2 deeper than that, the back surface 2a of the p diffusion region 2 is exposed on the back surface 3a of the thin n wafer 3. The thickness Q2 of the thinned n wafer 3, that is, the accuracy of the thickness of the n wafer thinned by the grinding process (polishing / etching process) is about 1 μm or less. That is, the error of the predetermined depth T1 of the p diffusion region 2 for measuring the lateral diffusion width W1 is about 1 μm or less.

ここで、厚いnウェハの厚さQ1は500μm程度であり、薄いnウェハの厚さQ2は100μm程度である。RB−IGBTの場合、nウェハの厚さは定格電圧に依存しており、定格電圧が高くなる程厚くなる。因みに、前記の厚さQ2を100μmとするのは定格電圧が600V程度の場合である。   Here, the thickness Q1 of the thick n wafer is about 500 μm, and the thickness Q2 of the thin n wafer is about 100 μm. In the case of RB-IGBT, the thickness of the n wafer depends on the rated voltage, and becomes thicker as the rated voltage becomes higher. Incidentally, the thickness Q2 is set to 100 μm when the rated voltage is about 600V.

上記の例では、深いp拡散領域の拡散深さT2を120μm程度とし、所定の深さT1すなわち薄いnウェハ3の厚さQ2は20μm程度小さい100μmとなる。
つぎに、同図(c)おいて、薄いnウェハ3をステインエッチング液5に浸漬して、nウェハ3の裏面3aをステインエッチングして、p拡散領域2の裏面2aとnウェハ3の裏面3aをステインエッチング面2b,3bにして図2に示すように可視化する。
In the above example, the diffusion depth T2 of the deep p diffusion region is about 120 μm, and the predetermined depth T1, that is, the thickness Q2 of the thin n-wafer 3 is about 100 μm, which is about 20 μm smaller.
Next, in FIG. 3C, the thin n wafer 3 is immersed in the stain etching solution 5 to stain the back surface 3a of the n wafer 3, and the back surface 2a of the p diffusion region 2 and the back surface of the n wafer 3 are then etched. 3a is made into the stain etching surfaces 2b and 3b and visualized as shown in FIG.

図2において、2つの斜線の違いはステインエッチングで生じたp拡散領域2の裏面2aとnウェハ3の裏面3aの色の違い(光学顕微鏡像)または白黒の濃淡の違い(SEM像)を示す二次元画像である。p拡散領域2とnウェハ3の境界がpn接合7である。   In FIG. 2, the difference between the two oblique lines indicates the difference in color between the back surface 2a of the p diffusion region 2 and the back surface 3a of the n wafer 3 (optical microscope image) or the difference in black and white (SEM image) caused by stain etching. It is a two-dimensional image. The boundary between the p diffusion region 2 and the n wafer 3 is a pn junction 7.

つぎに、図1(d)において、図2で示す可視化された二次元画像を用いて、対向するpn接合7の間隔W2を光学顕微鏡像6やSEM(電子顕微鏡)像などから計測する。pn接合7に挟まれた領域がp拡散領域2であり、この対向するpn接合7の間隔W2がp拡散領域2の横方向拡散幅W1である。従って、この対向するpn接合7の間隔W2を計測することで、横方向拡散幅W1を求めることができる。同図(d)は光学顕微鏡6で計測した図を示し、反射光6aで図2で示す二次元画像が得られる。   Next, in FIG. 1D, using the visualized two-dimensional image shown in FIG. 2, the interval W2 between the pn junctions 7 facing each other is measured from an optical microscope image 6 or an SEM (electron microscope) image. The region sandwiched between the pn junctions 7 is the p diffusion region 2, and the interval W <b> 2 between the opposing pn junctions 7 is the lateral diffusion width W <b> 1 of the p diffusion region 2. Accordingly, the lateral diffusion width W1 can be obtained by measuring the interval W2 between the opposing pn junctions 7. FIG. 4D shows a diagram measured with the optical microscope 6, and the two-dimensional image shown in FIG. 2 is obtained with the reflected light 6a.

前記のように、p拡散領域2の所定の深さT1は、薄いnウェハ3の厚さQ2で決まる。この薄いnウェハ3の厚さQ2の誤差は、研削と研磨またはエッチングの精度で決まり、この精度は極めて高い。そのため、薄いnウェハ3の厚さQ2の誤差は1μm程度以下、つまりp拡散領域2の所定の深さT1の誤差を1μm以下(従来方法では数μm)にすることができる。その結果、横方向拡散幅W1の誤差を数μm程度(従来方法では十数μm)と小さくすることができて、横方向拡散幅W1を精度よく計測できる。   As described above, the predetermined depth T1 of the p diffusion region 2 is determined by the thickness Q2 of the thin n wafer 3. The error in the thickness Q2 of the thin n wafer 3 is determined by the precision of grinding and polishing or etching, and this precision is extremely high. Therefore, the error of the thickness Q2 of the thin n wafer 3 can be about 1 μm or less, that is, the error of the predetermined depth T1 of the p diffusion region 2 can be 1 μm or less (several μm in the conventional method). As a result, the error in the lateral diffusion width W1 can be reduced to about several μm (ten and several μm in the conventional method), and the lateral diffusion width W1 can be accurately measured.

また、図3に示すように、nウェハ3に多数のp拡散領域2を設けて、裏面に露出したp拡散領域2bの横方向拡散幅W1を計測することで、横方向拡散幅W1のウェハ面内分布を効率よく計測することができる。   Further, as shown in FIG. 3, by providing a number of p diffusion regions 2 on the n wafer 3 and measuring the lateral diffusion width W1 of the p diffusion region 2b exposed on the back surface, the wafer having the lateral diffusion width W1 is measured. The in-plane distribution can be measured efficiently.

なお、図3では、長方形状のパターンにてp拡散領域を多数形成しているため、pn接合が対向する辺となって表出する。そこで、対向する辺の距離(間隔)を計測することで横方向の拡散幅を計測することができる。同様に他の2辺について計測を行うことができる。正方形状のパターンでも同様である。p拡散領域の形状は方形に限らず、他の形状としてもよい。例えば、円形状もしくは楕円形状のパターンとしてp拡散領域を多数形成し、裏面に露出した円形状もしくは楕円形状のp拡散領域(図示せず)の対向する2点間の距離すなわち直径(楕円の場合は短径または長径)の長さを計測するようにしてもよい。   In FIG. 3, since a large number of p diffusion regions are formed in a rectangular pattern, the pn junctions are exposed as opposing sides. Therefore, the lateral diffusion width can be measured by measuring the distance (interval) between the opposing sides. Similarly, measurement can be performed for the other two sides. The same applies to square patterns. The shape of the p diffusion region is not limited to a square, and may be other shapes. For example, a large number of p diffusion regions are formed as a circular or elliptical pattern, and the distance between two opposing points of a circular or elliptical p diffusion region (not shown) exposed on the back surface, that is, the diameter (in the case of an ellipse) May measure the length of the minor axis or the major axis).

あるいは、製品となるRB−IGBTの外周を囲むp拡散領域と同様に素子領域を囲むようないわゆる「口」文字状のp拡散領域として形成してもよい(図示せず)。裏面に露出したp拡散領域のpn接合が対向する部分の距離の計測は、上記の長方形のパターンと同様である。   Alternatively, it may be formed as a so-called “mouth” letter-shaped p diffusion region that surrounds the element region in the same manner as the p diffusion region that surrounds the outer periphery of the RB-IGBT to be a product (not shown). The measurement of the distance of the part where the pn junction of the p diffusion region exposed on the back face is the same as the above rectangular pattern.

また、図4に示すように、半導体チップのコーナーとなる箇所Bでの所定の深さでの横方向拡散幅W1の計測は、従来のような断面での計測より、本発明のような平面での計測の方がコーナー全域の計測ができるので適している。   Also, as shown in FIG. 4, the measurement of the lateral diffusion width W1 at a predetermined depth at the location B that becomes the corner of the semiconductor chip is more flat than the conventional measurement of the cross section. The measurement at is more suitable because it can measure the whole corner.

また、この発明による評価方法は、図6で説明したようなRB−IGBTの深いp拡散領域2の場合に適用できるだけでなく、他の半導体装置において、深い拡散領域の所定の深さでの横方向拡散幅を計測する場合にも適用できる。   In addition, the evaluation method according to the present invention can be applied not only to the case of the deep p diffusion region 2 of the RB-IGBT as described with reference to FIG. 6, but also to the lateral width of the deep diffusion region at a predetermined depth in other semiconductor devices. It can also be applied when measuring the directional diffusion width.

さらに、図4で示すような複雑な平面パターンの深い拡散領域の所定の深さでの横方向拡散幅を計測する場合にも適している。
また、1200Vクラスの耐圧を有するRB−IGBTでは、半導体基板の厚さが200μm程度になる。図5は、裏面に溝を形成したRB−IGBTの要部断面図であり、コレクタ電極や半導体基板の表面層に形成される耐圧終端構造は図示されていない。図中の51aはnドリフト領域であり8aはダイシングラインの側面である。n半導体基板51の厚さQ3は200μmである。このような厚さの半導体基板の一方の面(おもて面)から他方の面(裏面)へ到達するような非常に深い拡散領域を形成するのは困難である。そこで、図5に示すように、図1と同様に深さT2(例えば120μm程度)のp拡散領域2を形成し、n半導体基板の裏面3aからこのp拡散領域2に達する溝59を形成する。溝がp拡散領域2に到達することでp拡散領域2の深さはT1(例えば100μm)となる。その溝59の側面にp拡散領域2とpコレクタ領域58に接続されるp拡散層59aを形成している。このp拡散領域2とp拡散層59aが図1のp拡散領域2の働きをする。
Furthermore, it is also suitable for measuring a lateral diffusion width at a predetermined depth of a deep diffusion region having a complicated planar pattern as shown in FIG.
Further, in the RB-IGBT having a breakdown voltage of 1200 V class, the thickness of the semiconductor substrate is about 200 μm. FIG. 5 is a cross-sectional view of the main part of the RB-IGBT in which a groove is formed on the back surface, and the breakdown voltage termination structure formed on the collector electrode and the surface layer of the semiconductor substrate is not shown. In the figure, 51a is an n drift region, and 8a is a side surface of the dicing line. The thickness Q3 of the n semiconductor substrate 51 is 200 μm. It is difficult to form a very deep diffusion region that reaches from one surface (front surface) of the semiconductor substrate having such a thickness to the other surface (back surface). Therefore, as shown in FIG. 5, a p diffusion region 2 having a depth T2 (for example, about 120 μm) is formed as in FIG. 1, and a groove 59 reaching the p diffusion region 2 from the back surface 3a of the n semiconductor substrate is formed. . When the trench reaches the p diffusion region 2, the depth of the p diffusion region 2 becomes T1 (for example, 100 μm). A p diffusion layer 59 a connected to the p diffusion region 2 and the p collector region 58 is formed on the side surface of the groove 59. The p diffusion region 2 and the p diffusion layer 59a function as the p diffusion region 2 in FIG.

この場合もp拡散領域2の所定の深さでの横方向拡散幅W1を正確に把握する必要があり、本発明が適用できる。すなわち、図1に示した工程と同様にp拡散領域2を形成し、溝59が到達する予定の深さ(n半導体基板の厚さ)となるまで研削・研磨(エッチング)を行う。そして、裏面に露出したpn接合の間隔W1を計測することで、n半導体基板のおもて面から所定の深さにおけるp拡散領域の横方向拡散幅W1を計測できる。つまり、RB−IGBTを形成した際に、p拡散領域2に溝59が到達してp拡散領域2とp拡散層59が確実に接続されるか否かを評価することができる。   Also in this case, it is necessary to accurately grasp the lateral diffusion width W1 at a predetermined depth of the p diffusion region 2, and the present invention can be applied. That is, the p diffusion region 2 is formed in the same manner as in the process shown in FIG. 1, and grinding and polishing (etching) are performed until the groove 59 reaches a depth (the thickness of the n semiconductor substrate). Then, by measuring the interval W1 of the pn junction exposed on the back surface, the lateral diffusion width W1 of the p diffusion region at a predetermined depth from the front surface of the n semiconductor substrate can be measured. That is, it can be evaluated whether or not the trench 59 reaches the p diffusion region 2 and the p diffusion region 2 and the p diffusion layer 59 are securely connected when the RB-IGBT is formed.

なお、1200Vクラスの耐圧を有するRB−IGBTを600Vクラスと同様に、溝59を形成しないでp拡散領域2を裏面3aに達するように形成した場合も本発明を適用することで同様の効果が得られる。   In the case where an RB-IGBT having a breakdown voltage of 1200 V class is formed so that the p diffusion region 2 reaches the back surface 3a without forming the groove 59 as in the 600 V class, the same effect can be obtained by applying the present invention. can get.

また、上記の実施形態では、p型の拡散領域の所定深さにおける横方向拡散幅を計測する場合を例に説明した。本発明によれば、研削して裏面に露出したnp接合の境界部を計測の対象としているので、反対の導電型、すなわちn型の拡散領域を形成した場合にも、この拡散領域の所定深さにおける横方向拡散幅を計測することができる。   In the above-described embodiment, the case where the lateral diffusion width at a predetermined depth of the p-type diffusion region is measured has been described as an example. According to the present invention, the boundary portion of the np junction that has been ground and exposed on the back surface is targeted for measurement. Therefore, even when an opposite conductivity type, that is, an n-type diffusion region is formed, a predetermined depth of the diffusion region is formed. The lateral diffusion width can be measured.

1 厚いウェハ
1d ステインエッチング面(厚いウェハ1の断面)
1a,2a,3a 裏面
2 p拡散領域
2b ステインエッチング面(p拡散領域の裏面2a)
2c 底部(p拡散領域2)
2d ステインエッチング面(p拡散領域の断面)
3 薄いウェハ
3b ステインエッチング面(nウェハの裏面3a)
5 ステインエッチング液
6 光学顕微鏡
6a 反射光
7 pn接合
8 ダイシングライン
8a 側面
51 n半導体基板
51a nドリフト領域
52 pウェル領域
53 nエミッタ領域
54 ゲート絶縁膜
55 ゲート電極
56 層間絶縁膜
57 エミッタ電極
58 pコレクタ領域
59 溝
59a p拡散層
60 表面構造
61 損傷(クラック)
62 活性領域
63 空乏層
65 マスク
T1 p拡散領域の所定の深さ
T2 p拡散領域の拡散深さ
W1 所定の深さでの横方向拡散幅
W2 対向するpn接合の間隔
Q1 厚いウェハ1の厚さ
Q2 薄いウェハ3の厚さ
Δ1 所定の深さの誤差
Δ2 横方向拡散幅の誤差
1 Thick wafer 1d Stain etched surface (cross section of thick wafer 1)
1a, 2a, 3a Back surface 2 p diffusion region 2b stain etching surface (back surface 2a of p diffusion region)
2c Bottom (p diffusion region 2)
2d Stain etched surface (cross section of p diffusion region)
3 Thin wafer 3b Stain etched surface (n wafer back surface 3a)
5 stain etching liquid 6 optical microscope 6a reflected light 7 pn junction 8 dicing line 8a side surface 51 n semiconductor substrate 51a n drift region 52 p well region 53 n emitter region 54 gate insulating film 55 gate electrode 56 interlayer insulating film 57 emitter electrode 58 p Collector region 59 Groove 59a p diffusion layer 60 Surface structure 61 Damage (crack)
62 active region 63 depletion layer 65 mask T1 predetermined depth of p diffusion region T2 diffusion depth of p diffusion region W1 lateral diffusion width at predetermined depth W2 spacing between opposing pn junctions Q1 thickness of thick wafer 1 Q2 Thickness of thin wafer 3 Δ1 Predetermined depth error Δ2 Lateral diffusion width error

Claims (7)

第1導電型の半導体ウェハのおもて面から、ウェハ内部に向かって第2導電型の拡散領域を形成する工程と、
前記半導体ウェハの裏面全域を研削し、前記半導体ウェハの厚さを、前記拡散領域の拡散深さより薄くするため前記半導体ウェハの裏面を研削し研削面の加工層を除去する工程と、
前記半導体ウェハの裏面に化学的処理をして該ウェハ裏面の導電型を可視化する工程と、
前記半導体ウェハの裏面に露出した拡散領域の外周上の対向する2点の間隔を計測することで、前記拡散領域の所定の深さでの横方向拡散幅を計測する工程と、
を含むことを特徴とする半導体装置に形成される拡散領域の横方向拡散幅の評価方法。
Forming a diffusion region of the second conductivity type from the front surface of the first conductivity type semiconductor wafer toward the inside of the wafer;
Grinding the entire back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to make the thickness of the semiconductor wafer thinner than the diffusion depth of the diffusion region, and removing the processing layer of the ground surface;
Visualizing the conductivity type of the backside of the semiconductor by chemically treating the backside of the semiconductor wafer;
Measuring a lateral diffusion width at a predetermined depth of the diffusion region by measuring an interval between two opposing points on the outer periphery of the diffusion region exposed on the back surface of the semiconductor wafer;
A method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device.
前記半導体ウェハの研削前の前記拡散領域の拡散深さの寸法が、前記半導体ウェハの研削後の前記ウェハの厚さの寸法より大きいことを特徴とする請求項1に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。   2. The semiconductor device according to claim 1, wherein a dimension of a diffusion depth of the diffusion region before grinding of the semiconductor wafer is larger than a dimension of a thickness of the wafer after grinding of the semiconductor wafer. Evaluation method of lateral diffusion width of diffusion region. 前記拡散領域と前記半導体基板の二次元画像が顕微鏡を介して得られ、該得られた二次元画像の前記拡散領域の横方向拡散幅を対向するpn接合の間隔で計測することで、前記拡散領域の所定の深さでの横方向拡散幅を得ることを特徴とする請求項1または2のいずれか一項に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。   A two-dimensional image of the diffusion region and the semiconductor substrate is obtained through a microscope, and by measuring a lateral diffusion width of the diffusion region of the obtained two-dimensional image at an interval between opposing pn junctions, the diffusion 3. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 1, wherein a lateral diffusion width at a predetermined depth of the region is obtained. 前記拡散領域を前記半導体ウェハに複数個所形成し、
前記半導体ウェハの裏面に露出した拡散領域の端部に形成されるpn接合で、対向する前記pn接合同士の間隔について、前記複数の前記拡散領域の所定の深さでの横方向拡散幅をそれぞれについて計測することを特徴とする請求項1〜3のいずれか一項に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。
Forming a plurality of diffusion regions in the semiconductor wafer;
In the pn junction formed at the end of the diffusion region exposed on the back surface of the semiconductor wafer, the lateral diffusion width at a predetermined depth of the plurality of diffusion regions is set for the interval between the pn junctions facing each other. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to any one of claims 1 to 3, wherein:
前記薄くする工程につづいて、前記研削による加工層を除去する工程を有することを特徴とする請求項1〜4のいずれか一項に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。   5. The lateral diffusion width of the diffusion region formed in the semiconductor device according to claim 1, further comprising a step of removing a processed layer by the grinding following the thinning step. 6. Evaluation method. 前記加工層を除去する工程は、研磨もしくはエッチングを用いることを特徴とする請求項5に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。   6. The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 5, wherein the step of removing the processed layer uses polishing or etching. 前記化学的処理が、ステインエッチングであることを特徴とする請求項1〜6のいずれか一項に記載の半導体装置に形成される拡散領域の横方向拡散幅の評価方法。
The method for evaluating a lateral diffusion width of a diffusion region formed in a semiconductor device according to claim 1, wherein the chemical treatment is stain etching.
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