CN110034098B

CN110034098B - Semiconductor structure and forming method thereof

Info

Publication number: CN110034098B
Application number: CN201810029861.0A
Authority: CN
Inventors: 舒强
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2020-11-27
Anticipated expiration: 2038-01-12
Also published as: CN110034098A

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a device surface, and the device surface comprises a device area and a mark area; forming a first device structure and a second device structure in the device region, and forming a mark structure in the mark region, wherein the mark structure comprises a first rotation center, and after the mark structure rotates for a first angle around a straight line which is perpendicular to the device surface and passes through the first rotation center, the formed structure is superposed with the mark structure, and the first angle is larger than zero and smaller than or equal to 180 degrees; and forming a first patterned layer on the device region, and forming a test mark in the mark region. The forming method can improve the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

In the conventional semiconductor manufacturing process, a pattern is usually formed on a plurality of layers of films to form a semiconductor device with certain functions. The patterns of different layers have a certain alignment relationship, and usually a method of forming a registration mark on a wafer is adopted, and the alignment is realized through the registration mark.

In the prior art, due to the influence of factors such as a wafer offset vector or focusing accuracy in a photolithography process, an exposed pattern has problems in the aspects of offset vector, rotation, scaling or orthogonality in the exposure process of a photoresist. Therefore, in the process of forming a semiconductor structure, the exposure error between different unit areas formed on the same layer of photoresist needs to be measured by using the photolithography alignment mark, so as to ensure the overlay accuracy.

However, the forming method of the semiconductor structure in the prior art is complicated.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can simplify the forming method of the semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a device surface, and the device surface comprises a device area and a mark area; forming a first device structure and a second device structure in the device area, and forming a mark structure in the mark area, where the mark structure includes a first rotation center, the mark structure rotates around a straight line perpendicular to the device surface and passing through the first rotation center by a first angle, the formed structure coincides with the mark structure, the first angle is greater than zero and less than or equal to 180 degrees, the mark structure includes a plurality of mark portions uniformly distributed around the first rotation center, the mark portion includes a branch group, a projection pattern of the branch group on the device surface is in a bar shape, the branch group includes a first branch portion and a second branch portion, an arrangement direction of the projection pattern of the first branch portion and the second branch portion on the device surface is parallel to an extension direction of the projection pattern of the branch group on the device surface, forming the first branch portion in a process of forming the first device structure, and forming the second mark in a process of forming the second device structure; after the mark structure is formed, a test mark is formed in the mark area in the process of forming the first graphic layer, the test mark is formed in the process of forming the first graphic layer, and the projection of the center of the projection pattern of the test mark on the device surface relative to the first rotation center on the device surface has a first offset vector.

Optionally, the number of the branch groups in each mark portion is plural, and the branch groups are arranged in parallel.

Optionally, the number of the branch groups is 5 to 15; the distance between the centers of the adjacent branch parts is 0.9-1.1 μm; the width of the branch group is 0.45-0.55 μm.

Optionally, the number of each branch group is one, the branch group is rectangular, and the length of the branch group is 18 μm to 22 μm; the width of the branch group is 0.9-11 μm.

Optionally, the first branch portion is rectangular, the second branch portion is rectangular, and adjacent sides of the first branch portion and the second branch portion are equal in length.

Optionally, before forming the first graphic layer and the test mark, the method further includes: forming a fourth device structure in the device region; each branch group further includes: a third branch portion of each branch group for marking the fourth device structure; the arrangement direction of the projection patterns of the first branch part, the second branch part and the third branch part on the device surface is parallel to the extension direction of the projection patterns of the branch part group on the device surface.

Optionally, the number of the third branches in a single branch group is 1 to 3.

Optionally, the first device structure is located in the device region substrate, and the first branch portion is located in the substrate; or the first device structure is located on the substrate, and the first branch is located on the substrate; the second device structure is located in the device region substrate, and the second branch portion is located in the substrate; or the second device structure is located on the substrate, and the second branch portion is located on the substrate.

Optionally, a distance from the top of the first branch to the device surface is equal to a distance from the top of the second branch to the device surface.

Optionally, the first branch portion is located in the mark region substrate, and the second branch portion is located in the mark region substrate; or before forming the mark structure, the method further comprises: forming a first functional layer on the substrate; the first branch is a first opening in the first functional layer; the second branch is a second opening in the first functional layer.

Optionally, a line connecting the center of the marking part and the first rotation center is perpendicular to the extending direction of the branch group; or the connecting line of the center of the marking part and the first rotation center is parallel to the extending direction of the branch group; or a connecting line between the center of the marking part and the first rotating center and the extending direction of the branch part group form an acute included angle.

Optionally, the test mark includes a second rotation center, after the test mark rotates a second angle around a straight line perpendicular to the device surface and passing through the second rotation center, a formed structure coincides with the test mark, the second angle is greater than zero and less than or equal to 180 degrees, the test mark includes a plurality of test portions, the test portions are uniformly distributed around the second rotation center, and each test portion includes one or more test branch portions.

Optionally, the number of the test parts in a single test mark is equal to the number of the mark parts in a single mark structure, and each test part corresponds to each mark part one by one; the number of the test branch parts in the single test part is equal to that of the branch part groups in the single marking part, and the test branch parts in the test part and the marking part which correspond to each other respectively correspond to the branch part groups; the test branch part is strip-shaped, and the extending direction of the test branch part is parallel to the extending direction of the corresponding branch part group.

Optionally, after forming the test mark and the first pattern layer, the method further includes: forming a first graphic layer in a graphic mode on the substrate of the device area, and forming a test mark on the substrate of the mark area; detecting a first offset vector of the test mark center from the first rotation center in a direction parallel to the device face; acquiring a second offset vector of the first graphic layer according to the first offset vector; removing the first graphic layer and the test mark; after removing the first graphic layer and the test mark, forming a first graphic layer on the substrate of the device area according to the second offset vector; forming a third device structure in the device area by taking the second graphic layer as a mask; and after the third device structure is formed, removing the second graphic layer.

Optionally, forming a second functional layer on the functional region and the device region substrate; the first graphic layer, the second graphic layer and the first mark are positioned on the second functional layer; the step of forming the third device structure comprises: processing the second functional layer by taking the second graphic layer as a mask, and forming a third device structure on the device area substrate; alternatively, the step of forming the third device structure comprises: and processing the device area substrate by taking the second graphic layer as a mask, and forming a third device structure in the device area substrate.

Optionally, the processing technology includes: an etching process or an ion implantation process.

Optionally, the number of the marker structures is greater than or equal to three; the first centers of rotation of at least three of the plurality of marker structures are not collinear.

Accordingly, the present invention also provides a semiconductor structure comprising: a substrate comprising a device side comprising a device region and a marker region; a first device structure and a second device structure located in the device region; the marking structure is positioned in the marking area and comprises a first rotation center, the marking structure bypasses the first rotation center, a straight line perpendicular to the device surface is rotated by a first angle and is coincided with the marking structure, the first angle is larger than zero and smaller than or equal to 180 degrees, the marking structure comprises a plurality of marking parts, each marking part comprises a branch group, the projection graph of the branch group on the device surface is in a strip shape, each branch group comprises a first branch part and a second branch part, the arrangement direction of the projection graph of the first branch part and the second branch part on the device surface is parallel to the extension direction of the projection graph of the branch group on the device surface, the first branch part of each branch group is used for marking the first device structure, and the second branch part of each branch group is used for marking the second device structure; a test mark located in the substrate mark area, wherein the projection pattern center of the test mark on the device surface has a first offset vector relative to the projection of the first rotation center on the device surface; and the first pattern layer is positioned in the substrate device area.

Optionally, the method further includes: a fourth device structure located in the device region; each branch group further includes: a third branch portion of each branch group for marking the fourth device structure; the arrangement direction of the projection patterns of the first branch part, the second branch part and the third branch part on the device surface is parallel to the extension direction of the projection patterns of the branch part group on the device surface.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, before the first graphic layer and the test mark are formed, the mark structure is formed in the mark area. All the first branch parts in the marking structure are used for marking the first device structure, all the second branch parts in the marking structure are used for marking the second device structure, and the marking structure comprises the first branch parts and the second branch parts, so that the first rotation center of the marking structure can mark the positions of the first device structure and the second device structure. Therefore, by measuring the offset vector of the test mark relative to the first rotation center, the combined information of the offset vectors of the first graphic layer relative to the first device structure and the second device structure can be obtained, so that the method for aligning the third device structure with the first device structure and the second device structure can be simplified, and the method for forming the semiconductor structure can be simplified.

Further, the distance from the top of the first branch to the device surface is equal to the distance from the top of the second branch to the device surface. In the process of forming the second pattern layer, it is necessary to detect an offset vector between the test mark and the mark structure. The distance from the top of the first branch part to the device surface is equal to the distance from the top of the second branch part to the device surface, and no semiconductor material is arranged between the first branch part and the second branch part in the direction perpendicular to the device surface, so that the detection of the offset vector between the test mark and the mark structure is not easily influenced, and the detection precision can be improved.

Drawings

FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;

FIGS. 4-13 are schematic structural diagrams illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 14-16 are schematic structural views illustrating steps of another embodiment of a method for forming a semiconductor structure according to the present invention;

FIG. 17 is a schematic structural diagram of one embodiment of a semiconductor structure of the present invention;

FIG. 18 is a schematic structural diagram of another embodiment of a semiconductor structure in accordance with the present invention.

Detailed Description

As described in the background, the prior art forms semiconductor structures with low overlay accuracy.

Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a device region B and a mark region a; forming a first active region 101 in the device region B substrate 100, and forming a first mark 11 in the mark region a substrate, wherein the first mark 11 is used for marking the first active region 101; a second active region 102 is formed in the device region B substrate 100, and a second mark 12 for marking the second active region 102 is formed in the mark region a substrate 100.

Referring to fig. 2 and 3, fig. 3 illustrates a gate layer 110 formed on the substrate 100 in the device region B and the tag region a along a cutting line C-C' in fig. 2; forming a photoresist layer on the gate layer 110 in the device region B and the mark region a; and exposing the photoresist layer, forming a patterned photoresist 111 on the device region B gate layer 110, and forming a third mark 20 on the mark region A gate layer.

And etching the gate layer 110 by taking the photoresist 111 as a mask to form a gate structure.

Wherein the third mark 20 and the photoresist 111 are formed through the same exposure process, and the photoresist 111 is used as a mask for forming a gate structure, so that the third mark 20 can be used for marking the position of the gate structure, and the positional relationship between the gate structure and the first active region 101 can be obtained by detecting the positional relationship between the third mark 20 and the first mark 11; by detecting the positional relationship between the third mark 20 and the second mark 12, the positional relationship between the gate structure and the second active region 102 can be acquired, so that the offset vector of the gate structure can be reduced.

Before etching the gate layer 110, the forming method further includes: detecting a first offset vector of the center of the third mark 20 with respect to the center of the first mark 11; detecting a second offset vector of the center of the third mark 20 with respect to the center of the second mark 12; obtaining a third offset vector of the third mark 20 from the first offset vector and the second offset vector; and adjusting the position of the photoresist 111 according to the third offset vector. Therefore, the forming method needs to measure both the first offset vector and the second offset vector to obtain the third offset vector, which results in a complex forming method of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: and forming a first device structure and a second device structure in the device region, and forming a mark structure in the mark region, wherein the mark structure comprises a first rotation center, and the mark structure bypasses the first rotation center and is perpendicular to a rotating shaft of the device surface to rotate by a first angle to coincide with the rotating shaft. The forming method can improve the performance of the formed semiconductor structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 4, a substrate 200 is provided, where the substrate 200 includes a device surface, and the device surface includes a device region N and a mark region M.

The substrate 200 is made of a semiconductor structure such as silicon, germanium, silicon-on-insulator, germanium-on-insulator, or silicon germanium-on-insulator.

Subsequently forming a first device structure and a second device structure in the device area N, and forming a mark structure in the mark area M, where the mark structure includes a first rotation center, the mark structure rotates around a straight line perpendicular to the device surface and passing through the first rotation center by a first angle, the formed structure coincides with the mark structure, the first angle is greater than zero and less than or equal to 180 degrees, the mark structure includes a plurality of mark portions uniformly distributed around the first rotation center, the mark portion includes a branch group, a projection pattern of the branch group on the device surface is in a bar shape, each branch group includes a first branch portion and a second branch portion, an arrangement direction of the projection pattern of the first branch portion and the second branch portion on the device surface is parallel to an extension direction of the projection pattern of the branch group on the device surface, the first branch portion is formed in a process of forming the first device structure, and the second mark is formed in a process of forming the second device structure.

In this embodiment, the steps of forming the first device structure, the second device structure, and the mark structure are as shown in fig. 5 to 8.

Referring to fig. 5 and 6, fig. 6 is a top view of fig. 5, fig. 5 is a cross-sectional view of fig. 6 along a cutting line 1-2, fig. 5 is a schematic diagram of a subsequent step based on fig. 4, in which the first device structure 201 is formed in the device region N of the substrate 200, and the first branch portion 211 is formed in the mark region M of the substrate 200.

In this embodiment, the first device structure 201 serves as an active region of a semiconductor structure. The first device structure 201 is located in the device region N substrate 200. In other embodiments, the first device structure serves as a gate of a semiconductor structure, the first device structure being located on the substrate.

In the present embodiment, the first branch portion 211 among the plurality of mark portions constitutes a first mark. The first mark is used to mark the position of the first device structure 201.

If the number of the marking parts in the marking structure is too small, the rotation center of the marking structure is not favorably determined; if the number of the marking parts in the marking structure is too large, the process difficulty is easily increased. The number of the marking parts in the marking structure is 3-12.

Specifically, in this embodiment, the number of the marker portions in the marker structure is four, and the first bean is 90 degrees. The four marking parts are distributed in a central symmetry mode. In other embodiments, the number of marker portions in the marker structure is other values, such as 3, 6, 8, or 12.

In this embodiment, the number of the first branch portions 211 in each mark portion is one. In other embodiments, the number of each marker portion may be plural.

In this embodiment, the first supporting portion 211 is rectangular. In other embodiments, the first leg may be square.

If the width of the first leg 211 is too large or the length of the first leg 211 is too large, the integration level is easily reduced; if the width of the first branch 211 is too small, or the length of the first branch 211 is too small, the difficulty of measuring the first offset vector subsequently is easily increased. Specifically, in the present embodiment, the width of the first leg 211 is 0.9 μm to 11 μm, and the length of the first leg 211 is 4.5 μm to 5.5 μm.

In this embodiment, the first mark is an opening in the substrate 200. In other embodiments, the first mark may also be a protrusion on the surface of the substrate.

The steps of forming the first device structure 201 and first mark include: forming a patterned first mask layer on the substrate 200, wherein the first mask layer exposes a part of the device surface of the device region N and a part of the device surface of the mark region M; performing first ion implantation on the device region N substrate 200 by taking the first mask layer as a mask, and implanting first ions into the substrate 200 to form a first device structure 201; and performing first etching on the second marking area M substrate by using the first mask layer as a mask, and forming a first support part 211 in the device area N substrate 200.

The step of forming the mask layer includes: forming a first initial mask layer on the substrate 200; forming a first patterned photoresist on the first initial mask layer; and etching the first initial mask layer by taking the first photoresist as a mask to form a first mask layer.

Before the first ion implantation, the method further comprises: forming a first pattern film on the substrate 200 in the mark region M, wherein the first ion implantation further uses the first pattern film as a mask; and removing the first pattern film after the first ion implantation.

Before the first etching, the method further comprises the following steps: forming a second pattern film on the device region N substrate 200, wherein the second pattern film is also used as a mask in the first etching; and removing the second graphic film after the first etching.

In this embodiment, the first etching process includes a dry etching process. The dry etching process has a good line width control effect, and can accurately control the size of the pattern in the first mask layer.

The first ion implantation is used to implant first ions in the substrate 200, thereby increasing the conductive properties of the substrate 200. In this embodiment, the first ions are P-type ions, such as: boron ions or BF₂ ⁺Ions; alternatively, the first ions are N-type ions, such as phosphorous ions or arsenic ions.

In other embodiments, the gate is located on the substrate. The step of forming the first device structure comprises: forming a first functional layer on the liner; and etching the first functional layer to form a first device structure on the substrate device area. The first device structure is used to form a gate.

Alternatively, the first device structure may also be a first doped layer located in the substrate. The first doped layer is used for forming a source region or a drain region of the MOS transistor; or the first doping layer is used for forming the anode or the cathode of the diode; or the first doping layer is used for forming a base electrode, a collector electrode or an emitter electrode of the triode. The first device can also be a first isolation structure located in the substrate, and the first isolation structure is used for realizing isolation between different regions in a device region.

In other embodiments, the first leg is on the substrate and the first device structure is on the substrate. The step of forming the first mark and the first device structure comprises: forming a first device layer on the substrate; and etching the first device layer, removing part of the first device layer in the device area, removing part of the first device layer in the mark area, forming a first device structure on the substrate in the device area, and forming a first mark on the substrate in the mark area.

Alternatively, before forming the mark structure, the forming method further includes: forming a first functional layer on the substrate; the first branch portion is a first opening in the first functional layer. The steps of forming the marker structure, the first device structure and the second device structure include: and etching the first functional layer, forming a first device structure on the device area substrate, and forming a first branch part in the first functional layer of the mark area. And etching the first functional layer in the device area in the process of etching the first functional layer in the mark area, and removing part of the first functional layer in the device area to form a first device structure. The first device structure serves as a gate for the formed semiconductor structure.

Referring to fig. 7 and 8, fig. 8 is a top view of fig. 7, fig. 7 is a cross-sectional view of fig. 8 along a cutting line 3-4, fig. 7 is a schematic diagram of a subsequent step based on fig. 5, a second device structure 202 is formed in the device region N, a second branch 212 is formed in the mark region M of the substrate 200, and an arrangement direction of the first branch 211 and the second branch 212 in the same branch group is parallel to an extension direction of the branch group.

In this embodiment, the second device structure 202 is located in the device region N of the substrate 200, and the second device structure 202 is used as an active region of the formed semiconductor structure. In other embodiments, the second device structure may also be located on the substrate.

The step of forming the second device structure 202 includes: forming a patterned second photoresist on the substrate 200, wherein the second photoresist exposes a part of the device surface of the device region N; and performing second ion implantation on the substrate 200 by using the second photoresist as a mask, and implanting second ions into the substrate 200 to form a second device structure 202.

The second ion implantation is used to implant second ions in the substrate 200, thereby increasing the conductivity properties of the substrate 200. In this embodiment, the second ions are P-type ions, such as: boron ions or BF₂ ⁺Ions; alternatively, the second ion is an N-type ion, such as a phosphorous ion or an arsenic ion.

In other embodiments, the gate is located on the substrate. The step of forming the second device structure comprises: forming a second functional layer on the substrate; and etching the second functional layer to form a second device structure on the substrate device area. The second device structure is used to form a gate.

Alternatively, the second device structure may also be a second doped layer located in the substrate. The second doped layer is used for forming a source region or a drain region of the MOS transistor; or the second doped layer is used for forming the anode or the cathode of the diode; or the doped layer is used for forming a base electrode, a collector electrode or an emitting electrode of the triode. The second device may also be a second isolation structure located in the substrate, the second isolation structure being used to achieve isolation between different regions in the device region.

In this embodiment, the second device structure 202 is in contact with the first device structure 201. In other embodiments, the second device structure may not be in contact with the first device structure.

In this embodiment, the second branch portion 212 of all the mark portions in the mark structure constitutes a second mark. The second mark is used to mark the location of the second device structure 202.

In this embodiment, the position of the second device structure 202 is controlled by aligning the first mark with the second mark during the process of forming the second device structure 202.

In this embodiment, the number of the second branch portions 212 in a single marking portion is one. In other embodiments, the number of the second branch portions in a single marking portion may be plural.

In this embodiment, the second branch portion 212 is rectangular. In other embodiments, the second leg may be square.

In this embodiment, the second branch portion 212 is in contact with the first branch portion 211. In other embodiments, the second leg is not in contact with the first leg.

In this embodiment, a line connecting the center of the marking portion and the first rotation center is perpendicular to the extending direction of the branch group. Specifically, in this embodiment, if a single marking portion includes a branch group, a line connecting the center of the branch group and the first rotation center is perpendicular to the extending direction of the branch group.

In other embodiments, a line connecting the center of the marking portion and the first rotation center is parallel to the extending direction of the branch group; or, a line connecting the center of the mark portion and the first rotation center and the extending direction of the branch portion group have an acute included angle, for example: the included angle between the connecting line of the mark branch part center and the first rotating center and the extending direction of the branch part group is 45 degrees, 30 degrees or 60 degrees.

In this embodiment, the length direction of the second branch portion 212 is parallel to the extending direction of the branch portion group. The dimension of the set of branches in the direction of extension thereof is the sum of the lengths of the first branch 211 and the second branch 212.

If the size of the branch group in the extending direction thereof is too large, or the length of the second branch portion 212 is too large, the integration is easily reduced; if the dimension of the branch group along the extending direction is too small, or the length of the second branch 212 is too small, the difficulty of subsequently measuring the first offset vector is easily increased. Specifically, in the present embodiment, the size of the branch group in the extending direction thereof is 9 μm to 11 μm.

If the width of the second branch portion 212 is too large, or the length of the second branch portion 212 is too large, the integration level is easily reduced; if the width of the second branch portion 212 is too small, or the length of the second branch portion 212 is too small, the difficulty of subsequently measuring the first offset vector is easily increased. Specifically, in the present embodiment, the width of the second branch portion 212 is 0.9 μm to 11 μm, and the length of the second branch portion 212 is 4.5 μm to 5.5 μm.

In this embodiment, the second mark is an opening in the substrate 200. In other embodiments, the second mark may also be a protrusion on the surface of the substrate.

The steps of forming the second device structure 202 and second indicia include: forming a patterned second mask layer on the substrate 200, wherein the second mask layer exposes a part of the device surface of the device region N and a part of the device surface of the mark region M; performing second ion implantation on the device region N substrate 200 by taking the second mask layer as a mask, and implanting second ions into the substrate 200 to form a second device structure 202; and performing second etching on the mark region M substrate 200 by taking the second mask layer as a mask, and forming a second branch part 212 in the device region N substrate 200.

The step of forming the mask layer includes: forming a second initial mask layer on the substrate 200; forming a second patterned photoresist on the second initial mask layer; and etching the second initial mask layer by taking the second photoresist as a mask to form a second mask layer.

In this embodiment, the second etching process includes a dry etching process. The dry etching process has a good line width control effect, and can accurately control the size of the pattern in the second mask layer.

In other embodiments, the second leg is on the substrate and the second device structure is on the substrate. The step of forming the second mark and the second device structure comprises: forming a second device layer on the substrate; and etching the second device layer, removing part of the second device layer in the device area, removing part of the second device layer in the mark area, forming a second device structure on the substrate in the device area, and forming a second mark on the substrate in the mark area.

Alternatively, before forming the mark structure, the forming method further includes: forming a first functional layer on the substrate; the second branch portion is a second opening in the first functional layer. Specifically, the step of forming the second branch portion and the second device structure includes: and etching the first functional layer, forming a second branch part in the first functional layer of the mark area, removing part of the first functional layer of the device area, and forming a second device structure on the substrate of the device area. And etching the first functional layer in the device area in the process of etching the first functional layer, and removing part of the first functional layer in the device area to form a second device structure. The second device structure serves as a gate for the formed semiconductor structure.

In this embodiment, the distance from the top of the first branch portion 211 to the device surface is equal to the distance from the top of the second branch portion 212 to the device surface. The distance from the top of the first branch 211 to the device surface is equal to the distance from the top of the second branch 212 to the device surface, and the first branch 211 and the second branch 212 are located in the same semiconductor layer, so that in the subsequent process of measuring the first offset vector, the semiconductor material between the first branch 211 and the second branch 212 is not easy to influence the measurement result, and the measurement accuracy can be increased.

The number of the mark structures is more than or equal to three, and the first rotation centers of at least three mark structures in the plurality of mark structures are not collinear.

The number of the mark structures is larger than or equal to three, and the first rotation centers of at least three mark structures in the plurality of mark structures are not collinear, so that the first rotation centers of the plurality of mark structures can determine the enlargement, the reduction, the rotation and the translation of the graph in the subsequent second graph layer along any direction parallel to the device surface.

In other embodiments, before forming the first graphic layer and the test mark, the method further includes: forming a fourth device structure in the device region; each branch group further includes: a third branch portion of each branch group for marking the fourth device structure; the arrangement direction of the first branch part, the second branch part and the third branch part is parallel to the extending direction of the projection pattern of the branch part group on the device surface. The number of the third branch parts in each branch part group is 1 to 3.

In this embodiment, the first angle is 90 °, and the projection pattern of the mark structure on the device surface is a centrosymmetric pattern. In other embodiments, the first angle is 30 °, 45 °, 60 °, or 120 °.

Referring to fig. 9, a second functional layer 220 is formed on the substrate 200.

The second functional layer 220 is used for the subsequent formation of a third device structure.

In this embodiment, a third device structure formed subsequently is located on the substrate 200, and before the first pattern layer and the third mark are formed subsequently, the method further includes: a second functional layer 220 is formed on the substrate 200. In other embodiments, the third device structure may also be located in the substrate, and the method of forming does not include the step of forming the second functional layer.

In this embodiment, the material of the second functional layer 220 is polysilicon or metal.

Referring to fig. 10 and fig. 11, fig. 10 is a cross-sectional view of fig. 11 along a cutting line 5-6, fig. 11 is a top view of fig. 10, fig. 10 is a schematic diagram of a subsequent step on the basis of fig. 8, in fig. 11, omitting the functional layer 220, forming a patterned first pattern layer 230 on the device region N, and forming a test mark 213 in the mark region M during the process of forming the first pattern layer 230, wherein a projected pattern center of the test mark 213 on the device surface has a first offset vector on the device surface with respect to the first rotation center.

By a first offset vector of the center of the projected pattern of the test mark 213 on the device plane relative to the first rotation center on the device plane, the position of the first pattern layer 230 relative to the first device structure 201 and the second device structure 202 can be determined, so that the third device structure 240 can be aligned with the first device structure 201 and the second device structure 202, and the performance of the formed semiconductor structure can be improved.

It should be noted that all the first branches 211 in the mark structure are used for marking the first device structure 201, and all the second branches 212 in the mark structure are used for marking the second device structure 202, and since the mark structure includes the first branches 211 and the second branches 212, the first rotation center of the mark structure can mark the positions of the first device and the second device. Therefore, by measuring the offset vector of the test structure and the first rotation center, the combination information of the offset vectors of the first pattern layer 230 relative to the first device structure 201 and the second device structure 202 can be obtained, so that the method for aligning the third device structure 240 with the first device structure 201 and the second device structure 202 can be simplified, and the method for forming the semiconductor structure can be simplified.

In this embodiment, the first graphic layer 230 is located on the substrate 200; the test marks 213 are located on the substrate 200.

After forming the first pattern layer 230 and the test mark 213, the forming method further includes: detecting a first offset vector of the test mark center from the first rotation center in a direction parallel to the device face; acquiring a second offset vector of the graphic film according to the first offset vector; removing the first graphic layer 230 and the test marks; after removing the first pattern layer 230 and the test mark, a second pattern layer is formed on the device region N substrate 200 according to the second offset vector.

In other embodiments, during the forming of the second pattern layer, a correction test mark is formed on the mark region M substrate, and a projected pattern center of the correction test mark on the device surface is offset from the first rotation center by an offset vector smaller than an error allowed by a design requirement. Before forming the second graph layer, the method further comprises the step of repeatedly forming the first graph layer and the test surface, the second offset vector is gradually reduced until the second offset vector is smaller than or equal to the error value allowed by the design requirement, when the second offset vector is smaller than or equal to the preset value, the first graph layer is the second graph layer, and the test mark is the correction test mark.

The steps of forming the first graphic layer 230 and the test marks include: forming an initial pattern film on the substrate 200; and carrying out first exposure treatment on the initial pattern film through a photomask, removing part of the initial pattern film in the mark area M and part of the initial pattern film in the device area N, and forming a first pattern layer and a test mark.

The test mark 213 is formed by the same exposure process as the first pattern layer 230, and the test mark 213 is used to detect an offset vector of the first pattern layer 230 with respect to the first device structure and the second device structure, so that the test mark 213 can mark a position of a subsequently formed third device structure.

In this embodiment, the test mark 213 is the remaining initial pattern film on the mark region M after the second exposure process. In other embodiments, the third device structure formed subsequently is a third opening in the second functional layer or the substrate, and the test mark is a fourth opening in the initial pattern layer of the mark region.

The number of test marks 213 is the same as the number of mark structures.

In this embodiment, the second offset vector of the first graphic layer 230 can be obtained by a plurality of first offset vectors between the first rotation centers of a plurality of the mark structures and the center of the corresponding test mark 213, and if the second offset vector is greater than an error value allowed by design requirements, the method for forming the second graphic layer further includes: removing the first graphics layer 230; after removing the first pattern layer 230, a second pattern layer is formed on the device region N substrate 200 according to the second offset vector. The step of forming a second pattern layer on the device region N substrate 200 according to the second offset vector includes: forming an initial pattern layer on the substrate 200; adjusting the position of the reticle according to the second offset vector; and after the position of the photomask is adjusted, carrying out second exposure treatment on the initial graph layer through the photomask to form a second graph layer and a correction test mark.

If the second offset vector is smaller than the error value allowed by the design requirement, the first graphics layer 230 is the second graphics layer.

The number of the mark structures is more than or equal to 3, and the translation, the rotation, the enlargement and the reduction of the pattern in the pattern film along any direction parallel to the device surface can be determined through a plurality of first offset vectors between the first rotation centers of a plurality of the mark structures and the centers of the corresponding test marks 213. The second offset vector includes the translation, rotation, zoom in, and zoom out.

In this embodiment, the third test mark 213 and the mark structure are similar patterns.

Specifically, the test mark 213 includes a second rotation center, after the test mark 213 rotates around a straight line perpendicular to the device surface and passing through the second rotation center by a second angle, the formed structure coincides with the test mark 213, the second angle is greater than zero and less than or equal to 180 degrees, the test mark 213 includes a plurality of test portions, the test portions are uniformly distributed around the second rotation center, and each test portion includes one or more test branches.

The number of the test portions is 3 to 8, and specifically, in this embodiment, the number of the test portions in the test mark 213 is four.

In this embodiment, the number of test branches in each test section is one.

In this embodiment, the test branch portion is rectangular. The test branches are the same shape and size as the group of branches. In other embodiments, the test branches are not the same shape and size as the group of branches.

The number of test portions in a single test mark 213 is equal to the number of mark portions in a single mark structure, and each test portion corresponds to each mark portion one to one; the number of test branches in a single test portion is equal to the number of branch groups in a single mark portion, and each test branch corresponds to each branch group.

The mark region includes a plurality of sub-mark regions, and any one sub-mark region is rotated by a first angle about a line perpendicular to the device surface and passing through the center of the mark region to coincide with another sub-mark region. The number of the sub-mark areas is the same as the number of the mark parts in the mark structure. A plurality of mark parts in the mark structure are respectively positioned in the plurality of sub-mark areas; a plurality of test parts in the test mark are respectively positioned in a plurality of sub-mark areas; the fact that the test parts are in one-to-one correspondence with the mark parts respectively means that the mark parts and the test parts which are in mutual correspondence are located in the same sub-mark area.

The test branch parts in the test part and the mark part which correspond to each other respectively correspond to the branch parts, which means that: the test branch parts and the branch part groups corresponding to each other are located in the same sub-mark area. In this embodiment, the test branch portion is strip-shaped, and the extending direction of the test branch portion is parallel to the extending direction of the corresponding branch portion group. In other embodiments, the extension direction of the test branch is at an angle to the extension of the respective group of branches.

In this embodiment, the second angle is 90 °, and the projection pattern of the test on the device surface is a centrosymmetric pattern. In other embodiments, the second angle is 30 °, 45 °, 60 °, or 120 °.

Referring to fig. 12 and 13, fig. 12 is a cross-sectional view taken along a cutting line 7-8 in fig. 13, and fig. 12 is a schematic view of a subsequent step based on fig. 10, in which a third device structure 240 is formed in the device region N by using the second pattern layer as a mask.

In this embodiment, the third device structure 240 serves as a gate of a transistor. In other embodiments, the first device structure is a first doped layer and the second device structure is a second doped layer; alternatively, the first device structure is a first active region located in the substrate; the second device structure is used for forming a grid electrode positioned on the substrate; the third device is a third opening in the second functional layer, the third opening is used for accommodating a plug, and the plug is used for realizing the electrical connection between the first device and the second device and an external circuit.

In this embodiment, the forming method further includes: a third mark 214 is formed on the marking region M of the substrate 200, and the third mark 214 is used for marking the third device structure 240.

The steps of forming the third device structure 240 and the third indicia 214 include: and etching the functional layer by using the second pattern layer 230 and the correction test mark as masks to form the third device structure 240 and the third mark 214.

With continued reference to fig. 12 and 13, after the third device structure 240 is formed, the second patterning layer and the rework test mark are removed.

The process of removing the pattern layer 230 and the leveling test marks 213 includes an ashing process.

The forming method further includes: forming a dielectric layer covering the substrate, the first device structure, the second device structure, the third device structure and the mark structure; forming a contact hole in the dielectric layer, wherein the bottom of the contact hole is exposed out of the third device structure; and forming a device plug in the contact hole.

The device plug is used for realizing the electric connection of the third device structure and an external circuit.

Aligning the contact hole with the third device structure through the third mark in the process of forming the contact hole.

Fig. 14 to 17 are schematic structural views of another embodiment of a method for forming a semiconductor structure according to the present invention.

The same parts of this embodiment as those of the embodiment shown in fig. 4 to 13 are not repeated herein, but the differences are:

referring to fig. 14, a first branch 211 is formed in the mark region M; a first device structure 201 is formed in the device region N.

In this embodiment, the marker portion includes a plurality of branch groups. The plurality of branch groups are arranged along a direction perpendicular to the extension direction of the branch groups.

The number of the branch groups per marker is 5 to 15. Specifically, in this embodiment, the number of the branch groups in each marker portion is 10.

If the distance between the centers of the adjacent branch parts is too large or the width of the branch parts is too large, the integration level of the formed semiconductor structure is easily reduced; if the distance between the centers of the adjacent branch groups is too small, or the width of the branch groups is too small, the process difficulty of the first etching and the second etching is easily increased. Specifically, in the present embodiment, the distance between adjacent branch groups is 0.9 μm to 1.1 μm; the width of the branch group is 0.45-0.55 μm.

In this embodiment, the centers of the first branches 211 in a single mark are collinear, and an extension line of the center-to-center line of the first branches 211 in the single mark does not pass through the center of the first mark. In other embodiments, an extension of a central line of each first branch passes through the center of the first mark.

In this embodiment, an acute angle is formed between a connecting line between the center of the first mark and the center of the single mark portion and the extending direction of the branch portion group, and specifically, an angle formed between a connecting line between the center of the first mark and the center of the single mark portion and the extending direction of the first branch portion is 45 °. In other embodiments, an included angle between a connecting line of the first mark center and the center of the single mark portion and the extending direction of the first branch portion is 30 °, 60 ° or other angles; the connecting line of the first mark center and the center of the single mark part is vertical to the extending direction of the branch part group; alternatively, a line connecting the first mark center and the center of the single mark portion is parallel to the extending direction of the branch group.

Referring to fig. 15, a second branch 212 is formed in the mark region M; a second device structure 202 is formed in the device region N.

In this embodiment, the second branch portion 212 is rectangular, the first branch portion 211 is rectangular, the longitudinal direction of the first branch portion 211 is parallel to the extending direction of the branch portion group, and the longitudinal direction of the second branch portion 212 is parallel to the extending direction of the branch portion group.

The width of the second branch 212 is equal to the width of the first branch 211.

The number of the second branches 212 is the same as that of the first branches 211.

In this embodiment, the shape and size of each branch group in the mark portion are the same. In other embodiments, the groups of branches in the tag are not identical in shape or size. For example: the sizes of the long sides of the branch groups in the mark portion are different.

In this embodiment, the shape and size of the second branch portion 212 are the same as those of the first branch portion 211. In other embodiments, the shape and size of the second branch portion is different from the shape and size of the first branch portion. For example, the first branch portion may have a size smaller than that of the second branch portion or the first branch portion may have a size larger than that of the second branch portion in the extending direction along the branch portion group.

In this embodiment, an acute included angle is formed between a connection line between the center of the mark branch portion and the first rotation center and the extending direction of the branch portion group. Specifically, an included angle between a connecting line between the center of the mark branch part and the first rotation center and the extending direction of the branch part group is 45 °.

In other embodiments, an angle between a line connecting the mark branch center and the first rotation center and the extension direction of the branch group may be 30 ° or 60 °; or the connecting line of the center of the marking part and the first rotation center is parallel to the extending direction of the branch group; or a connecting line between the center of the marking part and the first rotating center and the extending direction of the branch part group form an acute included angle.

Referring to fig. 16, a patterned first pattern layer 230 is formed on the device region N, and a test mark 213 is formed in the mark region M, where the test mark 213 is used to mark the first pattern layer 230, and a projected pattern center of the test mark 213 on the device surface has a first offset vector on the device surface relative to the first rotation center.

In this embodiment, the number of test branches in a single test portion is the same as the number of branch groups in a single marker portion. In other embodiments, the number of test branches in a single test section is less than the number of branch groups in a single marker section; alternatively, the number of test branches in a single test portion is larger than the number of branch groups in a single marker portion.

In this embodiment, the number of the test portions is the same as the number of the mark portions. Specifically, the number of test portions in a single test mark 213 is four. Each testing part corresponds to each marking part; the test branch portions and the mark portion corresponding to each other correspond to the branch portion groups, respectively.

Each test portion corresponds to each marker portion, and means: the corresponding mark part and the test part are located in the same sub-mark area. The test branch parts in the test part and the mark part which correspond to each other respectively correspond to the branch parts, which means that: the testing branch parts and the branch part groups which correspond to each other are positioned in the same sub-mark area, and the connecting line of the centers of the testing branch parts and the center of the branch part group is parallel to the extending direction of the branch part group.

With continuing reference to fig. 10 and 11, embodiments of the present invention further provide a semiconductor structure comprising: a substrate 200, the substrate 200 comprising a device side, the device side comprising a device region N and a marker region M;

a first device structure 201 and a second device structure 202 located in the device region N;

a mark structure located in the mark region M, the mark structure including a first rotation center, the mark structure bypassing the first rotation center and being rotated by a first angle with respect to a straight line perpendicular to the device surface to coincide with itself, the first angle is greater than zero and less than or equal to 180 degrees, the marking structure comprises a plurality of marking portions, the mark part comprises a branch part group, the projection pattern of the branch part group on the device surface is in a strip shape, the branch group includes a first branch 211 and a second branch 212, an arrangement direction of projection patterns of the first branch 211 and the second branch 212 on the device surface is parallel to an extension direction of projection patterns of the branch group on the device surface, the first branch 211 of the branch group of each branch group is used for marking the first device structure 201, and the second branch 212 of each branch group is used for marking the second device structure 202; a test mark located in the mark region M of the substrate 200, wherein the projection pattern center of the test mark on the device surface has a first offset vector relative to the projection of the first rotation center on the device surface; a first patterning layer 230 located in the device region N of the substrate 200. .

In this embodiment, the distance from the top of the first branch portion 211 to the device surface is equal to the distance from the top of the second branch portion 212 to the device surface.

The semiconductor structure in this embodiment is formed by the forming method of the embodiment shown in fig. 4 to fig. 11, and will not be described herein again.

FIG. 17 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 17, the semiconductor structure of the present embodiment is the same as the semiconductor structure shown in fig. 13, and the description thereof is omitted here, except that:

the semiconductor structure further includes: a fourth device structure 303 located in the device region N; each branch group further includes: a third branch 313, the third branch 313 of each branch group being used to mark the fourth device structure 303; the arrangement direction of the projection patterns of the first branch portion 211, the second branch portion 212 and the third branch portion 313 on the device surface is parallel to the extending direction of the projection patterns of the branch portion group on the device surface.

In this embodiment, the fourth device structure 303 is located in the substrate 200. Specifically, in this embodiment, the fourth device structure 303 is a third active region located in the substrate 200, and the third active region is used to increase the conductivity of the substrate 200. In other embodiments, the fourth device structure may further be a third doped region located in the substrate, where the third doped region is used to form a source region or a drain region of a MOS transistor, a base, a collector, or an emitter of a triode, or a positive electrode and a negative electrode of a diode.

Correspondingly, the branch groups further include third branches 313, and the third branches 313 in each branch group are used for marking the fourth device structure 303.

The fourth device may also be an opening in the second functional layer or the fourth device may be used to form a gate of a MOS transistor.

In this embodiment, the number of the fourth devices is 1 to 3, for example, 2. Accordingly, the number of the third branch portions 313 in each branch group is 1 to 3.

The centers of the projected patterns of the third branch portion 313, the second branch portion 212 and the first branch portion 211 on the device surface are collinear, and the arrangement direction of the projected patterns of the third branch portion 313, the second branch portion 212 and the first branch portion 211 on the device surface is parallel to the extending direction of the projected patterns of the branch portion group on the device surface.

In this embodiment, the third branch portion 313, the second branch portion 212 and the first branch portion 211 are all located in the substrate.

In this embodiment, the number of branch groups in a single marker portion is one. The connecting line of the center of the projection pattern of the single branch group on the device surface and the center of the projection pattern of the mark structure on the device surface is vertical to the extending direction of the branch group. In other embodiments, a line connecting the center of the projected pattern of the single branch group on the device surface and the center of the projected pattern of the mark structure on the device surface forms an acute angle with the extending direction of the branch group.

Referring to fig. 18, the same points of the semiconductor structure formed by the method for forming a semiconductor structure shown in fig. 14 to 16 are omitted for brevity. The difference lies in that:

in this embodiment, the semiconductor structure further includes: a fourth device structure 303 located in the device region N; each branch group further includes: a third branch 413, the third branch 413 of each branch group being used to mark the fourth device structure 303; the arrangement direction of the projection patterns of the first branch portion 211, the second branch portion 212 and the third branch portion 413 on the device surface is parallel to the extending direction of the projection patterns of the branch portion group on the device surface.

In this embodiment, the third branch portion 413, the second branch portion 212 and the first branch portion 211 are all located in the substrate 200.

In this embodiment, the centers of the third branch 413, the second branch 212 and the first branch 211 are collinear, and the arrangement direction of the third branch 413, the second branch 212 and the first branch 211 is parallel to the extending direction of the branch group.

In this embodiment, the number of branch groups in a single marker portion is plural.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a device surface, and the device surface comprises a device area and a mark area;

forming a first device structure and a second device structure in the device area, and forming a mark structure in the mark area, where the mark structure includes a first rotation center, the mark structure rotates around a straight line perpendicular to the device surface and passing through the first rotation center by a first angle, the formed structure coincides with the mark structure, the first angle is greater than zero and less than or equal to 180 degrees, the mark structure includes a plurality of mark portions uniformly distributed around the first rotation center, the mark portion includes a branch group, a projection pattern of the branch group on the device surface is in a bar shape, the branch group includes a first branch portion and a second branch portion, an arrangement direction of the projection pattern of the first branch portion and the second branch portion on the device surface is parallel to an extension direction of the projection pattern of the branch group on the device surface, forming the first branch portion during formation of the first device structure and forming the second branch portion during formation of the second device structure;

after the mark structure is formed, a first graphic layer is formed on the device area in a patterning mode, and a test mark is formed in the mark area in the process of forming the first graphic layer, wherein the projection of the test mark on the device surface has a first offset vector relative to the projection of the first rotation center on the device surface.

2. The method of forming a semiconductor structure according to claim 1, wherein a plurality of branch groups are provided in each mark portion, and each branch group is arranged in parallel.

3. The method of forming a semiconductor structure of claim 1, wherein the number of the branch groups is 5 to 15; the distance between the centers of the adjacent branch parts is 0.9-1.1 μm; the width of the branch group is 0.45-0.55 μm.

4. The method of forming a semiconductor structure according to claim 1, wherein the number of each of the branch groups is one, the branch group is rectangular, and the length of the branch group is 18 μm to 22 μm; the width of the branch group is 0.9-11 μm.

5. The method of claim 1, wherein the first branch is rectangular, the second branch is rectangular, and adjacent sides of the first branch and the second branch are equal in length.

6. The method of forming a semiconductor structure of claim 1, wherein prior to forming the first pattern layer and the test mark, further comprising: forming a fourth device structure in the device region; each branch group further includes: a third branch portion of each branch group for marking the fourth device structure; the arrangement direction of the projection patterns of the first branch part, the second branch part and the third branch part on the device surface is parallel to the extension direction of the projection patterns of the branch part group on the device surface.

7. The method of forming a semiconductor structure of claim 6, wherein the number of the third branches in a single branch group is 1 to 3.

8. The method of forming a semiconductor structure of claim 1, wherein the first device structure is located in the device region substrate, the first leg is located in the substrate; or the first device structure is located on the substrate, and the first branch is located on the substrate;

the second device structure is located in the device region substrate, and the second branch portion is located in the substrate; or the second device structure is located on the substrate, and the second branch portion is located on the substrate.

9. The method of forming a semiconductor structure of claim 1, wherein a distance from a top of the first leg to the device face is equal to a distance from a top of the second leg to the device face.

10. The method of forming a semiconductor structure of claim 9, wherein the first branch is located in the mark region substrate and the second branch is located in the mark region substrate;

or before forming the mark structure, the method further comprises: forming a first functional layer on the substrate; the first branch is a first opening in the first functional layer; the second branch is a second opening in the first functional layer.

11. The method according to claim 1, wherein a line connecting a center of the mark portion and the first rotation center is perpendicular to an extending direction of the branch group; or a connecting line of the center of the marking part and the first rotation center is parallel to the extension direction of the branch group; or a connecting line between the center of the mark part and the first rotating center and the extending direction of the branch part group form an acute included angle.

12. The method of claim 1, wherein the test mark comprises a second rotation center, wherein the test mark is rotated by a second angle around a line perpendicular to the device surface and passing through the second rotation center, the formed structure coincides with the test mark, the second angle is greater than zero and less than or equal to 180 degrees, the test mark comprises a plurality of test portions, the test portions are uniformly distributed around the second rotation center, and each test portion comprises one or more test branches.

13. The method of forming a semiconductor structure of claim 12, wherein the number of test portions in a single test mark is equal to the number of mark portions in a single mark structure, each test portion corresponding to each mark portion one-to-one; the number of the test branch parts in the single test part is equal to that of the branch part groups in the single marking part, and the test branch parts in the test part and the marking part which correspond to each other respectively correspond to the branch part groups; the test branch part is strip-shaped, and the extending direction of the test branch part is parallel to the extending direction of the corresponding branch part group.

14. The method of forming a semiconductor structure of claim 1, further comprising, after forming the test mark and the first pattern layer: forming a first graphic layer in a graphic mode on the substrate of the device area, and forming a test mark on the substrate of the mark area; detecting a first offset vector of the test mark center from the first rotation center in a direction parallel to the device face; acquiring a second offset vector of the first graphic layer according to the first offset vector; removing the first graphic layer and the test mark; after removing the first graphic layer and the test mark, forming a second graphic layer on the substrate of the device area according to the second offset vector; forming a third device structure in the device area by taking the second graphic layer as a mask; and after the third device structure is formed, removing the second graphic layer.

15. The method of forming a semiconductor structure according to claim 14, wherein a second functional layer is formed over the mark region and the device region substrate; the first graphic layer, the second graphic layer and the test mark are positioned on the second functional layer;

the step of forming the third device structure comprises: processing the second functional layer by taking the second graphic layer as a mask, and forming a third device structure on the device area substrate;

alternatively, the step of forming the third device structure comprises: and processing the device area substrate by taking the second graphic layer as a mask, and forming a third device structure in the device area substrate.

16. The method of forming a semiconductor structure of claim 15, wherein the processing comprises: an etching process or an ion implantation process.

17. The method of forming a semiconductor structure of claim 1, wherein the number of marker structures is greater than or equal to three; the first centers of rotation of at least three of the plurality of marker structures are not collinear.

18. A semiconductor structure, comprising:

a substrate comprising a device side comprising a device region and a marker region;

a first device structure and a second device structure located in the device region;

the marking structure is positioned in the marking area and comprises a first rotation center, the marking structure bypasses the first rotation center, a straight line perpendicular to the device surface is rotated by a first angle and is coincided with the marking structure, the first angle is larger than zero and smaller than or equal to 180 degrees, the marking structure comprises a plurality of marking parts, each marking part comprises a branch group, the projection graph of the branch group on the device surface is in a strip shape, each branch group comprises a first branch part and a second branch part, the arrangement direction of the projection graph of the first branch part and the second branch part on the device surface is parallel to the extension direction of the projection graph of the branch group on the device surface, the first branch part of each branch group is used for marking the first device structure, and the second branch part of each branch group is used for marking the second device structure;

a test mark located in a mark region of the substrate, a projection pattern center of the test mark on the device surface has a first offset vector relative to a projection of the first rotation center on the device surface;

the first graphic layer is positioned in a device area of the substrate;

the distance from the top of the first branch part to the device surface is equal to the distance from the top of the second branch part to the device surface.

19. The semiconductor structure of claim 18, further comprising: a fourth device structure located in the device region; each branch group further includes: a third branch portion of each branch group for marking the fourth device structure; the arrangement direction of the projection patterns of the first branch part, the second branch part and the third branch part on the device surface is parallel to the extension direction of the projection patterns of the branch part group on the device surface.