JP2023006716A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To preferably improve positioning accuracy in manufacture of a semiconductor device.SOLUTION: There is provided a semiconductor device comprising a semiconductor substrate, a gate electrode provided in the semiconductor substrate, and a poly gate runner provided above the semiconductor substrate and connected to the gate electrode. The semiconductor device may comprise an oxide film provided on the semiconductor substrate. The through hole may expose the oxide film. The semiconductor device may comprise an inter-layer insulation film provided above the semiconductor substrate. The inter-layer insulation film may be filled in the through hole.SELECTED DRAWING: Figure 22

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Conventionally, in manufacturing a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), a marker is provided on a semiconductor substrate to perform alignment (position correction function) (see Patent Documents 1 and 2, for example).
Patent Document 1: JP-A-2021-032672 Patent Document 2: JP-A-2010-219233

In the manufacture of semiconductor devices, it is preferable to improve the positioning accuracy.

In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. A semiconductor device includes a semiconductor substrate. A semiconductor device includes a gate electrode. The gate electrode may be provided on the semiconductor substrate. A semiconductor device may comprise a poly gate runner. A poly gate runner may be provided over the semiconductor substrate. A poly gate runner may connect to the gate electrode. Poly gate runners may have through holes.

The semiconductor device may include an oxide film. An oxide film may be provided on the semiconductor substrate. The through holes may expose the oxide film. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided above the semiconductor substrate. The through holes may be filled with an interlayer insulating film. The interlayer insulating film may be in contact with the oxide film through the through hole.

A poly gate runner may have a plurality of through holes.

An active portion may be provided in the semiconductor substrate. The poly gate runners may have transverse poly gate runners. Transverse poly gate runners may be provided to traverse the active portion in top view. The transverse poly gate runners may have through holes.

The poly gate runners may have outer poly gate runners. The outer poly gate runner may be provided so as to surround the active portion when viewed from above. The outer poly gate runners may have through holes. The outer poly gate runner may have multiple edges. Two or more through-holes may be discretely arranged on each edge of the plurality of edges.

A semiconductor device may comprise a metal gate runner. A metal gate runner may be provided above the poly gate runner. Above the through hole, the metal gate runner may be recessed.

The interlayer insulating film may have contact holes. A contact hole may connect the poly gate runner and the metal gate runner. The contact hole may overlap the through hole when viewed from above. The contact hole does not have to overlap the through hole when viewed from above.

A second aspect of the present invention provides a method of manufacturing a semiconductor device. A semiconductor device includes a semiconductor substrate. A semiconductor device includes a gate electrode. The gate electrode may be provided on the semiconductor substrate. A semiconductor device may comprise a poly gate runner. A poly gate runner may be provided over the semiconductor substrate. A poly gate runner may connect to the gate electrode. In the method of manufacturing a semiconductor device, a through hole may be formed in the poly gate runner.

A method of manufacturing a semiconductor device may comprise a patterning step. In a patterning step, polysilicon may be patterned to form poly gate runners. Through holes may be formed in the poly gate runners during the patterning step.

The method of manufacturing a semiconductor device may include an inspection step. During the inspection phase, the semiconductor device may be inspected for defects. During the inspection stage, through-holes may be used for positioning and inspection.

It should be noted that the above summary of the invention does not list all the features of the invention. Subcombinations of these feature groups can also be inventions.

1 is a top view showing an example of a semiconductor device 100; FIG. 4 is a diagram showing an example of arrangement of poly gate runners 46 of the semiconductor device 100. FIG. 6 is a flow chart showing a method of forming a gate electrode of the semiconductor device 100 according to the comparative example; It is a figure explaining gate trench formation step S101. FIG. 5 is a diagram showing a cross section taken along line aa of FIG. 4; It is a figure explaining gate insulating film formation step S102. It is a figure explaining polysilicon film-forming step S103. It is a figure explaining resist formation step S104. FIG. 9 is a view showing a bb cross section of FIG. 8; It is a figure explaining patterning step S105. FIG. 11 is a view showing a cc cross section of FIG. 10; It is a figure explaining resist removal step S106. FIG. 13 is a view showing a dd cross section of FIG. 12; It is a figure explaining inspection step S107. 4 is a flow chart showing a method for forming a gate electrode of the semiconductor device 100 according to the embodiment; It is a figure explaining resist formation step S204. FIG. 17 is a view showing the ee cross section of FIG. 16; It is a figure explaining patterning step S205. FIG. 19 is a view showing the ff section of FIG. 18; It is a figure explaining resist removal step S206. FIG. 21 is a view showing a gg section of FIG. 20; It is a figure explaining inspection step S207. An example of the arrangement of the interlayer insulating film 38 and the metal gate runners 130 in top view is shown. FIG. 24 is a view showing the hh section of FIG. 23; Another example of the arrangement of the interlayer insulating film 38 and the metal gate runners 130 in top view is shown. An example of the arrangement of through-holes 184 in the poly gate runner 46 viewed from the top is shown. 4A and 4B are diagrams for explaining in detail the shape of a through-hole 184; FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is called "upper", and the other side is called "lower". One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface. The directions of “up” and “down” are not limited to the direction of gravity or the direction when the semiconductor module is mounted.

In this specification, technical matters may be described using X-, Y-, and Z-axis orthogonal coordinate axes. The Cartesian coordinate axes only specify the relative positions of the components and do not limit any particular orientation. For example, the Z axis does not limit the height direction with respect to the ground. Note that the +Z-axis direction and the −Z-axis direction are directions opposite to each other. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the Z-axis direction may be referred to as the depth direction. Further, in this specification, a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.

In this specification, terms such as "identical" or "equal" may include cases where there is an error due to manufacturing variations or the like. The error is, for example, within 10%.

FIG. 1 is a top view showing an example of a semiconductor device 100. FIG. FIG. 1 shows the positions of each member projected onto the upper surface of the semiconductor substrate 10 . In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

A semiconductor device 100 is provided on a semiconductor substrate 10 . The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. Semiconductor substrate 10 may be a silicon carbide substrate.

The semiconductor substrate 10 has a first edge 161 and a second edge 162 when viewed from above. In this specification, simply referring to a top view means viewing from the top side of the semiconductor substrate 10 . The semiconductor substrate 10 of this example has two sets of first edges 161 facing each other when viewed from above. In addition, the semiconductor substrate 10 of this example has two sets of second edges 162 facing each other when viewed from above. In FIG. 1, the first edge 161 is parallel to the X-axis direction. The second edge 162 is parallel to the Y-axis direction. Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10 . Also, the first edge 161 is perpendicular to the extension direction of the gate trench, which will be described later. The second edge 162 is parallel to the extending direction of the gate trench, which will be described later.

An active portion 160 is provided in the semiconductor substrate 10 . The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

In this example, the active portion 160 is provided with a transistor portion 70 including a transistor element such as a field effect transistor (MOSFET). In another example, transistor sections 70 and diode sections including diode elements such as FWD (Free Wheel Diode) may be alternately arranged along a predetermined arrangement direction on the upper surface of semiconductor substrate 10 . An IGBT may be provided in the transistor section 70 . A reverse blocking IGBT may be provided in the transistor section 70 . In this example, two transistor sections 70 (transistor section 70-1 and transistor section 70-2) are provided along the Y-axis direction. A P+ type well region or a poly gate runner, which will be described later, may be provided between the transistor portions 70 .

The transistor section 70 has a P + -type collector region in a region in contact with the lower surface of the semiconductor substrate 10 . In the transistor section 70, a gate electrode having an N+ type emitter region, a P− type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10. FIG.

Semiconductor device 100 may have one or more pads above semiconductor substrate 10 . The semiconductor device 100 of this example has a gate pad 164 . Semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is arranged near the first edge 161 . The vicinity of the first edge 161 refers to a region between the first edge 161 and the emitter electrode when viewed from above. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

A gate potential is applied to the gate pad 164 . Gate pad 164 is electrically connected to the conductive portion of the gate electrode of active portion 160 . The semiconductor device 100 includes a metal gate runner 130 connecting the gate pad 164 and the gate electrode. In FIG. 1, the metal gate runners 130 are hatched with oblique lines.

The metal gate runner 130 is arranged between the active portion 160 and the first edge 161 or the second edge 162 in top view. The metal gate runner 130 of this example surrounds the active portion 160 when viewed from above. A region surrounded by the metal gate runners 130 in top view may be the active portion 160 . Also, the metal gate runner 130 is connected to the gate pad 164 . A metal gate runner 130 is arranged above the semiconductor substrate 10 . The metal gate runners 130 may be metal lines including aluminum or the like.

The outer well region 11 is provided so as to overlap with the metal gate runner 130 . In other words, like the metal gate runner 130, the outer well region 11 surrounds the active portion 160 when viewed from above. The outer peripheral well region 11 is also provided extending with a predetermined width in a range not overlapping the metal gate runners 130 . The outer well region 11 is a region of the second conductivity type. The peripheral well region 11 in this example is of P+ type (not shown). The impurity concentration of outer well region 11 may be 5.0×10 ¹⁷ atoms/cm ³ or more and 5.0×10 ¹⁹ atoms/cm ³ or less. The impurity concentration of outer well region 11 may be 2.0×10 ¹⁸ atoms/cm ³ or more and 2.0×10 ¹⁹ atoms/cm ³ or less.

The semiconductor device 100 also includes a temperature sensing portion (not shown), which is a PN junction diode made of polysilicon or the like, and a current detecting portion (not shown) that simulates the operation of the transistor portion 70 provided in the active portion 160. may The temperature sensing section may be connected to the anode pad and the cathode pad through wiring. When the temperature sensing portion is provided, it is preferably provided in the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the first edge 161 or the second edge 162 in top view. Edge termination structure 90 in this example is positioned between metal gate runner 130 and first edge 161 or second edge 162 . The edge termination structure 90 reduces electric field concentration on the upper surface side of the semiconductor substrate 10 . Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf annularly surrounding active portion 160 .

FIG. 2 is a diagram showing an example of the arrangement of the poly gate runners 46 of the semiconductor device 100. As shown in FIG. Poly gate runners 46 connect to gate electrodes provided on semiconductor substrate 10 . In FIG. 2, the poly gate runners 46 are shown by discrete dashed lines, but the poly gate runners 46 are continuously provided along the dashed lines. A poly gate runner 46 connects with the gate conductive portion of the gate electrode. A gate potential can be applied to the gate electrode via the poly gate runner 46 by connecting the poly gate runner 46 and the gate electrode.

A poly gate runner 46 is provided above the semiconductor substrate 10 . The poly gate runner 46 at least partially overlaps the metal gate runner 130 when viewed from above. At least a portion of the poly gate runners 46 may be provided below the metal gate runners 130 . Thus, poly gate runners 46 and metal gate runners 130 can be connected. At least a portion of the poly gate runner 46 is provided in the active portion 160 . Therefore, the poly gate runner 46 and the gate electrode of the active portion 160 can be connected.

In this example, poly gate runners 46 have transverse poly gate runners 47 and perimeter poly gate runners 48 . A transverse poly gate runner 47 is provided so as to traverse the active portion 160 in top view. In this example, the transverse poly gate runners 47 extend in the X-axis direction. The transverse poly gate runner 47 is arranged between the transistor section 70-1 and the transistor section 70-2 when viewed from above. By providing the transverse poly gate runners 47, the gate potential can be evenly applied to each gate electrode. Two or more transverse poly gate runners 47 may be provided.

The outer poly gate runner 48 is provided so as to surround the active portion 160 when viewed from above. Further, the outer peripheral side poly gate runner 48 is arranged between the active portion 160 and the first edge 161 or the second edge 162 in top view. Note that the outer poly gate runner 48 may be provided so as to surround the gate pad 164 .

FIG. 3 is a flow chart showing a method of forming a gate electrode of the semiconductor device 100 according to the comparative example. The method of forming a gate electrode includes a gate trench forming step S101, a gate insulating film forming step S102, a polysilicon film forming step S103, a resist forming step S104, a patterning step S105, a resist removing step S106 and an inspection step S107. Each step is described below.

FIG. 4 is a diagram illustrating the gate trench forming step S101. FIG. 4 shows the gate trench 45 in top view.

The gate trench 45 of this example has two straight portions 39 extending along the extending direction (Y-axis direction) (a portion of the trench that is straight along the extending direction) and a tip connecting the two straight portions 39 . It may have a portion 41 .

It is preferable that at least part of the distal end portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated. As shown in FIG. 4, the gate trenches 45 may be arranged along the arrangement direction (X-axis direction) perpendicular to the extending direction.

FIG. 5 is a diagram showing a section aa of FIG. FIG. 5 is an XZ cross section through the gate trench 45 . 5, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

A gate trench 45 is formed in the upper surface 21 of the semiconductor substrate 10 in a gate trench forming step S101. The gate trench 45 may be formed by anisotropic dry etching. Since the gate trenches 45 are formed by anisotropic dry etching, the sidewalls of the gate trenches 45 are substantially perpendicular to the upper surface 21 of the semiconductor substrate 10 as shown in FIG.

FIG. 6 is a diagram illustrating the step S102 of forming a gate insulating film. FIG. 6 shows a section similar to that of FIG. In the gate insulating film forming step S102, the gate insulating film 42 is formed. A gate insulating film 42 is provided on the upper surface 21 of the semiconductor substrate 10 . The gate insulating film 42 is also provided inside the gate trench 45 . The gate insulating film 42 may be formed by thermal oxidation. The gate insulating film 42 may be formed by chemical vapor deposition (CVD). The gate insulating film 42 is an oxide film in this example.

FIG. 7 is a diagram for explaining the polysilicon film forming step S103. FIG. 7 shows a section similar to that of FIG. In the polysilicon film forming step S103, a polysilicon 50 is formed. The polysilicon 50 may be deposited with a predetermined thickness above the gate insulating film 42 . The inside of gate trench 45 may be filled with polysilicon 50 . Polysilicon 50 may be formed by chemical vapor deposition (CVD).

FIG. 8 is a diagram for explaining the resist formation step S104. FIG. 8 shows the arrangement of the resist 180 in top view. In FIG. 8, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 9 is a diagram showing a bb cross section of FIG. FIG. 9 is an XZ cross section passing through the gate trench 45 . 9, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

A resist 180 is formed above the polysilicon 50 in a resist forming step S104. The resist 180 may be formed by a known photoprocess method. By providing the resist 180, the polysilicon 50 can be patterned.

FIG. 10 is a diagram illustrating the patterning step S105. FIG. 10 shows the arrangement of the resist 180 in top view. In FIG. 10, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 11 is a diagram showing a cc section of FIG. FIG. 11 is an XZ cross section through the gate trench 45 . 11, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

In a patterning step S105, the polysilicon 50 is patterned. Polysilicon 50 is patterned by isotropic dry etching. A gate conductive portion 44 is formed inside the gate trench 45 by patterning the polysilicon 50 . Poly gate runners 46 are also formed above semiconductor substrate 10 by patterning polysilicon 50 . The gate electrode 40 is formed by performing the patterning step S105.

FIG. 12 is a diagram for explaining the resist removing step S106. FIG. 12 shows the arrangement of the poly gate runners 46 in top view. In FIG. 12, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 13 is a diagram showing a dd section of FIG. FIG. 13 is an XZ cross section through the gate trench 45 . 13, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

In the resist removing step S106, the resist 180 is removed. Resist 180 may be removed by ashing and washing.

FIG. 14 is a diagram explaining the inspection step S107. FIG. 14 shows a region including the poly gate runners 46 (peripheral side poly gate runners 48) in the vicinity of the gate pad 164 after the resist removal step S106. Poly gate runners 46 are the areas enclosed by the bold lines. In FIG. 14, semiconductor device 100 includes gate electrode 40 , poly gate runner 46 and gate pad 164 .

In the inspection step S107, the semiconductor device 100 is inspected. In this example, the semiconductor device 100 is inspected for defects. The defect inspection is performed using, for example, an image matching type defect inspection apparatus. In the image matching type defect inspection apparatus, image data of an area where no defect exists is registered in advance as a reference image, and a location having a characteristic shape is used as a reference for alignment. Therefore, it is possible to perform accurate collation with the corresponding region on the semiconductor device 100 and determine the presence or absence of defects. The image matching type defect inspection device may be a known device. By performing the defect inspection in the middle of the manufacturing process (in-line), it is possible to identify the cause of the defect and improve the yield. In addition, it is possible to prevent defective products from being distributed on the market.

In the case of image collation, it is positioned and inspected. In this example (comparative example), the end portion 41 of the gate trench 45 is used as a reference for positioning, and it is inspected whether or not the end portion of the poly gate runner 46 is provided at a predetermined position. The tip 41 of the gate trench 45 is provided below the poly gate runner 46 . Therefore, the positioning is performed using the front end portion 41 of the gate trench 45 that is visible when viewed from above. Since the poly gate runners 46 are patterned by isotropic dry etching in the patterning step S105, the sides of the poly gate runners 46 are not vertical. Therefore, the end position of the poly gate runner 46 may vary depending on the inclination of the side surface. Similarly, the position of the tip portion 41 of the gate trench 45 may also vary. Therefore, the relative positions of the ends of the poly gate runners 46 with respect to the tip 41 of the gate trench 45 vary. As a result, in the defect inspection, portions that do not match the reference image are detected as pseudo defects 190 . Therefore, it is preferable to improve the positioning accuracy in order to perform accurate inspection.

FIG. 15 is a flow chart showing a method for forming the gate electrode of the semiconductor device 100 according to the embodiment. The method of forming a gate electrode includes a gate trench forming step S201, a gate insulating film forming step S202, a polysilicon film forming step S203, a resist forming step S204, a patterning step S205, a resist removing step S206 and an inspection step S207. Each step is described below. The gate trench forming step S201, the gate insulating layer forming step S202, and the polysilicon forming step S203 may be the same as the gate trench forming step S101, the gate insulating layer forming step S102, and the polysilicon forming step S103, respectively. Therefore, descriptions of the gate trench forming step S201, the gate insulating layer forming step S202, and the polysilicon forming step S203 will be omitted.

FIG. 16 is a diagram for explaining the resist forming step S204. FIG. 16 shows the arrangement of the resist 180 in top view. In FIG. 16, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 17 is a diagram showing the ee section of FIG. FIG. 17 is an XZ section through the gate trench 45. FIG. 17, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

A resist 180 is formed above the polysilicon 50 in a resist forming step S204. In this example, resist 180 has pattern 182 . 16 and 17, pattern 182 exposes polysilicon 50. In FIGS. Because the resist 180 has a pattern 182, through holes can be formed in the poly gate runners 46 in the patterning step S205. Therefore, since the through holes are formed in the patterning step S205, the photomask for patterning the resist may be changed, and an increase in the number of steps can be prevented.

FIG. 18 is a diagram illustrating the patterning step S205. FIG. 18 shows the arrangement of the resist 180 in top view. In FIG. 18, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 19 is a diagram showing the ff section of FIG. FIG. 19 is an XZ section through the gate trench 45. FIG. 19, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

In patterning step S205, polysilicon 50 is patterned in the same manner as in patterning step S105 of FIG. In the patterning step S205, the poly gate runners 46 have through holes 184. As shown in FIG. In this example, resist 180 has pattern 182 so that vias 184 can be formed in poly gate runner 46 . In FIG. 19, the through hole 184 exposes the gate insulating film 42 . The through hole 184 may have the same shape as the pattern 182 when viewed from above. Via 184 is surrounded by poly gate runners 46 . That is, through holes 184 are not provided at the ends of poly gate runners 46 . A detailed shape of the through hole 184 will be described with reference to FIG.

FIG. 20 is a diagram explaining the resist removing step S206. FIG. 20 shows the arrangement of poly gate runners 46 in top view. In FIG. 20, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines.

FIG. 21 is a diagram showing a gg section of FIG. FIG. 21 is an XZ cross section through the gate trench 45. FIG. 21, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

In the resist removing step S206, the resist 180 is removed in the same manner as in the resist removing step S106 of FIG. After the resist 180 is removed, the through hole 184 exposes the gate insulating film 42 (an oxide film in this example). Therefore, the through holes 184 of the poly gate runners 46 can be visually recognized.

FIG. 22 is a diagram explaining the inspection step S207. FIG. 22 shows a region including the poly gate runners 46 (peripheral side poly gate runners 48) in the vicinity of the gate pad 164 after the resist removal step S206. Poly gate runners 46 are the areas enclosed by the bold lines. In FIG. 22, semiconductor device 100 includes gate electrode 40 , poly gate runner 46 and gate pad 164 .

In the inspection step S207, the semiconductor device 100 is inspected for defects. In this example (embodiment), a through hole 184 is used as a reference for positioning. That is, in the inspection step S207, positioning is performed using the through holes 184 for inspection. Since the through hole 184 is formed in the same process as the patterning of the poly gate runner 46, the inclination of the side surface of the through hole 184 and the inclination of the side surface of the poly gate runner 46 are approximately the same. Therefore, variations in the relative positions of the ends of the poly gate runners 46 with respect to the through holes 184 can be reduced. Therefore, it is possible to improve the positioning accuracy and prevent the occurrence of pseudo defects.

FIG. 23 shows an example of the arrangement of the interlayer insulating film 38 and the metal gate runners 130 in top view. FIG. 23 shows the arrangement of the interlayer insulating film 38 and the metal gate runners 130 as viewed from above when the interlayer insulating film 38 and the metal gate runners 130 are formed after the inspection step S207. In FIG. 23, the arrangement of the gate trenches 45 on the upper surface 21 is indicated by dotted lines. In FIG. 23, through holes 184 in poly gate runners 46 are also shown in dashed lines. Also, in FIG. 23, the contact hole 54 in the interlayer insulating film 38 is indicated by a dashed line.

FIG. 24 is a diagram showing the hh section of FIG. FIG. 24 is an XZ section through the gate trench 45. FIG. Note that the contact hole 54 is not shown in FIG. 24, only the vicinity of the upper surface 21 of the semiconductor substrate 10 is shown, and the vicinity of the lower surface of the semiconductor substrate 10 is omitted.

An interlayer insulating film 38 is provided above the semiconductor substrate 10 . An interlayer insulating film 38 may be provided between the poly gate runner 46 and the metal gate runner 130 . The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10 . The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with an impurity such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38 . Through contact holes 54 , poly gate runners 46 may connect with metal gate runners 130 . In FIG. 23, the contact hole 54 does not overlap the through hole 184 when viewed from above.

In FIG. 24, the through hole 184 is filled with the interlayer insulating film 38 . That is, the interlayer insulating film 38 is provided inside the through hole 184 of the poly gate runner 46 . Also, the interlayer insulating film 38 is in contact with the gate insulating film 42 via the through hole 184 . Since the poly gate runner 46 has a through hole 184 , the through hole 184 is filled with the interlayer insulating film 38 .

Also, in FIG. 24, the metal gate runner 130 is recessed above the through hole 184 . That is, above the through hole 184, the metal gate runner 130 has a recess. Metal gate runners 130 are recessed because poly gate runners 46 have through holes 184 .

FIG. 25 shows another example of the arrangement of the interlayer insulating film 38 and the metal gate runners 130 in top view. FIG. 25 differs from FIG. 23 in that the contact hole 54 overlaps the through hole 184 when viewed from above. Other configurations in FIG. 25 may be the same as in FIG. The contact hole 54 may overlap the through hole 184 when viewed from above.

FIG. 26 shows an example of arrangement of through-holes 184 in the poly gate runner 46 viewed from above. FIG. 26 only shows the placement of the through holes 184 in the poly gate runners 46 and does not match the dimensions of the other examples.

In this example, poly gate runner 46 has a plurality of through holes 184 . Preferably, at least one through-hole 184 is provided per field of view for defect inspection. That is, more through-holes 184 may be provided in the poly gate runners 46 than in the example of FIG.

In FIG. 26, transverse poly gate runners 47 have through holes 184 . Also, in FIG. 26, the outer poly gate runner 48 has a through hole 184 .

An end side parallel to the X-axis direction of the outer poly gate runner 48 is defined as an end side 49-1. Further, the edge parallel to the Y-axis direction of the outer poly gate runner 48 is defined as edge 49-2. The outer poly gate runner 48 has two edges 49-1 and two edges 49-2. In this example, two or more through-holes 184 are discretely arranged on each edge of the plurality of edges 49 . In this manner, a plurality of through holes 184 may be arranged on each edge.

27A and 27B are diagrams for explaining in detail the shape of the through hole 184. FIG. FIG. 27 shows poly gate runners 46 extending in the Y-axis direction. In this example, the through hole 184 has a cross shape. Since the through-hole 184 has a cross shape, it has many ends and can be easily used as a reference for alignment. Although the through hole 184 is represented as a cross shape in this specification, the shape of the through hole 184 is not limited to a cross shape.

The through hole 184 has an extension 186 and a protrusion 188 . The extending portion 186 is a portion of the through hole 184 extending in the X-axis direction. The protrusion 188 is a portion of the through hole 184 that protrudes in the Y-axis direction. The through hole 184 has two projections 188 (projection 188-1, projection 188-2). In FIG. 27, the boundary between the extending portion 186 and the projecting portion 188 is indicated by a dashed line.

The width d2 of the extension portion 186 in the X-axis direction may be 1/3 or less of the width d1 of the poly gate runner 46 in the X-axis direction. A width d2 of the extending portion 186 in the X-axis direction may be the maximum width of the through-hole 184 in the X-axis direction. The width d1 of the poly gate runner 46 in the X-axis direction may be the minimum width of the poly gate runner 46 in the X-axis direction and the Y-axis direction. If the width of the through-hole 184 is too large, the resistance value of the poly gate runner 46 increases. Therefore, the width d2 of the extended portion 186 in the X-axis direction is 1/3 or less of the width d1 of the poly gate runner 46 in the X-axis direction. It is preferable to If the width of the through-hole 184 is too small, it cannot be used as a reference for alignment, so the width d2 of the extending portion 186 in the X-axis direction may be 1/10 or more of the width d1 of the poly gate runner 46 in the X-axis direction. . A width d2 of the extending portion 186 in the X-axis direction is, for example, about 1.2 μm. A width d2 of the extension portion 186 in the X-axis direction may be 1.2 μm or less.

A width d3 of the extending portion 186 in the Y-axis direction may be 0.1 μm or more. A width d3 of the extending portion 186 in the Y-axis direction may be 0.5 μm or less. A width d4 of the protrusion 188-1 in the X-axis direction may be 0.1 μm or more. The width d4 of the protrusion 188-1 in the X-axis direction may be 0.5 μm or less. A width d5 of the protrusion 188-1 in the Y-axis direction may be 0.1 μm or more. A width d5 of the protrusion 188-1 in the Y-axis direction may be 0.5 μm or less. The width of the protrusion 188-2 may also be the same as that of the protrusion 188-1.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the scope of claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

The execution order of each process such as actions, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly "before", "before etc., and it should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if the description is made using "first," "next," etc. for the sake of convenience, it means that it is essential to carry out in this order. not a thing

DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 11... Periphery well region, 21... Top surface, 38... Interlayer insulating film, 39... Linear part, 40... Gate electrode, 41... Tip part, 42... Gate insulating film, 44 Gate conductive portion 45 Gate trench 46 Poly gate runner 47 Transverse poly gate runner 48 Peripheral poly gate runner 49 Edge 50 Polysilicon 70 Transistor part 90 Edge termination structure part 54 Contact hole 100 Semiconductor device 130 Metal gate runner 160 Active part 161 First edge 162 Second 2 edge sides 164 gate pad 180 resist 182 pattern 184 through hole 186 extension 188 protrusion 190 pseudo defect

Claims (14)

a semiconductor substrate;
a gate electrode provided on the semiconductor substrate;
a poly gate runner provided above the semiconductor substrate and connected to the gate electrode;
The semiconductor device, wherein the poly gate runner has a through hole. further comprising an oxide film provided on the semiconductor substrate;
The semiconductor device according to claim 1 , wherein the through hole exposes the oxide film. further comprising an interlayer insulating film provided above the semiconductor substrate;
3. The semiconductor device according to claim 2, wherein said through hole is filled with said interlayer insulating film. 4. The semiconductor device according to claim 3, wherein said interlayer insulating film is in contact with said oxide film through said through hole. 5. The semiconductor device according to claim 1, wherein said poly gate runner has a plurality of said through holes. The semiconductor substrate is provided with an active portion,
The poly gate runner has a transverse poly gate runner provided to traverse the active portion in top view,
6. The semiconductor device according to claim 1, wherein said transverse poly gate runner has said through hole. The semiconductor substrate is provided with an active portion,
The poly gate runner has an outer peripheral side poly gate runner provided so as to surround the active portion in top view,
The semiconductor device according to any one of claims 1 to 6, wherein the outer poly gate runner has the through hole. The outer peripheral side poly gate runner has a plurality of edges,
8. The semiconductor device according to claim 7, wherein two or more of said through holes are discretely arranged on each of said plurality of edges. further comprising a metal gate runner provided above the poly gate runner;
9. The semiconductor device according to claim 1, wherein said metal gate runner is recessed above said through hole. further comprising an interlayer insulating film provided above the semiconductor substrate;
the interlayer insulating film has a contact hole connecting the poly gate runner and the metal gate runner;
The semiconductor device according to claim 9 , wherein the contact hole overlaps with the through hole when viewed from above. further comprising an interlayer insulating film provided above the semiconductor substrate;
the interlayer insulating film has a contact hole connecting the poly gate runner and the metal gate runner;
The semiconductor device according to claim 9 , wherein the contact hole does not overlap the through hole when viewed from above. a semiconductor substrate;
a gate electrode provided on the semiconductor substrate;
and a poly gate runner provided above the semiconductor substrate and connected to the gate electrode, the method comprising:
A method of manufacturing a semiconductor device, comprising forming a through hole in the poly gate runner. patterning polysilicon to form said poly gate runner;
13. The method of manufacturing a semiconductor device according to claim 12, wherein the patterning step forms the through hole in the poly gate runner. further comprising an inspection step of inspecting defects in the semiconductor device;
14. The method of manufacturing a semiconductor device according to claim 12, wherein in said inspection step, inspection is performed by positioning using said through hole.

Images