CN109937476A - 晶片级封装和方法 - Google Patents

晶片级封装和方法 Download PDF

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Publication number
CN109937476A
CN109937476A CN201780051429.5A CN201780051429A CN109937476A CN 109937476 A CN109937476 A CN 109937476A CN 201780051429 A CN201780051429 A CN 201780051429A CN 109937476 A CN109937476 A CN 109937476A
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China
Prior art keywords
organic insulator
layer
semiconductor wafer
landing pad
copper pillar
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CN201780051429.5A
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CN109937476B (zh
Inventor
乔治·楚
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Microchip Technology Inc
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Microchip Technology Inc
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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Abstract

一种铜柱凸块半导体封装方法将形成在铜柱凸块下方的有机绝缘层仅图案化到围绕铜柱凸块和在铜柱凸块附近的区域。通常为薄膜聚合物层的有机绝缘层用作铜柱凸块的阻挡层，以在铜柱倒装芯片接合工艺期间保护半导体晶片。铜柱凸块半导体封装方法限制了施加有机绝缘层的区域，以减少由有机绝缘层引入到半导体晶片的应力。在另一个实施例中，一种铜柱凸块半导体封装方法将形成在铜柱凸块下方的有机绝缘层图案化到围绕铜柱凸块并沿着再分布层的路径的区域，而不使用大的且连续的有机绝缘层。

Description

晶片级封装和方法
相关申请的交叉引用
本申请要求2016年9月23日提交的标题为“晶片级封装和方法(WAFER LEVELPACKAGE AND METHOD)”的美国临时专利申请No.62/399,111的优先权，出于所有目的，该美国临时专利申请通过引用的方式并入本文。
背景技术
使用铜柱凸块倒装芯片互连技术的半导体封装已经被广泛采用。铜柱凸块用作集成电路芯片和封装基板之间的倒装芯片互连。铜柱凸块倒装芯片互连是一种晶片级封装，其中铜柱凸块在晶片处理完成之后但在晶片被切割成单独的集成电路管芯之前形成在集成电路管芯的接合焊盘上。更具体地，在晶片处理结束时，晶片被涂覆有称为钝化层的最终介电层，其覆盖集成电路的所有有源电路，仅暴露接合焊盘。该钝化层通常使用二氧化硅或氮化硅来形成。然后，晶片的后端处理可以从晶片被处理的地方开始，以在晶片的暴露的接合焊盘上形成铜柱凸块。在形成铜柱凸块之后，然后将晶片切割成单独的集成电路管芯，并且将每个集成电路管芯以倒装芯片构造组装到封装基板上，其中铜柱凸块用作到封装基板的倒装芯片互连。
图1是在一些示例中采用铜柱凸块倒装芯片互连技术的封装集成电路的剖面图。参考图1，集成电路管芯12被封装在倒装芯片半导体封装10中。在该封装中，包括有源电路和用于外部连接的接合焊盘的集成电路管芯12的前侧面向下。铜柱凸块14形成在集成电路12的接合焊盘上，并用作集成电路管芯12和通常形成为印刷电路板(PCB)基板的封装基板20之间的电互连。集成电路管芯12以倒装芯片方式附接到封装基板20。底部填充材料16和坝状件18可以用在倒装芯片附接工艺中。
PCB封装基板20可以是单层或多层PCB。PCB封装基板20包括印刷在其上并形成在PCB中的导电迹线，用于接收形成在集成电路管芯20上的铜柱凸块，并将形成在基板的顶部侧的铜柱凸块电连接到形成在基板的底部侧的焊料球22的阵列。焊料球22形成半导体封装10的外部连接。
在本图示中，集成电路管芯被形成为绝缘体上硅集成电路。在集成电路管芯用于高压应用的情况下，在集成电路管芯12的背侧上的绝缘体基板上可能会有大量电荷堆积。在一些示例中，集成电路管芯12的背侧需要接地。因此，导电的顶部基板26形成在集成电路管芯12的背侧上，并通过导电粘合剂24附接到所述背侧。接合线28用于将顶部基板26电连接到封装基板20，以用于电接地连接。然后，整个结构被包封在模制化合物29中，以形成半导体封装10。
在铜柱凸块倒装芯片互连工艺中，已经观察到由于管芯翘曲导致的封装失效。图2示出了一个示例中由于管芯翘曲导致的封装失效模式。在倒装芯片互连工艺中，在铜柱凸块形成在晶片上之后，晶片经受背侧研磨至某个期望的管芯厚度。例如，晶片可以具有700μm的厚度，并且被背侧研磨至约100μm。然后，晶片被切割成单独的管芯12。在切割之后，集成电路管芯12上的某些应力导致管芯翘曲，如图2所示。管芯12上的翘曲阻止了管芯被正确地附接到封装基板20。特别地，由于管芯翘曲，一些铜柱凸块将不能与封装基板20上的导电迹线进行物理接触，从而导致在管芯的拐角处的开路连接，如图2所示。
管芯翘曲问题通常影响具有大管芯尺寸(例如10mm×10mm)和薄管芯厚度(例如100μm)的集成电路管芯。在一些情况下，管芯翘曲可以最高达70μm，为管芯厚度的70％。管芯尺寸大但管芯厚度薄的集成电路管芯上的管芯翘曲问题使得不可能通过倒装芯片方式接合到印刷电路板基板上。
管芯翘曲问题的常规解决方案涉及增加管芯厚度，例如仅将晶片背侧研磨至200μm或250μm厚度。然而，较厚的管芯尺寸有时是不希望的，因为封装厚度也增加了，这使得半导体封装对于某些应用是不希望的，例如在小型移动设备中。在一些情况下，相信管芯翘曲是由于在后端处理期间施加到集成电路管芯的前表面以形成铜柱凸块的聚酰亚胺材料。因此，针对管芯翘曲问题的一些常规解决方案涉及在集成电路管芯上使用具有较低固化温度或较低挠曲模量特性的聚酰亚胺材料。这些替代材料有时会增加半导体封装的成本。
附图说明
在以下详细描述和附图中公开了本发明的各种实施例。
图1是在一些示例中采用铜柱凸块倒装芯片互连技术的封装集成电路的剖面图。
图2示出了一个示例中由于管芯翘曲导致的封装失效模式。
包括图3(a)至图3(i)的图3示出了用于在半导体晶片的接合焊盘上形成铜柱凸块的常规后端处理步骤。
包括图4(a)和4(b)的图4是形成在半导体晶片上的铜柱凸块的剖面图和具有使用图3的常规后端处理步骤形成的铜柱凸块的集成电路管芯的俯视图。
包括图5(a)和5(b)的图5是在再分布层上形成的铜柱凸块的剖面图、以及在一些示例中具有在再分布层上形成的铜柱凸块的集成电路管芯的俯视图。
图6是图3和4中的半导体晶片的另一剖面图，示出了其上形成有多个铜柱凸块的晶片的较大部分。
图7是具有使用本发明的实施例中的半导体封装方法在其上形成的铜柱凸块的半导体晶片的剖面图。
包括图8(a)的图8是流程图，示出了在本发明的实施例中用于形成铜柱凸块的半导体封装方法。
包括图9(a)至图9(i)的图9示出了使用图8中的半导体封装方法在半导体晶片的接合焊盘上形成铜柱凸块的后端处理步骤。
包括图10(a)和10(b)的图10是形成在半导体晶片上的铜柱凸块的剖面图和具有使用图8的后端半导体封装方法形成的铜柱凸块的集成电路管芯的俯视图。
包括图11(a)和11(b)的图11是在本发明的一个实施例中使用再分布层的铜柱凸块的剖面图和使用半导体封装方法形成的集成电路管芯的俯视图。
包括图12(a)和12(b)的图12是在本发明的替代实施例中使用再分布层的铜柱凸块的剖面图和使用半导体封装方法形成的集成电路管芯的俯视图。
图13是流程图，示出了在本发明的实施例中使用再分布层形成铜柱凸块的半导体封装方法。
图14是流程图，示出了在本发明的实施例中使用再分布层形成铜柱凸块的半导体封装方法。
具体实施方式
本发明可以以多种方式实现，包括作为过程、设备、系统和/或物质的组合物。在本说明书中，这些实现或本发明可以采取的任何其他形式可以被称为技术。通常，可以在本发明的范围内改变所公开的过程的步骤的顺序。
下面提供本发明的一个或多个实施例的详细描述以及示出本发明的原理的附图。本发明结合这样的实施例进行描述，但本发明不限于任何实施例。本发明的范围仅由权利要求限制，并且本发明包括许多替代形式、修改和等同物。在以下的描述中阐述了许多具体细节，以便提供对本发明的透彻理解。这些细节是出于示例的目的而提供的，并且本发明可以根据权利要求在没有这些具体细节中的一些或全部细节的情况下实施。为了清楚起见，在与本发明相关的技术领域中已知的技术材料没有被详细描述，以免本发明被不必要地模糊化。
根据本发明的实施例，一种形成铜柱凸块半导体封装的方法包括将形成在铜柱凸块下方的有机绝缘层仅图案化(patterning)到铜柱凸块周围和附近的区域。该有机绝缘层(通常是薄膜聚合物层)用作铜柱凸块的阻挡层，以在铜柱凸块倒装芯片接合工艺期间保护半导体晶片。本发明的半导体封装方法限制了施加该有机绝缘层的区域，以减少由该有机绝缘层引入到半导体晶片的应力。
在其它实施例中，一种使用再分布工艺形成铜柱凸块半导体封装的方法包括将形成在铜柱凸块和再分布层下方的有机绝缘层图案化，以覆盖接合焊盘和凸块焊盘周围的区域，并沿着再分布层的路径形成有机绝缘层的岛(islands)。当在再分布层的顶部上使用第二有机绝缘层时，第二有机绝缘层也可以被图案化以覆盖接合焊盘和凸块焊盘周围的区域，并形成第二有机绝缘层的岛。第二有机绝缘层的岛可以相对于形成在再分布层下方的有机绝缘层的岛偏移。以这种方式，一个或多个有机绝缘层用来提供来自铜柱凸块工艺的应力消除。然而，没有形成有机绝缘层的大的连续区域，从而显著减小了由有机绝缘层引入到半导体晶片的应力。
在本说明书中，有机绝缘层是指在后端处理以形成铜柱凸块期间被施加到半导体晶片或涂覆半导体晶片以保护晶片的薄膜有机绝缘材料。该有机绝缘层也被称为晶片后处理介电层，因为该有机绝缘层是在半导体晶片已完成晶片制造工艺之后施加的，在晶片制造工艺中，半导体晶片形成有最终介电层(钝化层)，其覆盖半导体晶片的整个表面并且仅暴露接合焊盘。更具体地，钝化层(通常是二氧化硅层或氮化硅层)覆盖在半导体晶片上形成的集成电路管芯的所有有源电路，仅暴露接合焊盘。半导体晶片的后端处理涉及在半导体晶片的暴露的接合焊盘上形成铜柱凸块，以使形成在半导体晶片上的集成电路管芯能够随后被封装，例如被封装在倒装芯片半导体封装中。有机绝缘层在铜柱凸块形成之前被形成在成品半导体晶片上，并用于在半导体晶片和形成在其上的铜柱凸块之间提供机械应力缓冲。有机绝缘层通常是薄膜聚合物材料，例如聚酰亚胺(PI)或聚苯并恶唑(PBO)。
在常规的后端处理步骤中，半导体晶片的整个表面涂覆有有机绝缘材料，其中在接合焊盘上形成有用于铜柱凸块的开口。包括图3(a)至图3(i)的图3示出了用于在半导体晶片的接合焊盘上形成铜柱凸块的常规后端处理步骤。包括图4(a)和4(b)的图4是形成在半导体晶片上的铜柱凸块的剖面图和具有使用图3的常规后端处理步骤形成的铜柱凸块的集成电路管芯的俯视图。参考图3和图4二者，在前端晶片制造工艺之后，半导体晶片5形成有钝化层34，该钝化层34形成在其上形成有有源电路的半导体基板30上(图3(a))。图3仅示出了半导体晶片5的一部分，其中接合焊盘32形成在半导体基板30上。除了暴露的接合焊盘32之外，半导体基板30被钝化层34完全覆盖。接合焊盘32通常是铝接合焊盘或铜接合焊盘。
在后端处理步骤开始时，用有机绝缘材料涂覆半导体晶片5，从而形成有机绝缘层35(图3(b))。更具体地，该铜柱凸块倒装芯片接合工艺将大量应力引入到集成电路管芯。为了提高可靠性，在铜柱凸块形成之前，将介电层(通常是有机绝缘材料)施加到晶片以密封接合焊盘开口。有机绝缘层35涂覆晶片表面并且仅暴露接合焊盘32。该有机绝缘材料通常是聚酰亚胺，并且有机绝缘层35在本文中被称为聚酰亚胺层。
特别地，聚酰亚胺层35被图案化，例如通过使用掩模来图案化光致抗蚀剂层36，以在接合焊盘32上形成开口37。在该图案化过程之后，聚酰亚胺层35覆盖除了接合焊盘32上的开口37之外的整个半导体晶片5(图3(c))。然后，例如通过溅射，将种子金属层38沉积到半导体晶片S上(图3(d))。种子金属层38通常是通过溅射钛-铜(Ti-Cu)层、或钛-镍-铜(Ti-Ni-Cu)层、或钛/钨-铜(TiW-Cu)层、或铝-镍-铜(Al-Ni-Cu)层、或铬-铬/铜-铜(Cr-CrCu-Cu)层而形成的。在其它示例中，可以通过向晶片进行无电镀铜来沉积种子金属层38。种子金属层38用作电镀种子层，以将金属和铜柱电镀到所述柱的最终厚度。
然后可以开始铜柱凸块工艺。半导体晶片5涂覆有光致抗蚀剂层40，该光致抗蚀剂层40被图案化以暴露接合焊盘32上方的区域(图3(e))。通常通过金属电镀在光致抗蚀剂层40的开口中形成铜柱凸块14(图3(f))。在本示例中，铜柱凸块14包括下铜层42、镍粘附层44和焊料帽层(solder cap layer)46。在金属电镀工艺之后，光致抗蚀剂层40被去除(图3(g))。然后，种子金属层38被蚀刻以去除所有暴露的种子金属层38。因此，仅保留种子金属层38的在铜柱凸块14下方的部分(图3(h))。然后，半导体晶片经受回流焊接工艺，以完成铜柱凸块14的形成。更具体地，该回流焊接工艺使焊料帽层46变圆，以形成用于铜柱凸块的圆形焊料帽(图3(i))。
作为常规后端处理步骤的结果，除了形成有铜柱凸块的地方之外，整个半导体晶片都涂覆有聚酰亚胺层。图6是图3和图4中的半导体晶片5的另一剖面图，示出了其上形成有多个铜柱凸块14的晶片的较大部分。如图4(b)和图6所示，除了形成有铜柱凸块14的接合焊盘区域32之外，形成在半导体晶片5上的集成电路管芯12的整个表面都将被聚酰亚胺层35覆盖。聚酰亚胺层35用作阻挡层，以在铜柱凸块工艺期间保护半导体晶片并提高由此形成的集成电路的可靠性。然而，聚酰亚胺层将应力引入到半导体晶片，特别是在固化过程期间。
更具体地，聚酰亚胺和硅的热膨胀系数(CTE)具有大的不匹配，其中，与硅相比，聚酰亚胺具有随温度变化的大得多的热膨胀和收缩。例如，硅具有4ppm的CTE，而聚酰亚胺具有35ppm的CTE。聚酰亚胺层沉积在硅晶片上，然后在诸如350℃的高温下固化。在固化和该结构的温度下降之后，聚酰亚胺层收缩得比硅晶片大得多，从而将应力引入到硅晶片中。引入到硅晶片中的应力可能直到晶片被背侧研磨并切割成单独的集成电路管芯时才会表现出来。因此，像往常一样通过铜柱凸块工艺处理该晶片。在背侧研磨和晶片切割之后，来自聚酰亚胺层的应力经常导致各个管芯翘曲，使得不可能将管芯附接到封装基板(图2)。
在上述示例中，铜柱凸块直接形成在接合焊盘上。在其他示例中，铜柱凸块工艺可以使用再分布工艺来形成远离接合焊盘的铜柱凸块。再分布层(RDL)是诸如铜的金属层，并且形成在集成电路管芯上，以用作将接合焊盘重新导引到新的凸块位置的路线(runner)或迹线。以这种方式，凸块位置可以在集成电路管芯上重新布置，并且铜柱凸块的位置不受集成电路管芯上的接合焊盘的布局的限制。包括图5(a)和5(b)的图5是在再分布层上形成的铜柱凸块的剖面图、以及在一些示例中具有在再分布层上形成的铜柱凸块的集成电路管芯的俯视图。参考图5，首先用第一聚酰亚胺层35涂覆半导体晶片，该第一聚酰亚胺层35被图案化以暴露接合焊盘32。然后，将再分布层39沉积到晶片上和暴露的接合焊盘区域中。通常通过在下面的种子金属层38a上电镀铜来形成再分布层39。再分布层39形成到半导体晶片上的要形成铜柱凸块14的另一位置的金属迹线。用第二聚酰亚胺层40涂覆半导体晶片，该第二聚酰亚胺层40被图案化以在凸块焊盘区域形成开口，用于形成铜柱凸块14。然后，可以使用参照图3描述的工艺形成铜柱凸块14。如图5(b)所示，集成电路管芯12具有两个聚酰亚胺层35和40，聚酰亚胺层35和40覆盖管芯的除了接合焊盘(第一聚酰亚胺层)和凸块焊盘区域(第二聚酰亚胺层)之外的所有表面。
根据本发明的实施例，用于形成铜柱凸块的半导体封装方法仅将半导体晶片上的有机绝缘层图案化到铜柱凸块周围和附近的区域。从半导体晶片的所有其余区域去除有机绝缘层。以这种方式，显著减小或消除了由有机绝缘层引入到半导体晶片上的应力。本发明的半导体封装方法使得：即使对于大的管芯尺寸和薄的管芯厚度，也能够使用铜柱凸块倒装芯片技术。例如，本发明的半导体封装方法能够应用于具有大约10mm×10mm的管芯尺寸和100μm的管芯厚度的集成电路管芯。通过从不需要作为针对铜柱凸块处理提供屏障保护的区域去除有机绝缘材料，避免了管芯翘曲。
图7是具有使用本发明的实施例中的半导体封装方法在其上形成的铜柱凸块的半导体晶片的剖面图。参考图7，半导体晶片65包括其上形成有有源电路的半导体基板30。半导体晶片65已经完成前端晶片制造工艺，并且被作为晶片制造工艺的最终介电层的钝化层34覆盖。除了被暴露以用于外部连接的接合焊盘32之外，半导体晶片65的整个表面被钝化层34覆盖。本发明的半导体封装方法在接合焊盘32上形成铜柱凸块14。特别地，首先在成品半导体晶片65上形成有机绝缘层55。特别地，有机绝缘层55被图案化，以从除了要形成铜柱凸块的区域周围和附近之外的所有区域去除有机绝缘层55。然后形成铜柱凸块14，其中每个凸块14形成在种子金属层38上，并且每个凸块包括下铜层42、镍粘附层44和焊料帽层46。
如图6和图7之间的比较所示，除了铜柱凸块的下方、周围和附近之外，本发明的半导体封装方法从晶片表面去除了几乎所有有机绝缘材料。因此，不像常规方法(图6)中那样使有机绝缘材料覆盖所有半导体晶片，本发明的半导体封装方法形成有机绝缘层使得该有机绝缘材料仅覆盖半导体晶片的一小部分。以这种方式，显著减小或消除了由有机绝缘材料引入到半导体晶片上的应力，并且避免了由于该应力引起的管芯翘曲。
包括图8(a)的图8是流程图，示出了在本发明的实施例中用于形成铜柱凸块的半导体封装方法。将参照图9所示的处理步骤以及图10所示的剖面图和俯视图来描述图8的半导体封装方法。包括图9(a)至图9(t)的图9示出了使用图8中的半导体封装方法在半导体晶片的接合焊盘上形成铜柱凸块的后端处理步骤。包括图10(a)和10(b)的图10是形成在半导体晶片上的铜柱凸块的剖面图和具有使用图8的后端半导体封装方法形成的铜柱凸块的集成电路管芯的俯视图。参考图8、9和10，本发明的半导体封装方法100以已经完成前端晶片制造工艺的半导体晶片65开始(102)。在前端晶片制造工艺之后，半导体晶片65形成有钝化层34，该钝化层34形成在其上形成有有源电路的半导体基板30上(图9(a))。图9仅示出半导体晶片65的一部分，其中在半导体基板30上形成有接合焊盘32。除了暴露的接合焊盘32之外，半导体基板30被钝化层34完全覆盖。接合焊盘32通常是铝接合焊盘或铜接合焊盘。
半导体封装方法100通过用有机绝缘材料涂覆半导体晶片65开始后端处理以形成有机绝缘层55(104)，如图9(b)所示。该有机绝缘材料可以是聚酰亚胺(PI)或聚苯并恶唑(PBO)或其它合适的薄膜聚合物材料。有机绝缘层55然后被图案化，例如通过使用掩模来图案化光致抗蚀剂56，以去除除了接合焊盘32和钝化层34之间的界面周围的区域以外的任何地方的有机绝缘层55(106)，如图9(c)所示。更具体地，在图案化工艺之后，有机绝缘层55在晶片表面上的各个地方被去除，但它覆盖了接合焊盘32和钝化层34的边缘周围的区域。有机绝缘层55覆盖并围绕接合焊盘和钝化层的界面区域，其重叠宽度“w”足以用作要形成的铜柱凸块的应力缓冲层。接合焊盘32被暴露，并且钝化层34的其余部分也被暴露。
然后，如图9(d)所示，在半导体晶片65上沉积种子金属层38(108)。例如，通过溅射金属层来形成种子金属层38。在一些示例中，种子金属层38是通过溅射钛-铜(Ti-Cu)层、或钛-镍-铜(Ti-Ni-Cu)层、或钛/钨-铜(TiW-Cu)层、或铝-镍-铜(Al-Ni-Cu)层、或铬-铬/铜-铜(Cr-CrCu-Cu)层而形成的。在其它示例中，可以通过向晶片进行无电镀铜来沉积种子金属层38。种子金属层38用作电镀种子层，以将金属和铜柱电镀到所述柱的最终厚度。在一些示例中，种子金属层38具有在0.15μm和0.5μm之间的厚度。
方法100然后在种子金属层38上和接合焊盘上方形成铜柱凸块(110)。在一个示例中，可以使用图8(a)所示的方法形成铜柱凸块，其中半导体晶片65涂覆有光致抗蚀剂层40，该光致抗蚀剂层40被图案化以暴露接合焊盘32上方的区域(112)，如图9(e)所示。方法100然后例如通过使用金属电镀在光致抗蚀剂层40的开口中形成铜柱凸块结构14(114)，如图9(f)所示。在本实施例中，铜柱凸块14包括下铜层42、镍粘附层44和焊料帽层46。在金属电镀工艺之后，去除光致抗蚀剂层40(116)，并且形成铜柱凸块，如图9(g)所示。在形成铜柱凸块14之后，方法100继续进行到蚀刻种子金属层38，以去除所有暴露的种子金属层(118)。因此，仅保留种子金属层38的在铜柱凸块14下方的部分，如图9(h)所示。然后，方法100在半导体晶片65上执行回流焊接工艺，以完成铜柱凸块14的形成(120)。更具体地，该回流焊接工艺使焊料帽层46变圆，以形成用于铜柱凸块的圆形焊料帽，如图9(i)所示。
作为半导体封装方法100的结果，在半导体晶片65上形成铜柱凸块，其中，仅晶片的一小部分被有机绝缘材料覆盖，如图10(b)所示。特别地，有机绝缘层55被图案化以密封所述接合焊盘和钝化层的界面。有机绝缘层55可以被图案化为具有符合所述接合焊盘的圆形形状或正方形或矩形形状。如此形成的有机绝缘层55为半导体晶片65提供了必要的保护，因为所述接合焊盘和钝化层的界面区域是这样的区域：该区域需要针对铜柱凸块倒装芯片接合工艺的应力受到保护，并且可以受益于有机绝缘层的保护。半导体晶片的其它区域被钝化层覆盖，并且不需要有机绝缘层55的保护。本发明的半导体封装方法使得能够在不损害可靠性的情况下使用铜柱凸块倒装芯片技术，同时避免由于有机绝缘层的应力引起的管芯翘曲问题。
在上述实施例中，应用本发明的半导体封装方法来形成位于半导体晶片的接合焊盘上的铜柱凸块。在其它实施例中，本发明的半导体封装方法可以应用于使用再分布层的铜柱凸块工艺，以形成远离半导体晶片的接合焊盘的铜柱凸块。当铜柱凸块形成在再分布层上时，常规工艺使用两个聚酰亚胺层，如图5所描述的。根据本发明的实施例，半导体封装方法应用于使用再分布层的铜柱凸块工艺，其中一个或多个有机绝缘层被图案化，使得不形成有机绝缘层的大的连续区域。在一些实施例中，最上面的有机绝缘层被完全消除。
包括图11(a)和11(b)的图11是在本发明的一个实施例中使用再分布层的铜柱凸块的剖面图、以及使用半导体封装方法形成的集成电路管芯的俯视图。图13是流程图，示出了在本发明的实施例中使用再分布层形成铜柱凸块的半导体封装方法。参考图11和13，本发明的半导体封装方法200以已经完成前端晶片制造工艺的半导体晶片85开始(202)。在前端晶片制造工艺之后，半导体晶片85形成有钝化层34，该钝化层34形成在半导体基板30上，该半导体基板30上形成有有源电路。图11仅示出半导体晶片85的一部分，其中接合焊盘32形成在半导体基板30上。除了暴露的接合焊盘32之外，半导体基板30被钝化层34完全覆盖。接合焊盘32通常是铝接合焊盘或铜接合焊盘。
半导体封装方法200通过用有机绝缘材料涂覆半导体晶片85开始后端处理，以形成第一有机绝缘层75(204)。该有机绝缘材料可以是聚酰亚胺(PI)或聚苯并恶唑(PBO)或其它合适的薄膜聚合物材料。第一有机绝缘层75然后被图案化，例如通过使用掩模来图案化光致抗蚀剂，以去除除了接合焊盘32和钝化层34之间的界面周围的区域和形成凸块焊盘的区域以外的任何地方的有机绝缘层75(206)。第一有机绝缘层75被图案化以密封所述接合焊盘和钝化层的界面，并形成缓冲层作为待形成的铜柱凸块的凸块焊盘。第一有机绝缘层75被进一步图案化以沿着待形成的再分布层的路径形成有机材料的岛。该有机材料的岛可以具有约1mm至5mm的尺寸。更具体地，有机绝缘层75保留在用作待形成的铜柱凸块的应力缓冲层的区域中。接合焊盘32被暴露，并且钝化层34的其余部分也被暴露，如图11(b)所示。
然后，在半导体晶片85上沉积第一种子金属层38a(208)。在一些示例中，通过以与上文参照图8所述的相同的方式溅射金属层来形成第一种子金属层38a。然后，在半导体晶片85上在第一种子金属层38a的顶部上形成再分布层39(210)。在一些示例中，使用光致抗蚀剂来图案化半导体晶片85，以限定要形成再分布层的路线或迹线的区域。然后，使用电镀工艺在第一种子金属层38a上形成再分布金属化。第一种子金属层38a此时被蚀刻，以去除除了再分布层39下方之外的所有地方的第一种子金属层。在一些示例中，第一种子金属层38a具有在0.15μm至0.5μm之间的厚度。同时，再分布层具有在5μm至10μm之间的厚度。
方法200可以继续进行到在半导体晶片85上形成第二有机绝缘层80(212)。第二有机绝缘层80以类似于第一有机绝缘层的方式被图案化(214)，在图11所示的示例中，第二有机绝缘层80被形成为覆盖接合焊盘并限定凸块焊盘，该凸块焊盘暴露再分布层39并且铜柱凸块将形成在该凸块焊盘上。此外，第二有机绝缘层80被图案化以沿着所形成的再分布层的路径形成有机绝缘材料的岛。第二有机绝缘层的岛可以相对于第一有机绝缘层的岛偏移，如图11所示。
根据本发明的实施例，第一有机绝缘层和第二有机绝缘层被图案化，使得有机绝缘材料的足够区域被提供用于从铜柱凸块工艺中消除应力，但没有形成有机绝缘材料的大的连续区域而将应力引入到半导体晶片中。图11中形成在半导体晶片85上的有机绝缘层75和80的图案、尺寸和形状仅是说明性的，并非旨在是限制性的。可以在不将额外的应力引入到晶片中的情况下使用有机绝缘层的其它形状、尺寸和图案来实现所期望的应力消除。
方法200继续进行到在半导体晶片85上沉积第二种子金属层38b(216)。方法200然后在凸块焊盘上方在种子金属层38b上形成铜柱凸块(218)。在一个示例中，可以使用图8(a)中所示和上文所述的方法形成铜柱凸块。在形成铜柱凸块14之后，方法200继续进行到蚀刻种子金属层38b以去除所有暴露的种子金属层38b(220)。因此，仅保留种子金属层38b的在铜柱凸块14下方的部分，如图11(a)所示。然后，方法200在半导体晶片85上执行回流焊接工艺以完成铜柱凸块14的形成(222)。更具体地，该回流焊接工艺使焊料帽层变圆，以形成用于铜柱凸块的圆形焊料帽。
在本发明的替代实施例中，半导体封装方法被应用于使用再分布层形成铜柱凸块，其中第二有机绝缘层被完全省略，如图12所示。包括图12(a)和12(b)的图12是在本发明的替代实施例中、使用再分布层的铜柱凸块的剖面图和使用半导体封装方法形成的集成电路管芯的俯视图。图14是流程图，示出了在本发明的实施例中使用再分布层形成铜柱凸块的半导体封装方法。参考图12和14，本发明的半导体封装方法250以已经完成前端晶片制造工艺的半导体晶片95开始(252)。在前端晶片制造工艺之后，半导体晶片95形成有钝化层34，该钝化层34形成在其上形成有有源电路的半导体基板30上。图12仅示出了半导体晶片95的一部分，其中接合焊盘32形成在半导体基板30上。除了暴露的接合焊盘32之外，半导体基板30被钝化层34完全覆盖。接合焊盘32通常是铝接合焊盘或铜接合焊盘。
半导体封装方法250通过用有机绝缘材料涂覆半导体晶片95开始后端处理以形成第一有机绝缘层75(254)。该有机绝缘材料可以是聚酰亚胺(PI)或聚苯并恶唑(PBO)或其它合适的薄膜聚合物材料。第一有机绝缘层75然后被图案化，例如通过使用掩模来图案化光致抗蚀剂，以去除除了接合焊盘32和钝化层34之间的界面周围的区域和形成凸块焊盘的区域以外的任何地方的有机绝缘层75(256)。第一有机绝缘层75被进一步图案化以沿着待形成的再分布层的路径形成有机材料的岛。在一个实施例中，第一有机绝缘层75以与上文参照图13描述的相同方式被图案化。
然后，例如通过溅射，在半导体晶片95上沉积第一种子金属层38a(258)。然后，在半导体晶片95上在第一种子金属层38a的顶部上形成再分布层39(260)。在一些示例中，使用光致抗蚀剂来图案化半导体晶片95，以限定要形成有再分布层的路线或迹线的区域。然后，使用电镀工艺在第一种子金属层38a上形成再分布金属化。第一种子金属层38a此时被蚀刻，以去除除了再分布层39下方之外的所有地方的第一种子金属层。
方法250然后继续进行到在半导体晶片95上沉积第二种子金属层38b(262)，而不使用任何更多的有机绝缘层。方法250然后在凸块焊盘上方在种子金属层38b上形成铜柱凸块(264)。在一个示例中，可以使用图8(a)中所示和上文所述的方法形成铜柱凸块。在形成铜柱凸块14之后，方法250继续进行到蚀刻种子金属层38b以去除所有暴露的种子金属层38b(266)。因此，仅保留种子金属层38b的在铜柱凸块14下方的部分，如图12(a)所示。然后，方法250在半导体晶片95上执行回流焊接工艺以完成铜柱凸块14的形成(268)。更具体地，该回流焊接工艺使焊料帽层变圆，以形成用于铜柱凸块的圆形焊料帽。
在图12所示的实施例中，铜柱凸块14形成在再分布层39上，而不使用第二有机绝缘层。尽管在该封装阶段、再分布层39暴露在半导体晶片中，但后续的封装工艺将封装该集成电路管芯，例如使用环氧树脂材料，从而密封和保护所述再分布层。
尽管为了清楚理解的目的已经详细描述了前述实施例，但本发明不限于所提供的细节。有许多实现本发明的替代方式。所公开的实施例是说明性而非限制性的。

Claims (20)

1.一种形成铜柱凸块半导体封装的方法，包括：
提供成品半导体晶片，所述成品半导体晶片包括半导体基板，所述半导体基板上形成有钝化层，所述钝化层覆盖所述半导体基板的顶表面并暴露接合焊盘；
在所述半导体晶片上形成有机绝缘层；
图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的界面处的区域，所述有机绝缘层被去除以暴露所述接合焊盘并且被从所述半导体晶片的剩余区域去除；
在所述有机绝缘层和所述半导体晶片上形成种子金属层；
在所述接合焊盘上方在所述种子金属层上形成铜柱凸块；
去除未形成在所述铜柱凸块下方的所述种子金属层；以及
回流焊所述铜柱凸块。
2.根据权利要求1所述的方法，其中，在所述半导体晶片上形成所述有机绝缘层包括：
在所述半导体晶片上形成所述有机绝缘层，所述有机绝缘层包括薄膜聚合物材料。
3.根据权利要求2所述的方法，其中，所述有机绝缘层包括聚酰亚胺(PI)或聚苯并恶唑(PBO)。
4.根据权利要求1所述的方法，其中，图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的界面处的区域包括：
图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域，所述有机绝缘层以重叠宽度与所述界面重叠以提供用于待形成的所述铜柱凸块的应力缓冲层，所述有机绝缘层被去除以暴露所述接合焊盘并且被从所述半导体晶片的剩余区域去除。
5.根据权利要求4所述的方法，其中，图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域包括：
以圆形形状来图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域，所述有机绝缘层以重叠宽度与所述界面重叠以提供用于待形成的所述铜柱凸块的所述应力缓冲层，所述有机绝缘层被去除以暴露所述接合焊盘并且被从所述半导体晶片的所述剩余区域去除。
6.根据权利要求4所述的方法，其中，图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域包括：
以矩形形状图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域，所述有机绝缘层以重叠宽度与所述界面重叠以提供用于待形成的所述铜柱凸块的所述应力缓冲层，所述有机绝缘层被去除以暴露所述接合焊盘并且被从所述半导体晶片的所述剩余区域去除。
7.根据权利要求1所述的方法，其中，在所述半导体晶片上形成所述有机绝缘层和图案化所述有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的界面处的所述区域包括：
形成所述有机绝缘层以覆盖所述半导体晶片的整个表面；和
图案化所述有机绝缘层，以从所述半导体晶片的除了位于所述接合焊盘与所述钝化层的所述界面处的所述区域之外的表面去除所述有机绝缘层。
8.一种形成铜柱凸块半导体封装的方法，包括：
提供成品半导体晶片，所述成品半导体晶片包括半导体基板，所述半导体基板上形成有钝化层，所述钝化层覆盖所述半导体基板的顶表面并暴露接合焊盘；
在所述半导体晶片上形成第一有机绝缘层；
图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的界面处的第一区域，覆盖待形成的凸块焊盘的第二区域并沿着待形成的再分布层的从所述接合焊盘到所述凸块焊盘的路径形成所述第一有机绝缘层的岛，所述第一有机绝缘层被从所述接合焊盘去除并且被从所述半导体晶片的除了所述第一区域、所述第二区域和所述第一有机绝缘层的所述岛之外的剩余区域去除；
在所述第一有机绝缘层和所述半导体晶片上形成第一种子金属层；
在所述接合焊盘和所述第一有机绝缘层上方在所述半导体晶片上形成所述再分布层，所述再分布层被形成为包括与所述接合焊盘间隔开的所述凸块焊盘和将所述接合焊盘连接到所述凸块焊盘的导电迹线，所述凸块焊盘形成在所述第一有机绝缘层的所述第二区域上方，并且所述导电迹线形成在所述第一有机绝缘层的所述岛上方；
去除未形成在所述再分布层下方的所述第一种子金属层；
在所述再分布层和所述半导体晶片上形成第二种子金属层；
在所述凸块焊盘上方在所述第二种子金属层上形成铜柱凸块；
去除未形成在所述铜柱凸块下方的所述第二种子金属层；以及
回流焊所述铜柱凸块。
9.根据权利要求8所述的方法，其中，在所述半导体晶片上形成所述第一有机绝缘层包括：
在所述半导体晶片上形成所述第一有机绝缘层，所述第一有机绝缘层包括薄膜聚合物材料。
10.根据权利要求9所述的方法，其中，所述第一有机绝缘层包括聚酰亚胺(PI)或聚苯并恶唑(PBO)。
11.根据权利要求8所述的方法，其中，图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述第一区域包括：
图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述第一区域，所述第一有机绝缘层与所述界面以重叠宽度重叠，所述第一有机绝缘层被从所述接合焊盘去除并且被从所述半导体晶片的除了所述第一区域、所述第二区域和所述第一有机绝缘层的所述岛之外的所述剩余区域去除。
12.根据权利要求11所述的方法，其中，图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述第一区域包括：
以圆形形状图案化来所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述第一区域，所述第一有机绝缘层与所述界面以重叠宽度重叠，所述第一有机绝缘层被从所述接合焊盘去除并且被从所述半导体晶片的除了所述第一区域、所述第二区域和所述第一有机绝缘层的所述岛之外的所述剩余区域去除。
13.根据权利要求11所述的方法，其中，图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述区域包括：
以矩形形状图案化所述第一有机绝缘层以覆盖位于所述接合焊盘与所述钝化层的所述界面处的所述第一区域，所述第一有机绝缘层与所述界面以重叠宽度重叠，所述第一有机绝缘层被从所述接合焊盘去除并且被从所述半导体晶片的除了所述第一区域、所述第二区域和所述第一有机绝缘层的所述岛之外的所述剩余区域去除。
14.根据权利要求8所述的方法，其中，在所述半导体晶片上形成所述第一有机绝缘层和图案化所述第一有机绝缘层包括：
形成所述第一有机绝缘层以覆盖所述半导体晶片的整个表面；和
图案化所述第一有机绝缘层，以便除了在所述接合焊盘与所述钝化层的所述界面处的所述第一区域、待形成的所述凸块焊盘的所述第二区域和所述第一有机绝缘层的所述岛处之外，从所述半导体晶片的表面去除所述有机绝缘层。
15.根据权利要求8所述的方法，其中，在所述半导体晶片上形成所述再分布层包括：
图案化所述半导体晶片以暴露要形成所述再分布层的区域；和
通过电镀在暴露区域中形成铜层，作为所述半导体晶片上的所述再分布层。
16.根据权利要求8所述的方法，还包括：
在去除所述第一种子金属层之后但形成所述第二种子金属层之前，在所述再分布层上方在所述半导体晶片上形成第二有机绝缘层；和
图案化所述第二有机绝缘层，以覆盖所述接合焊盘上方和周围的第三区域，覆盖所述凸块焊盘周围的第四区域，并沿着所述再分布层的从所述接合焊盘到所述凸块焊盘的路径形成所述第二有机绝缘层的岛，所述第二有机绝缘层被从所述凸块焊盘去除并且被从所述半导体晶片的除了所述第三区域和所述第四区域之外的剩余区域去除，
其中，所述第二种子金属层在所述第二有机绝缘层和由所述再分布层形成的所述凸块焊盘上方形成在所述半导体晶片上。
17.根据权利要求16所述的方法，其中，所述第二有机绝缘层的所述岛相对于所述第一有机绝缘层的所述岛偏移。
18.根据权利要求16所述的方法，其中，在所述再分布层上方在所述半导体晶片上形成所述第二有机绝缘层包括：
在所述再分布层上方在所述半导体晶片上形成所述第二有机绝缘层，所述第二有机绝缘层包括薄膜聚合物材料。
19.根据权利要求18所述的方法，其中，所述第二有机绝缘层包括聚酰亚胺(PI)或聚苯并恶唑(PBO)。
20.根据权利要求16所述的方法，其中，在所述半导体晶片上形成所述第二有机绝缘层和图案化所述第二有机绝缘层包括：
形成所述第二有机绝缘层以在所述再分布层上方覆盖所述半导体晶片的整个表面；和
图案化所述第二有机绝缘层，以便除了在所述接合焊盘上方和周围的所述第三区域、所述凸块焊盘周围的所述第四区域以及所述第二有机绝缘层的所述岛处之外，从所述半导体晶片的表面去除所述第二有机绝缘层。
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