CN109917192B - Power MOSFET device on-resistance and output capacitance testing device based on damped oscillation wave - Google Patents
Power MOSFET device on-resistance and output capacitance testing device based on damped oscillation wave Download PDFInfo
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Abstract
The invention discloses a device for testing the on-resistance and the output capacitance of a power MOSFET device based on damped oscillation waves, which comprises a tested power MOSFET device at the front end, a peripheral test circuit thereof and a sampling control system at the rear end, wherein the tested power MOSFET device is connected with the output capacitance of the power MOSFET device; the test circuit comprises an adjustable direct-current power supply, a fuse, an adjustable inductor, a voltage sampling resistor, a divider resistor and a current sampling resistor, and the sampling control system comprises an operational amplifier module, an AD module, a CPU module, a driving module and an upper computer. The measuring method is simple and convenient, the device cost is low, the avalanche tolerance, the on-resistance and the output capacitance of the power MOSFET device can be measured simultaneously, and the operation is simple and efficient.
Description
Technical Field
The invention belongs to the technical field of semiconductor testing, and particularly relates to a device for testing on-resistance and output capacitance of a power MOSFET device based on damped oscillation waves.
Background
A power MOSFET (Metal-Oxide-Semiconductor Field-Effect transistor) device plays an important role in high-frequency power conversion due to its advantages of high frequency, low driving power, strong anti-interference energy, high cost performance, and the like, and thus, the power MOSFET device is integrated in modern electronic components.
For example, in the automotive field, which drives Inductive loads such as motors and alternators, these power MOSFET devices need to withstand the energy spikes of Undamped Inductive Switching (UIS). The switching process under non-clamped inductive load is generally considered to be the most extreme stress situation that a power MOSFET device can be subjected to in system applications, because the energy stored in the inductor must be fully released by the power device at the moment of turn-off when the loop is turned on, and the high voltage and large current applied to the power device are very likely to cause device failure, and the damage caused by the failure is usually irreparable, so the avalanche tolerance is usually an important index for reliable performance of the power device.
When considering a power MOSFET device operating in a switching mode, the goal is to switch between the minimum and maximum resistance states of the device in as short a time as possible; due to the parasitic capacitance of the power MOSFET device, the actual switching time of the power MOSFET device is at least 2-3 orders of magnitude longer than the theoretical switching time, so in the application of high-speed switching, the most important parameter is the parasitic capacitance of the device.
In summary, it is very necessary to measure the avalanche capability, the on-resistance and the output capacitance of the power MOSFET device, and most of the existing measuring devices can only measure the avalanche capability, the on-resistance or the output capacitance individually, which has the problems of low measuring efficiency and high cost, and cannot realize the simultaneous measurement of a plurality of characteristic parameters. The output capacitance of the power MOSFET device is mainly measured by combining an LCR tester and a test circuit, and the change curve of the output capacitance of the power MOSFET device along with the voltage between drain and source electrodes of the device under a certain condition can be drawn by changing the output voltage of a direct-current voltage source in the test circuit to measure the corresponding output capacitance; the LCR tester, although simply connected to a test circuit, causes large errors due to contact resistance, series impedance of the connection cable, and stray capacitance between the connection cable and the terminals.
Disclosure of Invention
In view of the above, the present invention provides a device for testing the on-resistance and the output capacitance of a power MOSFET device based on a damped oscillatory wave, which has low device cost and simple measurement method, and can simultaneously measure the avalanche tolerance, the on-resistance and the output capacitance of the power MOSFET device.
A device for testing the on-resistance and the output capacitance of a power MOSFET device based on damped oscillation waves comprises: the device comprises a tested power MOSFET device at the front end, a peripheral test circuit thereof and a sampling control system at the rear end; the test circuit comprises an adjustable DC power supply, a fuse, an adjustable inductor and a voltage sampling resistor RU1A voltage dividing resistor RU2And a current sampling resistor RIWherein: the anode of the adjustable direct current power supply is connected with one end of a fuse, the other end of the fuse is connected with one end of an adjustable inductor, and the other end of the adjustable inductor is connected with the drain electrode of the tested power MOSFET device and a divider resistor RU2One end phase ofConnecting, voltage-dividing resistor RU2And the other end of the voltage sampling resistor RU1Is connected with a sampling control system, a voltage sampling resistor RU1And the other end of the current sampling resistor R, the negative electrode of the adjustable direct current power supply and the current sampling resistor RIIs connected to ground and is connected to a current sampling resistor RIThe other end of the sampling control system is connected with the source electrode of the tested power MOSFET device and the sampling control system, and the grid electrode of the tested power MOSFET device is connected with a switch control signal provided by the sampling control system;
the sampling control system comprises an operational amplifier module, an AD module, a CPU module, a driving module and an upper computer; wherein:
the operational amplifier module is used for receiving the current RICurrent signal and RU1The two groups of signals are respectively conditioned and shaped;
the AD module is used for carrying out AD sampling on the conditioned and shaped current signal and voltage signal;
the CPU module comprises a CPLD (Complex Programmable Logic Device) and a static storage module, wherein the CPLD receives a test instruction output by the upper computer and then generates a corresponding pulse signal, the pulse signal is amplified by the power of the driving module to generate a corresponding switch control signal and output the signal to the grid of the power MOSFET Device to be tested so as to control the switch state of the power MOSFET Device to be tested, meanwhile, the CPLD also receives sampling signal data output by the AD module and stores the sampling signal data into the static storage module, and when needed, the CPLD calls the sampling signal data from the static storage module and transmits the sampling signal data to the upper computer;
the upper computer is used for receiving test parameters input by user settings so as to output corresponding test instructions to the CPU module, receiving sampling signal data provided by the CPU module so as to display voltage waveform between a drain electrode and a source electrode and current waveform flowing through a drain electrode and a source electrode in the avalanche tolerance test process of the tested power MOSFET device in real time, judging whether the tested power MOSFET device is subjected to avalanche breakdown or not, and calculating avalanche tolerance, on-resistance and output capacitance of the tested power MOSFET device according to the voltage and the current.
Further, the test instruction output by the upper computer comprises test condition parameters and a test mode, wherein the test condition parameters comprise the output voltage of the adjustable direct-current power supply, the inductance value of the adjustable inductor and the pulse width, and the test mode is a single pulse avalanche tolerance test or a repeated pulse avalanche tolerance test.
Further, the operational amplifier module comprises a sampling voltage conditioning circuit and a sampling current conditioning circuit.
The sampling voltage conditioning circuit comprises two operational amplifiers U1-U2, seven resistors R1-R7 and three capacitors C1-C3; wherein, one end of the resistor R1 is connected with the voltage signal, the other end of the resistor R1 is connected with one end of the resistor R2 and the non-inverting input end of the operational amplifier U1, the other end of the resistor R2 is connected with one end of the resistor R3 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the other end of the resistor R3 is connected with +5V working voltage, the inverting input end and the output end of the operational amplifier U1 are connected with one end of the resistor R7, the other end of the resistor R7 is connected with one end of the resistor R5, one end of the capacitor C3 and the inverting input end of the operational amplifier U2, the other end of the resistor R5 is connected with the other end of the capacitor C24 and the output end of the operational amplifier U2 and outputs the conditioned voltage signal, the non-inverting input end of the operational amplifier U2 is connected with one end of the resistor R9, one end of the capacitor C2 and one end of the resistor R6, the other end of the resistor R6 is connected with the +5V working voltage.
The sampling current conditioning circuit comprises two operational amplifiers U3-U24, four resistors R8-R11 and a capacitor C4; the non-inverting input end of the operational amplifier U3 is connected with the current signal, the inverting input end of the operational amplifier U3 is connected with one end of a resistor R9, one end of a capacitor C4 and one end of a resistor R8, the other end of the resistor R8 is grounded, the other end of a resistor R9 is connected with the other end of a capacitor C4, the output end of the operational amplifier U3 and one end of a resistor R10, the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U4 and one end of the resistor R11, the other end of the resistor R11 is grounded, and the inverting input end and the output end of the operational amplifier U4 are connected in common and output the conditioned and.
Further, the upper computer calculates the avalanche tolerance of the tested power MOSFET device according to the following relational expression;
wherein: e is the avalanche tolerance of the tested power MOSFET device, L is the inductance value of the adjustable inductor, and VCCFor regulating the output voltage of the DC power supply, IASFor the current flowing through the drain-source of the tested power MOSFET device at tpPeak value reached in time interval, BVdsThe breakdown voltage between the drain and the source after the tested power MOSFET device enters into avalanche state (i.e. from the falling edge of the pulse), tpCorresponding to a pulse width period (i.e., the on period of the power MOSFET device under test).
Further, the upper computer calculates the on-resistance of the tested power MOSFET device according to the following relational expression;
wherein: rds(on)Is the on-resistance, V, of the power MOSFET device under testdsIs tpVoltage between drain and source of MOSFET device under test during time period, IdIs tpCurrent flowing through drain-source of the power MOSFET device under test during the time period, tpCorresponding to a pulse width period.
Further, the specific implementation process of the upper computer for calculating the output capacitance of the tested power MOSFET device is as follows:
(1) in the avalanche tolerance test process, the voltage waveform between the drain and the source of the tested power MOSFET device generates decaying oscillation after being turned off, so that N continuous sampling points X are intercepted from the decaying oscillation wave band of the voltage signal1～XNAs a sampling sequence, N is a natural number greater than 1;
(2) these N sampling points X are measured according to the following formula1～XNPreprocessing the voltage value;
V'(Xi)＝V(Xi)-VCC
wherein: v' (X)i) And V1(Xi) Respectively as sampling points X before and after pretreatmentiI is a natural number, i is more than or equal to 0 and less than or equal to N, VCCIs the output voltage of the adjustable direct current power supply;
(3) for these N sampling points X1～XNObtaining the wave crests of the voltage waveform in each oscillation period by a method of solving a maximum value after the voltage waveform is preprocessed, and obtaining 2n wave crests in total, wherein n is half of the number of the oscillation periods of the voltage waveform;
(4) dividing 2n wave crests into two groups, and calculating the oscillation period T by adopting a step-by-step difference methoddThe specific algorithm formula is as follows:
wherein: t is1(1)、T1(2)…T1(n) generation time corresponding to the first n peaks, T2(1)、T2(2)…T2(n) corresponding to the generation time of the last n peaks;
(5) finally, the output capacitance C of the MOSFET device of the power to be measured is calculated according to the following formulaoss；
Wherein: and L is the inductance value of the adjustable inductor.
Based on the technical scheme, the invention has the following beneficial technical effects:
1. the method for testing the on-resistance and the output capacitance of the power MOSFET device based on the damped oscillation waves is simple and convenient in measurement mode and low in device cost.
2. The invention can realize the simultaneous measurement of the avalanche tolerance, the on-resistance and the output capacitance of the power MOSFET device, and has simple and efficient operation.
Drawings
Fig. 1 is an equivalent model diagram of a power MOSFET device to be tested.
Fig. 2 is a schematic diagram of an equivalent oscillation circuit in the measurement circuit.
FIG. 3 is a schematic diagram of the circuit principle and structure of the testing device of the present invention.
FIG. 4 is a diagram showing an actual waveform of the drain-source voltage of the power MOSFET device under test.
FIG. 5 is a waveform diagram of the pre-processed drain-source voltage ringing band of the power MOSFET device under test.
Fig. 6 is a schematic circuit diagram of an operational amplifier module in the testing apparatus according to the present invention.
Fig. 7 is a waveform diagram illustrating the drain-source voltage and the drain-source current flowing through the power MOSFET device under test during the avalanche resistance test.
Detailed Description
In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.
As shown in fig. 3, the on-resistance and output capacitance online test device for power MOSFET device based on damped oscillatory waves of the present invention includes a front-end avalanche test circuit, a sampling circuit and a back-end control module.
The front-end avalanche test circuit 101 comprises an adjustable direct-current power supply V, a fuse, an adjustable inductor L1, a power MOSFET device to be tested and a current sampling resistor RI(ii) a The positive electrode of the adjustable direct current power supply V is connected with the fuse; the other end of the fuse is connected with an inductor L1; the other end of the inductor L1 is connected with the drain electrode of the MOSFET device to be tested; source electrode and current sampling resistor R of MOSFET device to be testedIConnecting; current sampling resistor RIThe other end of the voltage regulator is connected with a grounding wire and the negative electrode of an adjustable direct current power supply V; receiving a pulse signal by a grid electrode of the MOSFET device to be tested; in this embodiment, the adjustable dc power V is adjusted within a range of 0-100V, and the adjustable test inductor L1 is adjusted within a range of 0-30 mH.
The structure of the rear-end avalanche voltage and current sampling circuit and the control module comprises a current sampling resistor RIVoltage sampling resistor RU1A voltage dividing resistor RU2Operational amplifier module 102, AD module 103 and driverModule 104, CPU module 105, and upper computer 106; source electrode and current sampling resistor R of MOSFET device to be testedIConnecting; current sampling resistor RIThe other end of the voltage regulator is connected with a grounding wire and the negative electrode of an adjustable direct current power supply V; the CPU module 105 is connected with the driving module 104; the operational amplifier module 102 receives the sampling voltage signal and the sampling current signal, conditions and shapes the signals, outputs a detection voltage signal and a detection current signal to the AD module 103, and the AD module 103 performs analog-to-digital conversion according to the received detection voltage signal and detection current signal and outputs the signals to the CPU module 105; the upper computer 106 communicates with the CPU module 105.
The avalanche voltage current sampling circuit comprises a source electrode of a power MOSFET device to be tested and a current sampling resistor RIIs connected to a current sampling resistor RIThe other end of the first and second electrodes is grounded; parallel divider resistor R between drain electrode and source electrode of power MOSFET device to be testedU2And a voltage sampling resistor RU1. In this embodiment, the current sampling resistor RIUsing milliohm-level, voltage-sampling resistors RU1The megaohm scale is used.
As shown in fig. 6, the operational amplifier module 102 includes a voltage operational amplifier module and a current operational amplifier module, the voltage operational amplifier module is composed of seven resistors R1-R7, three capacitors C1-C3 and two operational amplifiers U1-U2, wherein one end of a resistor R1 is used as a sampling voltage signal input end, the other end of the resistor R3 is connected to one end of a resistor R2 and the positive input end of an operational amplifier U1, the other end of the resistor R2 is connected to one end of a resistor R3 and one end of a capacitor C1, the other end of the capacitor C1 is grounded, the other end of the resistor R3 is connected to a +5V power supply voltage, the inverting input end of the operational amplifier U1 is connected to one end of a resistor 686r 9 and the output end of an operational amplifier U1, one end of a resistor R4 and one end of a capacitor C2 are connected to one end of a resistor R3 and the positive input end of an operational amplifier U2, the other end of a resistor R4 is connected to the other end of a capacitor C2 and the, the other end of the resistor R7 and one end of the resistor R5 are connected with one end of the capacitor C3 and the reverse input end of the operational amplifier U2, and the other end of the resistor R5 is connected with the other end of the capacitor C3 and the output end of the operational amplifier U2 to form the output end of the voltage operational amplifier module and output a detection voltage signal.
The current operational amplifier module is composed of four resistors R8-R11, a capacitor C4 and two operational amplifiers U3-U4, wherein a forward input end of the operational amplifier U3 serves as a sampling voltage signal input end, an inverting input end of the operational amplifier U3 and one end of the resistor R9 are connected with one end of the capacitor C4 and one end of the resistor R8, the other end of the resistor R8 is grounded, the other ends of the resistor R9 and the capacitor C4 are connected with one end of the resistor R10 and an output end of the operational amplifier U3, the other end of the resistor R10 is connected with one end of the resistor R11 and the forward input end of the operational amplifier U4, the other end of the resistor R11 is grounded, and an inverting input end of the operational amplifier U4 is connected with the output end of the operational amplifier U4 to form an output end of the current sampling module and output a detection.
The AD module 103 is connected to the operational amplifier module 102, and includes a voltage analog-to-digital conversion circuit and a current analog-to-digital conversion circuit, which respectively receive the detection voltage signal and the detection current signal conditioned and shaped by the operational amplifier module 102, and perform analog-to-digital conversion on the signals and output the signals to the control module. In this embodiment, the AD module 103 is composed of two AD chips, and the AD sampling chip is an AD9220 chip of Analog Device corporation.
The control module comprises a CPU module 105 and an upper computer 106; the CPU module 105 comprises a CPLD control center and a static storage module, wherein the CPLD control center generates a pulse signal to control the on or off of the MOSFET device to be tested after receiving the test signal output by the upper computer 106, receives the sampling data output by the AD module 103, stores the sampling data into the static storage module, and can also read the data from the static storage module and transmit the data to the upper computer 106; the upper computer 106 is used for setting instructions and outputting instructions including test conditions and test modes, receiving detection voltage and detection current signals output by the CPU module 105 after avalanche test starts, displaying drain-source voltage waveforms and current oscillograms flowing through the drain-source in the avalanche tolerance test process of the tested MOSFET device, judging whether the tested MOSFET device is subjected to avalanche breakdown or not, analyzing the test waveforms, and realizing calculation of avalanche energy of the tested MOSFET device. In this embodiment, the CPU module 105 IS composed of an MCU chip, the static memory module IS composed of two static RAM chips, the upper computer 106 IS constructed based on the MATLAB platform, the MCU chip IS an EPM570T144C5N chip of Altera corporation, and the static RAM chip IS an IS61WV102416BLL chip of ISSI corporation.
The control module outputs instructions including set test conditions and a selected test mode, the test conditions include adjustable direct current power supply output voltage, adjustable inductance test size and pulse width, and the test mode includes single pulse avalanche energy test and repeated pulse avalanche energy test.
In this embodiment, a method for testing the on-resistance and the output capacitance of a power MOSFET device using an avalanche tolerance test platform includes the following steps:
(1) the upper computer 106 inputs parameters such as an adjustable direct current voltage source, a test value of an adjustable inductor, an avalanche tolerance test mode, a pulse width and the like adopted by the avalanche tolerance test at this time in correspondence to the setting columns, adjusts and confirms that the test circuits are consistent, and sends an output instruction to the CPU module 105 after completion to start the avalanche tolerance test.
(2) Taking a single-pulse avalanche energy test as an example, after the avalanche tolerance test is started, the CPU module 105 receives the operating condition of the avalanche tolerance test and the test mode signal, outputs a single-pulse signal with a set width to the driving module, and controls the operational amplifier module 102 and the AD module 103 to start operating.
(3) The single pulse signal controls the on and off of the power MOSFET device to be tested through the driving module, the power MOSFET device to be tested which is connected in the non-clamping inductive circuit in series formally enters the stage of avalanche tolerance test, when the power MOSFET device is switched on, the inductive current rises, the power MOSFET device is switched off after a certain time, and at the moment, the drain-source voltage V isdsRising rapidly, as shown in fig. 7, the energy stored on the inductor during the switch turn-on period is dissipated through the power MOSFET device.
(4) After the sampling voltage signal and the sampling current signal in the testing stage are amplified by the operational amplifier module 102, the signals are output to the CPU module 105 through analog-to-digital conversion of the AD module 103, the CPU module 105 outputs the sampling current and the sampling voltage signal to the upper computer 106, the upper computer 106 receives data and respectively displays the MOSFET device to be tested in the avalanche energy testing processPlot of drain current and drain-source voltage waveforms, with corresponding peak currents IASSum voltage BVds. Judging whether the tested power MOSFET device is damaged by avalanche through a oscillogram, and when the tested power MOSFET device is not damaged by avalanche, calculating the avalanche energy of the power MOSFET device in the test according to the following formula:
wherein: l is the inductance of the adjustable inductor L1, VCCFor regulating the output voltage of the DC power supply, IASFor the current flowing through the drain-source of the tested power MOSFET device at tpPeak value reached in time interval, BVdsThe breakdown voltage between the drain and the source after the tested power MOSFET device enters into avalanche state (i.e. from the falling edge of the pulse), tpCorresponding to a pulse width period.
The upper computer 106 calculates and displays avalanche energy of the MOSFET device to be tested and judges whether the MOSFET to be tested is damaged by avalanche.
(5) As shown in fig. 7, for tpAnalyzing the voltage and current in a time period, charging an inductor, gradually increasing the current flowing through the MOSFET, gradually increasing the voltage of a drain electrode and a source electrode along with the change of the current to obtain tpOn-resistance value in time period:
wherein: vdsIs tpDrain-source voltage of MOSFET device under test during time period, IdIs tpAnd the current flowing through the drain-source electrode of the tested MOSFET device in the time period.
R obtained by the above calculationds(on)Drawing a waveform to obtain the conduction from the beginning to t of the tested MOSFET devicepCurve of on-resistance over time.
(6) FIG. 1 is an equivalent model of a conventional non-ideal MOSFET device, where Cgd、CgsAnd CdsAre respectively asInterelectrode capacitance between gate, drain and source, LdAnd LsParasitic inductances of a drain electrode and a source electrode respectively; rgIs a gate parasitic resistance; the relationship between the input capacitance and the interelectrode capacitance is as follows:
Coss＝Cgd+Cds
because of the parasitic components of the power MOSFET device, an oscillation circuit is formed among the loop resistance, the output capacitance of the MOSFET device and the loop inductance when the power MOSFET device is turned off, as shown in FIG. 2, wherein RsumIs the total resistance value in the second-order circuit, LsumIs the total inductance in the second order circuit (L is much greater than the parasitic inductance due to the test inductance LsumCan be approximated as a test inductance L).
When the tested MOSFET device is not subjected to avalanche damage, the avalanche test voltage waveform of the actual power MOSFET device generates a decaying oscillation wave when being turned off, as shown in FIG. 4; intercepting the decaying oscillation wave band of the voltage waveform of the drain electrode and the source electrode of the power MOSFET device obtained by the upper computer 106 for further analysis, and obtaining N continuous sampling points X of the decaying oscillation wave signal of the voltage signal1～XNAs a sampling sequence, N is a freely selected natural number greater than 1.
(7) For N sampling points X according to the following formula1～XNThe voltage value is preprocessed to obtain preprocessed voltage values of each sampling point:
V'(Xi)＝V(Xi)-VCC
wherein: v' (X)i) And V1(Xi) Respectively as sampling points X before and after pretreatmentiI is a natural number and is more than or equal to 0 and less than or equal to N.
The preprocessed sampled voltage ringing waveform is shown in fig. 5; on the basis of N sampling voltage data, a peak in each oscillation period of the sampling voltage damped oscillation waveform is obtained by a method of solving a maximum value, but when the oscillation frequency is higher, the captured peak has deviation with the actual waveform, so that the error is increased; to reduce such errors, the oscillation period T is determined by a difference-by-difference methodd。
Extracting N preprocessed sampling voltagesThe number of wave crests in each oscillation period in the oscillation waveform is 2n, the 2n wave crests are divided into two groups, and the oscillation period T is obtained according to the following formulad：
Wherein: t is1(1)、T1(2)…T1(n) generation time corresponding to the first n peaks, T2(1)、T2(2)…T2And (n) corresponds to the generation time of the last n peaks.
(8) When the oscillation period is accurately measured, the loop equivalent resistance is obtained according to the following equation:
wherein: v1(1)、V1(2)…V1(n) are each T1(1)、T1(2)…T1(n) corresponding to the voltage value, V2(1)、V2(2)…V2(n) are each T2(1)、T2(2)…T2(n) corresponds to the voltage value, TdTo calculate the resulting period of oscillation, LsumThe inductance is tested in series for the selected loop.
The expression formula of the preprocessed sampling voltage damped oscillation wave is as follows:
u1(t)＝Asin(ωdt+θ)e-bt
wherein:
obtaining the equivalent circuit series capacitance C according to the following formulasumI.e. the output capacitance C of the MOSFET power device under testoss：
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.
Claims (2)
1. The utility model provides a power MOSFET device on-resistance and output capacitance's testing arrangement based on attenuate oscillatory wave which characterized in that: the device comprises a tested power MOSFET device at the front end, a peripheral test circuit thereof and a sampling control system at the rear end; the peripheral test circuit comprises an adjustable direct current power supply, a fuse, an adjustable inductor and a voltage sampling resistor RU1A voltage dividing resistor RU2And a current sampling resistor RIWherein: the anode of the adjustable direct current power supply is connected with one end of a fuse, the other end of the fuse is connected with one end of an adjustable inductor, and the other end of the adjustable inductor is connected with the drain electrode of the tested power MOSFET device and a divider resistor RU2One end of which is connected with a voltage dividing resistor RU2And the other end of the voltage sampling resistor RU1Is connected with a sampling control system, a voltage sampling resistor RU1And the other end of the current sampling resistor R, the negative electrode of the adjustable direct current power supply and the current sampling resistor RIIs connected to ground and is connected to a current sampling resistor RIThe other end of the sampling control system is connected with the source electrode of the tested power MOSFET device and the sampling control system, and the grid electrode of the tested power MOSFET device is connected with a switch control signal provided by the sampling control system;
the sampling control system comprises an operational amplifier module, an AD module, a CPU module, a driving module and an upper computer; wherein:
the operational amplifier module is used for receiving the current RICurrent signal and RU1The two groups of signals are respectively conditioned and shaped;
the AD module is used for carrying out AD sampling on the conditioned and shaped current signal and voltage signal;
the CPU module comprises a CPLD and a static storage module, wherein the CPLD receives a test instruction output by the upper computer and then generates a corresponding pulse signal, the pulse signal is amplified by the power of the driving module to generate a corresponding switch control signal and output the signal to the grid of the power MOSFET device to be tested so as to control the switch state of the power MOSFET device to be tested, meanwhile, the CPLD also receives sampling signal data output by the AD module and stores the sampling signal data into the static storage module, and when needed, the CPLD calls the sampling signal data from the static storage module and transmits the sampling signal data to the upper computer;
the upper computer is used for receiving test parameters input by user settings so as to output corresponding test instructions to the CPU module, receiving sampling signal data provided by the CPU module so as to display voltage waveform between a drain electrode and a source electrode and current waveform flowing through a drain electrode and a source electrode in the avalanche tolerance test process of the tested power MOSFET device in real time, judging whether the tested power MOSFET device is subjected to avalanche breakdown or not, and calculating avalanche tolerance, on-resistance and output capacitance of the tested power MOSFET device according to the voltage and the current;
the operational amplifier module comprises a sampling voltage conditioning circuit and a sampling current conditioning circuit, wherein the sampling voltage conditioning circuit comprises two operational amplifiers U1-U2, seven resistors R1-R7 and three capacitors C1-C3; wherein, one end of the resistor R1 is connected with the voltage signal, the other end of the resistor R1 is connected with one end of the resistor R2 and the non-inverting input end of the operational amplifier U1, the other end of the resistor R2 is connected with one end of the resistor R3 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the other end of the resistor R3 is connected with +5V working voltage, the inverting input end and the output end of the operational amplifier U1 are connected with one end of the resistor R7, the other end of the resistor R7 is connected with one end of the resistor R5, one end of the capacitor C3 and the inverting input end of the operational amplifier U2, the other end of the resistor R5 is connected with the other end of the capacitor C24 and the output end of the operational amplifier U2 and outputs the conditioned voltage signal, the non-inverting input end of the operational amplifier U2 is connected with one end of the resistor R9, one end of the capacitor C2 and one end of the resistor R6, the other end of the resistor R6 is connected with the +5V working voltage;
the sampling current conditioning circuit comprises two operational amplifiers U3-U4, four resistors R8-R11 and a capacitor C4; the non-inverting input end of the operational amplifier U3 is connected with the current signal, the inverting input end of the operational amplifier U3 is connected with one end of a resistor R9, one end of a capacitor C4 and one end of a resistor R8, the other end of the resistor R8 is grounded, the other end of a resistor R9 is connected with the other end of a capacitor C4, the output end of the operational amplifier U3 and one end of a resistor R10, the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U4 and one end of the resistor R11, the other end of the resistor R11 is grounded, and the inverting input end and the output end of the operational amplifier U4 are connected in common and output the conditioned and;
the upper computer calculates the avalanche tolerance of the tested power MOSFET device according to the following relational expression;
wherein: e is the avalanche tolerance of the tested power MOSFET device, L is the inductance value of the adjustable inductor, and VCCFor regulating the output voltage of the DC power supply, IASFor the current flowing through the drain-source of the tested power MOSFET device at tpPeak value reached in time interval, BVdsThe breakdown voltage between the drain and the source after the tested power MOSFET device enters into avalanche state, tpCorresponding to a pulse width time period;
the upper computer calculates the on-resistance of the tested power MOSFET device according to the following relational expression;
wherein: rds(on)Is the on-resistance, V, of the power MOSFET device under testdsIs tpVoltage between drain and source of MOSFET device under test during time period, IdIs tpCurrent flowing through drain-source of the power MOSFET device under test during the time period, tpCorresponding to a pulse width time period;
the specific implementation process of the upper computer for calculating the output capacitance of the tested power MOSFET device is as follows:
(1) in the avalanche tolerance test process, the voltage waveform between the drain and the source of the tested power MOSFET device generates decaying oscillation after being turned off, so that N continuous sampling points X are intercepted from the decaying oscillation wave band of the voltage signal1～XNAs a sampling sequence, N is a natural number greater than 1;
(2) these N sampling points X are measured according to the following formula1～XNPreprocessing the voltage value;
V'(Xi)＝V(Xi)-VCC
wherein: v1(Xi) And V' (X)i) Respectively as sampling points X before and after pretreatmentiI is a natural number, i is more than or equal to 0 and less than or equal to N, VCCIs the output voltage of the adjustable direct current power supply;
(3) for these N sampling points X1～XNObtaining the wave crests of the voltage waveform in each oscillation period by a method of solving a maximum value after the voltage waveform is preprocessed, and obtaining 2n wave crests in total, wherein n is half of the number of the oscillation periods of the voltage waveform;
(4) dividing 2n wave crests into two groups, and calculating the oscillation period T by adopting a step-by-step difference methoddThe specific algorithm formula is as follows:
wherein: t is1(1)、T1(2)…T1(n) generation time corresponding to the first n peaks, T2(1)、T2(2)…T2(n) corresponding to the generation time of the last n peaks;
(5) finally, the output capacitance C of the MOSFET device of the power to be measured is calculated according to the following formulaoss；
Wherein: and L is the inductance value of the adjustable inductor.
2. The test device of claim 1, wherein: the test instruction output by the upper computer comprises test condition parameters and a test mode, wherein the test condition parameters comprise the output voltage of the adjustable direct-current power supply, the inductance value of the adjustable inductor and the pulse width, and the test mode is a single pulse avalanche tolerance test or a repeated pulse avalanche tolerance test.
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