CN109902036B

CN109902036B - EMIF interface-based double-rate 1553B bus equipment communication method

Info

Publication number: CN109902036B
Application number: CN201910085275.2A
Authority: CN
Inventors: 刘嘉祥; 徐元; 周晨君; 兰鹏涛; 张中元
Original assignee: Hubei Sanjiang Aerospace Hongfeng Control Co Ltd
Current assignee: Hubei Sanjiang Aerospace Hongfeng Control Co Ltd
Priority date: 2019-01-29
Filing date: 2019-01-29
Publication date: 2023-07-25
Anticipated expiration: 2039-01-29
Also published as: CN109902036A

Abstract

The invention discloses a communication method of a dual-speed 1553B bus device based on an EMIF interface, which comprises the following steps: the DSP processor sends a command packet and an interrupt signal to the FPGA through an EMIF bus; the FPGA executes commands corresponding to the command packets through 1553B bus controllers of 1Mbps and 4Mbps respectively according to the interrupt signals; the FPGA returns a response packet and an interrupt notification to the DSP processor. Through the technical scheme of the invention, 1553B bus equipment communication with 1Mbps and 4Mbps rates is realized, and the synchronism and the integrity of signals are ensured.

Description

EMIF interface-based double-rate 1553B bus equipment communication method

Technical Field

The invention relates to the technical field of computer bus communication, in particular to a double-rate 1553B bus equipment communication method based on an EMIF (External Memory Interface ) interface.

Background

If a DSP (Digital Signal Processing ) processor is used to connect a 1553B bus controller, a communication rate of 1Mbps and a communication rate of 4Mbps are needed to be used to communicate with different 1553B bus devices at the same time. If the 1553B bus controller is configured by adopting a switching rate on the DSP processor to realize simultaneous communication with 1553B bus equipment with 1Mbps and 4Mbps, signal asynchronization or data loss is caused.

Disclosure of Invention

Aiming at the problems, the invention provides a communication method of a double-rate 1553B bus device based on an EMIF (electronic memory interface), which utilizes a DSP (digital signal processor) to send command packets and interrupt signals to an FPGA (Field-Programmable GateArray, field programmable gate array), the FPGA is respectively connected with a 1553B bus controller with the speed of 1Mbps and 4Mbps, the command sent by the DSP is executed, the FPGA returns response packets to the DSP after executing the command, and the communication of the 1553B bus device with the speed of 1Mbps and 4Mbps is realized by the method, and the synchronism and the integrity of signals are ensured.

In order to achieve the above purpose, the present invention provides a dual-rate 1553B bus device communication method based on an EMIF interface, which includes: the DSP processor sends a command packet and an interrupt signal to the FPGA through an EMIF bus; the FPGA executes commands corresponding to the command packets through 1553B bus controllers of 1Mbps and 4Mbps respectively according to the interrupt signals; and the FPGA returns a response packet and an interrupt notification to the DSP processor.

In the above technical solution, preferably, the communication method of the dual-rate 1553B bus device based on the EMIF interface further includes: when receiving a command packet sent by the DSP, the FPGA caches the command packet by using a FIFO (First Input First Output, first-in first-out memory); and when the FPGA sends the response packet to the DSP, the response packet is cached by using the FIFO.

In the above technical solution, preferably, the FPGA is connected to a 1553B bus device through a 1553B bus controller with a rate of 1 Mbps; the FPGA is connected with another 1553B bus device through a 1553B bus controller with the speed of 4 Mbps.

In the above technical solution, preferably, the interrupt signal is used to notify the FPGA of the execution command, and the interrupt notification is used to notify the DSP processor that the execution of the command is completed.

In the above technical solution, preferably, the FIFO is disposed at the FPGA end, and the FIFO is used for buffering command packets and response packets.

In the above technical solution, preferably, the communication protocol format of the command packet includes a packet header, a data length, a command word, operation data, and a check bit.

In the above technical solution, preferably, the communication protocol format of the reply packet includes a packet header, a data length, a reply command word, reply data and a check bit.

In the above technical solution, preferably, the command word includes an operation instruction of the 1553B bus controller with a rate of 4Mbps and an operation instruction of the 1553B bus controller with a rate of 1 Mbps.

Compared with the prior art, the invention has the beneficial effects that: the DSP processor is utilized to send command packets and interrupt signals to the FPGA, the FPGA is respectively connected with 1553B bus controllers with the speed of 1Mbps and 4Mbps, the commands sent by the DSP processor are executed, the FPGA returns response packets to the DSP processor after executing the commands, the communication of 1553B bus devices with the speed of 1Mbps and 4Mbps is realized through the method, and the synchronism and the integrity of signals are ensured.

Drawings

Fig. 1 is a flow chart of a communication method of a dual-rate 1553B bus device based on an EMIF interface according to an embodiment of the invention;

fig. 2 is a system schematic diagram of a communication method of a dual-rate 1553B bus device based on an EMIF interface according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1 and fig. 2, the communication method of the dual-rate 1553B bus device based on the EMIF interface according to the present invention includes: the DSP processor sends a command packet and an interrupt signal to the FPGA through an EMIF bus; the FPGA executes commands corresponding to the command packets through 1553B bus controllers of 1Mbps and 4Mbps respectively according to the interrupt signals; the FPGA returns a response packet and an interrupt notification to the DSP processor.

In this embodiment, the DSP processor is connected to the FPGA through an EMIF bus and an interrupt signal, and the EMIF bus between the DSP processor and the FPGA uses data packet communication, and is divided into a command packet and a response packet. The DSP processor is an active party, sends a command packet to the FPGA, sends an interrupt signal to inform the FPGA of executing the command, the FPGA is a passive party, the FPGA is respectively connected with 1553B bus controllers with the speed of 1Mbps and 4Mbps, and after the FPGA operates the 1553B bus controllers to execute the corresponding command, the FPGA returns a response packet to the DSP processor and sends an interrupt notification to the DSP processor to determine that the command is executed.

In the above embodiment, preferably, the dual-rate 1553B bus device communication method based on the EMIF interface further includes: when receiving a command packet sent by a DSP, the FPGA caches the command packet by using a FIFO; when the FPGA sends the response packet to the DSP, the response packet is buffered by the FIFO.

In the above embodiment, preferably, the FPGA is connected to a 1553B bus device through a 1553B bus controller with a rate of 1 Mbps; the FPGA is connected with another 1553B bus device through a 1553B bus controller with the speed of 4 Mbps.

In the above embodiment, preferably, the interrupt signal is used to notify the FPGA of the execution command, and the interrupt notification is used to notify the DSP processor that the execution of the command is completed.

In the above embodiment, preferably, the FIFO is provided at the FPGA end, and the FIFO is used to buffer the command packet and the response packet.

In the above embodiment, preferably, the communication protocol format of the command packet includes a packet header, a data length, a command word, operation data, and a check bit. The specific command packet communication protocol format is shown in table 1:

table 1 command packet communication protocol format

In the above embodiment, preferably, the communication protocol format of the reply packet includes a packet header, a data length, a reply command word, reply data, and a check bit. The specific acknowledgement packet communication protocol format is shown in table 2:

table 2 reply packet communication protocol format

Name of the name	Content	Length (byte)
			Packet head	0xAA55	2
Data length	The packet data length (except the header)	2
			Response command word	Returning command words in a command packet	2
Data	Response data	N
			Verification of	CRC check	2

In the above embodiment, it is preferable that the command word includes an operation instruction of the 1553B bus controller with a rate of 4Mbps and an operation instruction of the 1553B bus controller with a rate of 1 Mbps. Wherein, the 1553B operation instruction with the rate of 4Mbps is shown in table 3, and the 1553B operation instruction with the rate of 1Mbps is shown in table 4:

table 3 Rate 4Mbps1553B Instructions

4Mbps1553B operation instruction	Instruction code	Description of the invention
			CMD_EMIF_1553B_INIT_BC0	0x1010	Initializing BC patterns
CMD_EMIF_1553B_BC2RT_0	0x1011	BCtoRT
			CMD_EMIF_1553B_RT2BC_0	0x1012	RTtoBC
CMD_EMIF_1553B_INIT_RT0	0x1013	Initializing RT mode
			CMD_EMIF_1553B_PUT_RT_0	0x1014	Setting RT data
CMD_EMIF_1553B_GET_RT_0	0x1015	Acquisition of RT data
			CMD_EMIF_1553B_RTSET_VW_0	0x1016	Setting RT vector words
CMD_EMIF_1553B_RTGET_VW_0	0x1017	Acquiring RT vector words

Table 4 Rate 1Mbps1553B operating Instructions

1Mbps1553B operation instruction	Instruction code	Description of the invention
			CMD_EMIF_1553B_INIT_BC1	0x1110	Initializing BC patterns
CMD_EMIF_1553B_BC2RT_1	0x1111	BCtoRT
			CMD_EMIF_1553B_RT2BC_1	0x1112	RTtoBC
CMD_EMIF_1553B_INIT_RT1	0x1113	Initializing RT mode
			CMD_EMIF_1553B_PUT_RT_1	0x1114	Setting RT data
CMD_EMIF_1553B_GET_RT_1	0x1115	Acquisition of RT data
			CMD_EMIF_1553B_RTSET_VW_1	0x1116	Setting RT vector words
CMD_EMIF_1553B_RTGET_VW_1	0x1117	Acquiring RT vector words

According to the communication method of the dual-speed 1553B bus equipment based on the EMIF interface, which is provided by the invention, the DSP processor is utilized to send command packets and interrupt signals to the FPGA, the FPGA is respectively connected with the 1553B bus controllers with the rates of 1Mbps and 4Mbps, the commands sent by the DSP processor are executed, the FPGA returns response packets to the DSP processor after executing the commands, and the communication of the 1553B bus equipment with the rates of 1Mbps and 4Mbps is realized by the method. Furthermore, in the method, the FIFO in the FPGA is adopted to buffer the command packet and the response packet, so that the synchronism and the integrity of communication data are ensured.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The communication method of the dual-rate 1553B bus equipment based on the EMIF interface is characterized by comprising the following steps of:

the DSP processor sends a command packet and an interrupt signal to the FPGA through an EMIF bus;

the FPGA executes commands corresponding to the command packets through 1553B bus controllers of 1Mbps and 4Mbps respectively according to the interrupt signals;

the FPGA returns a response packet and an interrupt notification to the DSP processor;

the EMIF bus between the DSP processor and the FPGA adopts the form of data packet for communication, and is divided into command packets and response packets; the DSP processor is an active party, sends a command packet to the FPGA, sends an interrupt signal to inform the FPGA of executing the command, the FPGA is a passive party, the FPGA is respectively connected with 1553B bus controllers with the speed of 1Mbps and 4Mbps, and after executing the corresponding command, the FPGA operates the 1553B bus controllers to return a response packet to the DSP processor, and sends an interrupt notification to the DSP processor to determine that the command is executed;

when receiving a command packet sent by the DSP, the FPGA caches the command packet by using a FIFO;

and when the FPGA sends the response packet to the DSP, the response packet is cached by using the FIFO.

2. The EMIF interface-based dual-rate 1553B bus device communication method of claim 1, wherein the interrupt signal is used to notify the FPGA to execute a command and the interrupt notification is used to notify the DSP processor that the command is executed.

3. The EMIF interface-based dual-rate 1553B bus device communication method of claim 1, wherein the FIFO is disposed at the FPGA side, and the FIFO is used for buffering command packets and response packets.

4. The EMIF interface-based dual rate 1553B bus device communication method of claim 1, wherein the communication protocol format of the command packet comprises a packet header, a data length, a command word, operation data, and a check bit.

5. The EMIF interface-based dual rate 1553B bus device communication method of claim 1, wherein the communication protocol format of the reply packet comprises a packet header, a data length, a reply command word, reply data and a check bit.

6. The EMIF interface-based dual-rate 1553B bus device communication method of claim 4, wherein the command word comprises an operation command of a 1553B bus controller with a rate of 4Mbps and an operation command of a 1553B bus controller with a rate of 1 Mbps.