CN109902036A

CN109902036A - Dual rate 1553B bus apparatus communication means based on EMIF interface

Info

Publication number: CN109902036A
Application number: CN201910085275.2A
Authority: CN
Inventors: 刘嘉祥; 徐元; 周晨君; 兰鹏涛; 张中元
Original assignee: Hubei Sanjiang Aerospace Hongfeng Control Co Ltd
Current assignee: Hubei Sanjiang Aerospace Hongfeng Control Co Ltd
Priority date: 2019-01-29
Filing date: 2019-01-29
Publication date: 2019-06-18
Anticipated expiration: 2039-01-29
Also published as: CN109902036B

Abstract

The invention discloses a kind of dual rate 1553B bus apparatus communication means based on EMIF interface, comprising: dsp processor sends order packet and interrupt signal to FPGA by EMIF bus；The 1553B bus control unit that FPGA passes through 1Mbps and 4Mbps according to interrupt signal respectively executes order and wraps corresponding order；FPGA returns to response bag and interrupt notification to dsp processor.According to the technical solution of the present invention, it realizes while the 1553B bus apparatus of 1Mbps and 4Mbps rate is communicated, and ensure that the synchronism and integrality of signal.

Description

Dual rate 1553B bus apparatus communication means based on EMIF interface

Technical field

The present invention relates to computer bus fields of communication technology, more particularly to one kind to be based on EMIF (External Memory Interface, external memory interface) interface dual rate 1553B bus apparatus communication means.

Background technique

A certain 1553B bus communication device, if using a DSP (Digital Signal Processing, number Signal processing) processor one 1553B bus control unit of connection, it needs to distinguish using the traffic rate of 1Mbps and 4Mbps simultaneously It is communicated from different 1553B bus apparatus.If using switching rate to 1553B bus control unit on dsp processor The mode of configuration certainly will will cause the asynchronous of signal to realize while communicate with the 1553B bus apparatus of 1Mbps and 4Mbps Or the loss of data.

Summary of the invention

In view of the above-mentioned problems, the present invention provides a kind of dual rate 1553B bus apparatus communication party based on EMIF interface Method is sent out using dsp processor to FPGA (Field-Programmable GateArray, field programmable gate array) Order of losing one's life is wrapped and interrupt signal, and FPGA is connect with the 1553B bus control unit that rate is 1Mbps and 4Mbps respectively, executes DSP Order transmitted by processor returns to response bag to dsp processor after FPGA execution order, and it is right simultaneously to be realized by the above method The 1553B bus apparatus of 1Mbps and 4Mbps rate communicates, and guarantees the synchronism and integrality of signal.

To achieve the above object, the dual rate 1553B bus apparatus communication based on EMIF interface that the present invention provides a kind of Method, comprising: dsp processor sends order packet and interrupt signal to FPGA by EMIF bus；The FPGA is according in described The 1553B bus control unit that break signal passes through 1Mbps and 4Mbps respectively executes the order and wraps corresponding order；The FPGA Response bag and interrupt notification are returned to the dsp processor.

In the above-mentioned technical solutions, it is preferable that the dual rate 1553B bus apparatus communication means based on EMIF interface also wraps Include: the FPGA when receiving the order packet that the DSP is sent, using FIFO (First Input First Output, it is advanced First go out memory) the caching order packet；The FPGA caches institute when sending response bag to the DSP, using the FIFO State response bag.

In the above-mentioned technical solutions, it is preferable that the FPGA through-rate is the 1553B bus control unit and one of 1Mbps 1553B bus apparatus is connected；The FPGA through-rate is that the 1553B bus control unit of 4Mbps is set with another 1553B bus It is standby to be connected.

In the above-mentioned technical solutions, it is preferable that the interrupt signal is for notifying the FPGA to execute order, the interruption Notice is for notifying the dsp processor order to be finished.

In the above-mentioned technical solutions, it is preferable that the FIFO is set to the end FPGA, and the FIFO is used for cache command Packet and response bag.

In the above-mentioned technical solutions, it is preferable that the communications protocol format of the order packet includes packet header, data length, life Enable word, operation data and check bit.

In the above-mentioned technical solutions, it is preferable that the communications protocol format of the response bag includes packet header, data length, answers Answer command word, reply data and check bit.

In the above-mentioned technical solutions, it is preferable that the command word includes the 1553B bus control unit that rate is 4Mbps The operational order for the 1553B bus control unit that operational order and rate are 1Mbps.

Compared with prior art, the invention has the benefit that sending order packet to FPGA using dsp processor and interrupting Signal, FPGA connect with the 1553B bus control unit that rate is 1Mbps and 4Mbps respectively, execute transmitted by dsp processor Order returns to response bag to dsp processor after FPGA execution order, is realized by the above method fast to 1Mbps and 4Mbps simultaneously The 1553B bus apparatus of rate communicates, and guarantees the synchronism and integrality of signal.

Detailed description of the invention

Fig. 1 is the dual rate 1553B bus apparatus communication means based on EMIF interface disclosed in an embodiment of the present invention Flow diagram；

Fig. 2 is the dual rate 1553B bus apparatus communication means based on EMIF interface disclosed in an embodiment of the present invention System schematic.

Specific embodiment

In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.

The present invention is described in further detail with reference to the accompanying drawing:

As depicted in figs. 1 and 2, a kind of dual rate 1553B bus apparatus based on EMIF interface provided according to the present invention Communication means, comprising: dsp processor sends order packet and interrupt signal to FPGA by EMIF bus；FPGA believes according to interruption Order is executed by the 1553B bus control unit of 1Mbps and 4Mbps number respectively and wraps corresponding order；FPGA is returned to dsp processor Return response bag and interrupt notification.

In this embodiment, dsp processor is connected with FPGA by EMIF bus and interrupt signal, dsp processor with EMIF bus between FPGA is communicated in the form of data packet, is divided into order packet and response bag.Wherein, based on dsp processor Dynamic side sends order packet to FPGA, and sends interrupt signal notice FPGA and execute order, and FPGA is passive side, FPGA respectively with Rate is that 1Mbps is connected with the 1553B bus control unit of 4Mbps, and FPGA operates 1553B bus control unit and executes corresponding order Backward dsp processor returns to response bag, and sends interrupt notification to dsp processor and determine that order is finished.

In the above embodiment, it is preferable that the dual rate 1553B bus apparatus communication means based on EMIF interface also wraps Include: FPGA utilizes FIFO cache command packet when receiving the order packet of DSP transmission；FPGA is when sending response bag to DSP, benefit Response bag is cached with FIFO.

In the above embodiment, it is preferable that the 1553B bus control unit and a 1553B that FPGA through-rate is 1Mbps are total Line equipment is connected；FPGA through-rate is that the 1553B bus control unit of 4Mbps is connected with another 1553B bus apparatus.

In the above embodiment, it is preferable that interrupt signal is for notifying FPGA to execute order, interrupt notification is for notifying Dsp processor order is finished.

In the above embodiment, it is preferable that FIFO is set to the end FPGA, FIFO is used for cache command packet and response bag.

In the above embodiment, it is preferable that the communications protocol format of order packet includes packet header, data length, command word, behaviour Make data and check bit.Specific order communication protocol packet format is as shown in table 1:

1 order communication protocol packet format of table

In the above embodiment, it is preferable that the communications protocol format of response bag includes packet header, data length, acknowledgement command Word, reply data and check bit.Specific response bag communications protocol format is as shown in table 2:

2 response bag communications protocol format of table

Title	Content	Length (byte)
			Packet header	0xAA55	2
Data length	This bag data length (removing packet header)	2
			Acknowledgement command word	Command word in return command packet	2
Data	Reply data	N
			Verification	CRC check	2

In the above embodiment, it is preferable that the operation that command word includes the 1553B bus control unit that rate is 4Mbps refers to Enable the operational order with the 1553B bus control unit that rate is 1Mbps.Wherein, rate be 4Mbps 1553B operational order such as Shown in table 3, rate is that the 1553B operational order of 1Mbps is as shown in table 4:

3 rate of table is the 1553B operational order of 4Mbps

4Mbps1553B operational order	Instruction code	Explanation
			CMD_EMIF_1553B_INIT_BC0	0x1010	Initialize BC mode
CMD_EMIF_1553B_BC2RT_0	0x1011	BCtoRT
			CMD_EMIF_1553B_RT2BC_0	0x1012	RTtoBC
CMD_EMIF_1553B_INIT_RT0	0x1013	Initialize RT mode
			CMD_EMIF_1553B_PUT_RT_0	0x1014	RT data are set
CMD_EMIF_1553B_GET_RT_0	0x1015	Obtain RT data
			CMD_EMIF_1553B_RTSET_VW_0	0x1016	RT vector font is set
CMD_EMIF_1553B_RTGET_VW_0	0x1017	Obtain RT vector font

4 rate of table is the 1553B operational order of 1Mbps

1Mbps1553B operational order	Instruction code	Explanation
			CMD_EMIF_1553B_INIT_BC1	0x1110	Initialize BC mode
CMD_EMIF_1553B_BC2RT_1	0x1111	BCtoRT
			CMD_EMIF_1553B_RT2BC_1	0x1112	RTtoBC
CMD_EMIF_1553B_INIT_RT1	0x1113	Initialize RT mode
			CMD_EMIF_1553B_PUT_RT_1	0x1114	RT data are set
CMD_EMIF_1553B_GET_RT_1	0x1115	Obtain RT data
			CMD_EMIF_1553B_RTSET_VW_1	0x1116	RT vector font is set
CMD_EMIF_1553B_RTGET_VW_1	0x1117	Obtain RT vector font

The above is embodiments of the present invention, the dual rate 1553B based on EMIF interface proposed according to the present invention Bus apparatus communication means sends order packet to FPGA using dsp processor and interrupt signal, FPGA is with rate respectively 1Mbps is connected with the 1553B bus control unit of 4Mbps, executes order transmitted by dsp processor, it is backward that FPGA executes order Dsp processor returns to response bag, is realized by the above method logical to the 1553B bus apparatus of 1Mbps and 4Mbps rate simultaneously Letter.Further, in the method using the FIFO in FPGA come cache command packet and response bag, it ensure that the same of communication data Step property and integrality.

These are only the preferred embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art For member, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is made it is any modification, Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.

Claims

1. a kind of dual rate 1553B bus apparatus communication means based on EMIF interface characterized by comprising

Dsp processor sends order packet and interrupt signal to FPGA by EMIF bus；

The FPGA executes the order according to the 1553B bus control unit that the interrupt signal passes through 1Mbps and 4Mbps respectively Wrap corresponding order；

The FPGA returns to response bag and interrupt notification to the dsp processor.

2. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In, further includes:

The FPGA caches the order using FIFO and wraps when receiving the order packet that the DSP is sent；

The FPGA caches the response bag when sending response bag to the DSP, using the FIFO.

3. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In,

The FPGA through-rate is that the 1553B bus control unit of 1Mbps is connected with a 1553B bus apparatus；

The FPGA through-rate is that the 1553B bus control unit of 4Mbps is connected with another 1553B bus apparatus.

4. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In the interrupt signal is for notifying the FPGA to execute order, and the interrupt notification is for notifying the dsp processor order It is finished.

5. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In the FIFO is set to the end FPGA, and the FIFO is used for cache command packet and response bag.

6. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In the communications protocol format of the order packet includes packet header, data length, command word, operation data and check bit.

7. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In the communications protocol format of the response bag includes packet header, data length, acknowledgement command word, reply data and check bit.

8. the dual rate 1553B bus apparatus communication means according to claim 1 based on EMIF interface, feature exist In, the command word include the operational order for the 1553B bus control unit that rate is 4Mbps and 1553B that rate is 1Mbps total The operational order of lane controller.