CN111078605A

CN111078605A - Comprehensive processing system for multi-communication interface interruption

Info

Publication number: CN111078605A
Application number: CN201911258198.2A
Authority: CN
Inventors: 林益锋; 何浩; 杨健; 张晓澈; 阮忠园; 蒋凯
Original assignee: Shanghai Aerospace Control Technology Institute
Current assignee: Shanghai Aerospace Control Technology Institute
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-04-28

Abstract

The invention relates to a comprehensive processing system for multi-communication interface interrupt, which is based on a DSP and an FPGA digital processing system, wherein a main processor DSP comprises 4 hardware interrupt functions; the main processor interacts data with the FPGA through the EMIF; the FPGA controls 11 serial communication interfaces and 1 1553B bus interface, so that the on-line connection of the receiving interrupt of a plurality of communication interfaces and the hardware interrupt of the DSP can be realized, and the interrupt processing priority can be changed as required. Meanwhile, a plurality of interrupt sources can share one hardware interrupt, and the function of receiving a plurality of interrupts triggered simultaneously or sequentially is realized by storing the base address of the interrupt source, so that the interrupt information loss caused by the contention interrupt is avoided.

Description

Comprehensive processing system for multi-communication interface interruption

Technical Field

The invention relates to the field of data processing, in particular to a comprehensive processing system for multi-communication interface interrupt, which mainly relates to data interaction between a DSP (digital signal processor) and an FPGA (field programmable gate array) and interrupt processing of a communication interface.

Background

With the increasing abundance of on-board equipment, the number of communication interfaces of on-board computers is also increasing, and the importance of each communication interface data is also different in different stages of flight, so that the interruption priority which is fixed unchanged in the past is increasingly unable to meet the requirements. Meanwhile, due to the fact that time sequences of different devices are asynchronous, the pop-up computer can also encounter the situation that a communication interface contends for interruption, and the situation can cause the problems that interruption information is lost, data updating is delayed and the like.

The invention designs a processing device which can flexibly change the processing priority of the communication interface according to the conditions and conditions, avoid information loss by storing the interrupt information and optimize the processing of receiving interrupt by multiple communication interfaces.

Disclosure of Invention

The invention aims to realize the comprehensive processing of the interruption of a plurality of communication interfaces through the FPGA software design, meet the requirements of modifying the processing priority of the communication interfaces according to the conditions and avoid information loss caused by contention interruption.

The invention adopts the following technical scheme: a comprehensive processing system for multi-communication interface interrupt is prepared as setting DSP and FPGA on data processing system, setting multiple communication interfaces on peripheral, connecting on-line receiving interrupt of communication interface to hardware interrupt of DSP, receiving multiple interrupts triggered at same time or in sequence by same hardware interrupt.

The processing technology is characterized in that a main processor DSP comprises 4 hardware interrupt functions; the main processor interacts data with the FPGA through the EMIF; the FPGA controls 11 serial communication interfaces and 1 1553B bus interface.

In the processing technology, an interrupt processing module receives interrupt input of peripheral equipment and sends out hardware interrupt output; the 4 x 12 matrix is adopted to realize the connection of input and output, the row represents the hardware output, the column represents the receiving interrupt source, the elements of the connection matrix are 1 table connection and 0 table disconnection, the same row can have a plurality of connections, and the same column does not allow a plurality of connections; the connection matrix element values may be set by the DSP.

In the processing technology, after the peripheral interrupt is triggered, the interrupt processing module presses the base address of the peripheral into FIFO; a plurality of interrupts triggered simultaneously are pressed into the FIFO from small to large according to the size of the base address; a plurality of interrupts triggered successively are pressed into the FIFO in a time sequence; FIFO depth is 16; after receiving the hardware interrupt, the DSP firstly accesses the interrupt processing module to obtain the base address of the peripheral, and then accesses the peripheral according to the base address and carries out corresponding processing.

The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and any simple changes or equivalent substitutions of the technical solutions that can be made obvious by those skilled in the art within the technical scope of the present invention are within the scope of the present invention.

Compared with the prior art, the invention has the following advantages:

(1) the FPGA software is adopted to realize the function, and the interrupt connection can be modified on line.

(2) The base address of the peripheral is stored, and the loss of the interrupt information is prevented.

Drawings

The invention will be further explained with reference to the drawings and examples.

FIG. 1 is a block diagram of an integrated processing system for multiple communication interface interrupts in accordance with the present invention;

FIG. 2 is a block diagram of an interrupt handling module according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention are described below with reference to the accompanying drawings:

referring to FIG. 1, a data processing system comprises a DSP and an FPGA, and a main processor DSP comprises 4 hardware interrupts; DSP interacts data, address bus ADDR [2 ], with FPGA through EMIF. 21], DATA bus DATA [0..15], control signals CE, WR, RD; 11 serial communication interface protocols UART 1-UART 11 and 1 1553B bus communication protocol are arranged outside; the receiving interrupt of each communication interface is input into an interrupt processing module, and the module outputs the interrupt to 4 hardware interrupt pins of the DSP.

Referring to FIG. 2, the interrupt handling module contains two major parts, namely the connection matrix and the base address storage. The method comprises the following steps that connection between interrupt sources 1-12 and output is realized according to a 4 x 12 matrix, a row represents hardware output, a column represents a receiving interrupt source, elements of the connection matrix are 1 table connection and 0 table disconnection, a plurality of connections can be arranged in the same row, and a plurality of connections are not allowed in the same column; the connection matrix element values may be set by the DSP. When the interrupt sources of different lines trigger the interrupt at the same time, the DSP processes the interrupt sources in sequence according to the hardware interrupt priority; when the interrupt sources in the same line trigger the interrupt at the same time, the base address storage is pressed into the FIFO from small to large according to the size of the base address; when the interrupt sources in the same line trigger interrupts in sequence, the base address storage is pressed into FIFO according to the time sequence, and the first interrupt is directly processed; the FIFO depth of base address storage is 16; after receiving the hardware interrupt, the DSP firstly accesses the interrupt processing module to obtain the base address of the peripheral, and then accesses the peripheral according to the base address and carries out corresponding processing.

Claims

1. An integrated processing system for multiple communication interface interrupts, wherein: the data processing system comprises a main processor DSP and an FPGA, the peripheral comprises a plurality of communication interfaces, the receiving interrupt of the communication interfaces and the hardware interrupt of the DSP can be connected in an on-line mode, and the same hardware interrupt can receive a plurality of interrupts triggered simultaneously or sequentially.

2. The integrated processing system for multiple communication interface interrupts of claim 1, wherein the host processor DSP comprises 4 hardware interrupt functions; the main processor interacts data with the FPGA through the EMIF; the FPGA controls 11 serial communication interfaces and 1 1553B bus interface.

3. The integrated processing system for multi-communication interface interrupts of claim 1, wherein the interrupt processing module receives the interrupt input of the peripheral device and issues the hardware interrupt output; the 4 x 12 matrix is adopted to realize the connection of input and output, the row represents the hardware output, the column represents the receiving interrupt source, the elements of the connection matrix are 1 table connection and 0 table disconnection, the same row can have a plurality of connections, and the same column does not allow a plurality of connections; the connection matrix element values may be set by the DSP.

4. The integrated processing system for multi-communication interface interrupts of claim 1, wherein after the peripheral interrupt is triggered, the interrupt processing module pushes the base address of the peripheral into the FIFO; a plurality of interrupts triggered simultaneously are pressed into the FIFO from small to large according to the size of the base address; a plurality of interrupts triggered successively are pressed into the FIFO in a time sequence; FIFO depth is 16; after receiving the hardware interrupt, the DSP firstly accesses the interrupt processing module to obtain the base address of the peripheral, and then accesses the peripheral according to the base address and carries out corresponding processing.