CN109841671B - 源极/漏极接触件的形成方法及半导体器件的形成方法 - Google Patents

源极/漏极接触件的形成方法及半导体器件的形成方法 Download PDF

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CN109841671B
CN109841671B CN201811007588.8A CN201811007588A CN109841671B CN 109841671 B CN109841671 B CN 109841671B CN 201811007588 A CN201811007588 A CN 201811007588A CN 109841671 B CN109841671 B CN 109841671B
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source
annealing process
drain
forming
semiconductor device
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CN109841671A (zh
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B.摩尔 沙哈吉
蔡俊雄
张世杰
游国丰
彭成毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括提供结构，其中，该结构含有衬底、衬底上方的栅极结构、以及与栅极结构相邻的含有硅锗(SiGe)的源极/漏极(S/D)部件。该方法还包括将镓(Ga)注入到S/D中；在第一温度的条件下实施第一退火工艺以再结晶SiGe；在第一退火工艺之后，在S/D上方沉积包括金属的导电材料；在第二温度的条件下实施第二退火工艺，以引起金属和S/D之间的反应；以及在第三温度条件下实施第三退火工艺，以激活S/D中含有Ga的掺杂剂。本发明的实施例还提供了半导体器件的形成方法。

Description

源极/漏极接触件的形成方法及半导体器件的形成方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及源极/漏极接触件的形成方法及半导体器件的形成方法。
背景技术
半导体集成电路(IC)工业经历了指数增长。IC材料和设计方面的技术进步产生了几代IC，其中每代都具有比上一代更小和更复杂的电路。在 IC演进的过程中，功能密度(即，每芯片面积的互连器件的数量)通常已经增加，而几何尺寸(即，可以使用制造工艺创建的最小组件(或线)) 已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也增加了IC的加工和制造的复杂性，并且为了实现这些改进，需要IC加工和制造中的类似发展。
例如，当按比例缩小继续超过32nm或更小时，源极/漏极(S/D)接触电阻在整个晶体管电阻中变得越来越占优势。非常需要用于降低S/D接触电阻的方法和结构。
发明内容
根据本发明的一方面，提供了一种形成半导体器件的方法，包括：提供结构，所述结构包括：衬底；栅极结构，位于所述衬底上方；和源极/漏极(S/D)部件，与所述栅极结构相邻并包括硅锗(SiGe)；将镓(Ga)注入到所述源极/漏极中；在第一温度的条件下实施第一退火工艺以再结晶所述硅锗；在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的导电材料；在第二温度的条件下实施第二退火工艺以引起所述金属和所述源极/漏极之间的反应；以及在第三温度的条件下实施第三退火工艺以激活所述源极/漏极中包括镓的掺杂剂。
根据本发明的另一方面，提供了一种形成半导体器件的方法，包括：提供结构，所述结构包括：衬底；栅极结构，位于所述衬底上方；源极/漏极(S/D)部件，与所述栅极结构相邻并包括硅锗(SiGe)；和一个或多个介电层，位于所述栅极结构的侧壁上方和所述源极/漏极上方；蚀刻所述一个或多个介电层以形成暴露所述源极/漏极的开口；通过所述开口将镓(Ga) 离子注入到所述源极/漏极中；在所述硅锗的再结晶温度的条件下实施第一退火工艺；在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的材料；实施第二退火工艺以在所述源极/漏极上方形成具有Si和所述金属的化合物；实施第三退火工艺以激活所述源极/漏极中包括镓的掺杂剂；以及在所述化合物上方形成源极/漏极接触塞。
根据本发明的又一方面，提供了一种形成半导体器件的方法，包括：提供结构，所述结构包括：衬底；高k金属栅极结构，位于所述衬底上方；和源极/漏极(S/D)部件，与所述高k金属栅极结构相邻并且包括硅锗 (SiGe)；将镓(Ga)离子和硼(B)离子注入到所述源极/漏极中；在所述硅锗的再结晶温度的条件下实施第一退火工艺；在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的导电材料；实施第二退火工艺以在所述源极/漏极上方形成具有Si和所述金属的一种或多种化合物；实施第三退火工艺以激活所述源极/漏极中的包括镓和硼的掺杂剂；以及在所述一种或多种化合物上方形成源极/漏极接触塞。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A示出了根据本发明的实施例的形成半导体器件的方法的流程图。
图1B示出了根据本发明的实施例的图1A中的方法的制造阶段中的半导体器件的部分的立体图。
图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A 和图11A是根据本发明的实施例的图1A中的方法在各个制造阶段期间半导体器件的部分的截面图(沿着鳍长度方向)。
图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B 和图11B是根据本发明的实施例的图1A中的方法在各个制造阶段期间半导体器件的部分的截面图(沿着鳍宽度方向)。
具体实施方式
以下公开内容提供了用于实现所提供主题的不同部件的许多不同实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括以直接接触的方式形成第一部件和第二部件的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，在本文中可以使用诸如“在...之下”、“在... 下面”、“下部”、“在...之上”、“上部”等的空间相对术语来描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的取向之外，空间相对术语旨在包含在使用或操作中的器件的不同取向。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在本文中使用的空间相对描述符同样可以作出相应地解释。此外，当用“大约”、“近似”等描述数字或数字范围时，该术语旨在涵盖在包含所描述的数字的合理范围内的数字，例如在所描述数字的+/-10％内或本领域技术人员所理解的其它值。例如，术语“约5nm”涵盖从4.5nm至5.5nm的尺寸范围。
本发明通常涉及半导体器件及其形成方法。更具体地，本发明涉及形成用于p型晶体管(特别是用于p型FinFET)的源极/漏极(S/D)接触件。本发明的一个目的是通过以下步骤来降低S/D接触电阻：将镓(Ga)注入到具有硅锗(SiGe)的S/D中；随后进行适当退火工艺，其中，该适当退火工艺包括在SiGe再结晶(或修复)温度下进行退火。本发明的实施例选择S/D中的Si和Ge之间的特定比率来提高Ga原子在S/D中的溶解度，并且选择特定退火温度和持续时间以允许：(a)SiGe合金在Ga离子注入之后修复，以及(b)Ga离子或原子在S/D的顶部处分离。(a)和(b) 都有助于降低S/D接触电阻。例如，在S/D的顶部处分离的Ga离子或原子减少了具有金属、硅和硼的稳定化合物的形成，从而降低了S/D接触塞与注入Ga的SiGe S/D之间的电阻。例如，再结晶提高了SiGe合金的导电性。将参考图1A至图11B进一步讨论本发明的这些和其他方面。
图1A示出了根据本发明的各个方面的形成半导体器件100的方法10 的流程图。图1B中示出了处于制造阶段的半导体器件100的立体图。方法 10仅仅是实例，并不旨在限制本发明的范围，其中，本发明可以超出在权利要求中明确记载的范围之外。可以在方法10之前、期间和之后提供附加的操作，并且对于该方法的附加实施例，所描述的一些操作可以被替换、去除或重新定位。在下面结合图2A至图10B描述方法10，其中，图2A 至图10B是在制造工艺的各个阶段中的半导体器件100的截面图。具体地，图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A是沿着图1B的鳍长度方向“A-A”的器件100的部分的截面图；并且图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B和图11B是沿着图1B的鳍宽度方向“B-B”的器件100的部分的截面图。提供半导体器件100是为了说明的目的，并不一定将本发明的实施例限制于任何数量的器件、任何数量的区域或者任何结构或区域的配置。此外，如图2A至图11B所示的半导体器件100可以是在处理IC或部分IC期间所制造的中间器件，其中，IC可以包括静态随机存取存储器(SRAM)；和/ 或逻辑电路、无源组件(例如电阻器、电容器和电感器)以及有源组件(例如p型场效应晶体管(PFET)、n型FET(NFET)、例如FinFET的多栅极FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极型晶体管、高电压晶体管、高频晶体管、其他存储单元及它们的组合)。
在操作12处，方法10(图1A)提供了如图2A和图2B所示的器件 100的结构，其中图1B示出了器件100的一些组件的立体图。共同参考图 1B、图2A和图2B，器件100包括衬底102以及在其中或其上形成的各种部件。器件100还包括由隔离结构105分离的一个或多个半导体鳍103(所示的一个)。具体地，图2A示出了沿着鳍103的长度(“x”方向)的器件100的截面图，并且图2B示出了在器件100的S/D区域中沿着鳍103 的宽度(“y”方向)的器件100的截面图。器件100还包括邻近鳍103的沟道区的栅极堆叠件(或栅极结构)106以及位于鳍103上方并且位于栅极堆叠件106两侧上的S/D 104。器件100还包括位于栅极堆叠件106的侧壁上的栅极间隔件108、位于鳍103的侧壁上的鳍侧壁间隔件107、位于栅极间隔件108和S/D 104上方的接触蚀刻停止层(CESL)110、以及位于 CESL 110上方并且填充在相邻栅极间隔件108之间的间隙中的介电层112。在下面进一步描述器件100的各种部件(或组件)。
在本实施例中，衬底102是硅(Si)衬底。在可选实施例中，衬底102 包括其他元素半导体，例如锗(Ge)；化合物半导体，例如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和磷化铟(InP)；或合金半导体，例如硅锗碳化物(SiGeC)、磷砷化镓(GaAsP)和磷化镓铟(GaInP)。在实施例中，衬底102可以包括绝缘体上硅(SOI)衬底，衬底102可以产生应变和/或应力以用于提高性能，衬底102包括外延区域、掺杂区域和/或包括其他合适的部件和层。
鳍103可以包括一层或多层半导体材料，例如硅或硅锗。在一个实施例中，鳍103包括一个交替地堆叠在另一个上方的多层半导体材料，例如，具有交替堆叠的多个硅层和多个硅锗层。可以通过任何合适的方法图案化鳍103。例如，可以使用一种或多种光刻工艺(包括双重图案化或多重图案化工艺)来图案化鳍103。通常，双重图案化或多重图案化工艺结合了光刻和自对准工艺，从而允许创建的图案的间距诸如比使用单一直接光刻工艺以其他方式可获得的间距小。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺进行图案化。使用自对准工艺沿着图案化的牺牲层的侧面形成间隔件。然后去除牺牲层，并且然后可以将剩余的间隔件或芯轴(mandrel)用作图案化鳍103的掩模元件。例如，掩模元件可以用于衬底102上方或之中的半导体层中蚀刻凹槽，将鳍103留在衬底102上。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的工艺。例如，干蚀刻工艺可以实施含氧气体、含氟气体(例如CF4、SF6、 CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4、和/或BCl3)、含溴气体(例如HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体、和/或它们的组合。例如，湿蚀刻工艺可以包括以下湿蚀刻剂或其他合适的湿蚀刻剂的蚀刻：稀释的氢氟酸(DHF)；氢氧化钾(KOH)溶液；氨；包含氢氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液。形成鳍103的方法的许多其他实施例可能是合适的。
例如，S/D 104可以包括外延半导体材料，用于施加适当的应力并且提高器件100的性能。在本实施例中，S/D 104包括外延生长的硅锗(SiGe) 合金，其中，SiGe合金可以掺杂有一种或多种p型掺杂剂，例如硼(B) 或铟(In)。在一个实施例中，SiGe合金中Ge与Si的比率大于1(即Ge： Si>1)。在另一实施例中，SiGe合金中Ge原子浓度大于50％但小于90％，例如在约55％至约75％的范围内。换句话说，S/D 104包括Si1-xGex合金，其中x表示Ge组分的原子百分比，并且x大于50％并且小于90％，例如在从约55％至约75％的范围内。在各种实施例中，选择S/D 104中的Ge 浓度的特定范围以实现多个目的。一个目的是在随后的镓离子注入工艺期间提高镓在SiGe合金中的溶解度。已经发现，在SiGe合金中Ge：Si的比率越高，镓离子或原子越容易溶解在SiGe合金中，因此已经注入镓离子之后在SiGe合金中的缺陷就越少。然而，SiGe合金中的Ge：Si的比率也会影响其中的p型掺杂剂(例如硼)的激活。已经发现，Ge：Si的比率越高， p型掺杂剂的激活速率越低。在本实施例中，选择Ge：Si的比率(如上所述)有利于镓的溶解度以降低S/D接触电阻，同时确保用于器件性能的p 型掺杂剂的足够的激活速率。更进一步，SiGe合金中Ge：Si比率的选择与后续的退火工艺(例如操作18)一起工作以促进SiGe再结晶并且减少 SiGe合金中的缺陷。
在一个实施方式中，通过以下步骤来形成S/D 104：在鳍103中蚀刻凹槽和外延生长掺杂有一种或多种p型掺杂剂(例如硼和/或铟)的SiGe合金。可以在外延生长(原位)期间或在外延生长(非原位)之后实施掺杂。此外，每个S/D 104均可以包括具有不同掺杂剂浓度的一个或多个SiGe合金层(例如三层)。在一些实施例中，相邻的S/D 104可以彼此分离或者可以合并在一起。每个S/D 104均可以为任何合适的形状，例如多刻面形状(multi-facetshape)。
隔离结构105可以包括氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅 (SiON)、掺氟硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。在一个实施例中，通过以下步骤形成隔离结构105：在衬底102中或上方蚀刻沟槽(例如，作为形成鳍103的工艺的部分)；用绝缘材料填充沟槽并且对绝缘材料实施化学机械平坦化(CMP)工艺和/或回蚀刻工艺，留下剩余的绝缘材料作为隔离结构105。其他类型的隔离结构也可以是合适的，例如场氧化物和硅的局部氧化物(LOCOS)。隔离结构105可以包括多层结构，例如，在衬底102和鳍103的表面上具有一个或多个衬垫层，以及在一个或多个衬垫层上方具有主隔离层。
每个栅极堆叠件106均包括多层结构。例如，每个栅极堆叠件106均可以包括介电界面层(未示出)、位于介电界面层上方的栅极介电层106A (例如，SiO2)、以及位于栅极介电层106A上方的栅电极层106B。在一个实施例中，每个栅极堆叠件106均包括所谓的“高k金属栅极”，其中，高k金属栅极可以包括高k栅极介电层106A、位于高k栅极介电层上方的功函数层(栅电极层106B的一部分)、以及位于功函数层上方的金属层(栅电极层106B的另一部分)。栅极堆叠件106可以包括附加层，例如覆盖层和阻挡层。在各种实施例中，介电界面层可以包括介电材料，例如氧化硅 (SiO2)或氮氧化硅(SiON)，并且可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其他合适的方法来形成该介电界面层。高k栅极介电层可以包括氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、其他合适的金属氧化物、或它们的组合；并且可以通过ALD和/或其他合适的方法来形成该高k栅极介电层。功函数层可以包括但不限于选自以下组中的金属：氮化钛铝(TiAlN)、氮化钛(TiN)、氮化钽(TaN)、钌 (Ru)、钼(Mo)、钨(W)、铂(Pt)、铝(Al)或它们的组合；并且可以通过CVD、PVD和/或其他合适的工艺沉积该功函数层。栅电极层可以包括多晶硅或金属，例如铝(Al)、钨(W)、钴(Co)、铜(Cu) 和/或其他合适的材料；并且可以使用镀敷、CVD、PVD或其他合适的工艺来沉积。可以通过包括先栅极工艺和后栅极工艺的任何合适的工艺形成栅极堆叠件106。在先栅极工艺中，在形成S/D 104之前，将各种材料层沉积并图案化为为栅极堆叠件106。在后栅极工艺(也称为栅极替换工艺)中，首先形成临时栅极结构。然后，在形成S/D 104之后，去除临时栅极结构并替换为栅极堆叠件106。
鳍侧壁间隔件107和栅极间隔件108中的每一个均可以是单层或多层结构。在一些实施例中，间隔件107和108中的每一个均包括介电材料，例如氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、其它介电材料或它们的组合。在一个实例中，通过以下步骤形成间隔件107和108：包括在栅极堆叠件106和鳍103的器件100上方沉积第一介电层(例如，具有基本上均匀厚度的SiO2层)作为衬垫层，以及在第一介电层上方沉积作为第二介电层(例如，Si3N4层)主D形间隔件，并且然后，进行各向异性蚀刻以去除这些介电层的部分，从而形成间隔件107和108。此外，在生长S/D 104之前，在蚀刻工艺期间可以部分地去除鳍侧壁间隔件107，从而在鳍103中形成凹槽。在一些实施例中，可以通过这种蚀刻工艺完全地去除鳍侧壁间隔件107。
CESL 110可以包括氮化硅(Si3N4)、氮氧化硅(SiON)、具有氧(O) 或碳(C)元素的氮化硅、和/或其它材料。在一个实例中，CESL 110包括具有内应力(intrinsic stress)的氮化硅(Si3N4)，其中，内应力具有1GPa 或更高的量级。内应力对于p沟道器件是压缩应力，并且对于n沟道器件是拉伸应力。可以通过等离子体增强CVD(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成CESL 110。CESL 110覆盖S/D 104的外表面、栅极间隔件108的侧壁以及隔离结构105的顶面。
介电层(或层间电介质或ILD)112可以包括诸如原硅酸四乙酯(TEOS) 氧化物、未掺杂的硅酸盐玻璃或掺杂氧化硅(例如，硼磷硅酸盐玻璃 (BPSG)、熔融硅玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺硼硅玻璃(BSG)) 的介电材料和/或其他合适的介电材料。可以通过PECVD工艺、可流动CVD (FCVD)工艺或其他合适的沉积技术来沉积介电层112。在一个实施例中， CESL 110沉积在衬底102上方作为共形层，以覆盖衬底102上的各种结构，并且介电层112沉积在CESL 110上方以填充栅极堆叠件106之间的沟槽。
在操作14处，方法10(图1A)蚀刻介电层112和CESL 110以暴露 S/D 104，以准备在相应的S/D 104上方形成S/D接触件。这可能涉及包括沉积、光刻和蚀刻的各种工艺。
参考图3A和图3B，蚀刻掩模114形成在器件100上方，从而提供暴露器件100的各个部分的开口116。开口116对应于器件100中用于形成 S/D 104的S/D接触件的区域。在各种实施例中，蚀刻掩模114可以包括硬掩模层(例如，具有氮化硅或氧化硅)、光刻胶层或它们的组合。可以通过光刻和蚀刻工艺形成蚀刻掩模114。
参照图4A和图4B，例如使用干蚀刻工艺、湿蚀刻工艺、反应离子蚀刻工艺或其他合适的蚀刻工艺，通过开口116蚀刻器件100以去除介电层 112的暴露部分。在本实施例中，蚀刻工艺调整为对于介电层112的材料具有选择性，并且没有(或不显著地)蚀刻栅极堆叠件106、栅极间隔件 108和CESL 110。
参考图5A和图5B，例如使用干蚀刻工艺、湿蚀刻工艺或反应离子蚀刻工艺，通过开口116蚀刻器件100以去除CESL 110的位于开口116的底部处的部分。具体地，该蚀刻工艺是各向异性的并且调整为对于CESL 110 具有选择性。因此，在完成蚀刻工艺之后，CESL 110的部分保留在栅极堆叠件106的侧壁上方。在各种实施例中，可以通过一个联合蚀刻工艺或一个以上的蚀刻工艺来蚀刻介电层112和CESL 110。
在操作16处，方法10(图1A)将镓(Ga)离子或Ga和硼(B)离子注入到暴露的S/D 104中。在一个实施例中，操作16仅将Ga离子注入暴露的S/D 104。然而，当外延生长S/D 104时，可以将某些B离子原位掺杂到S/D 104中。因此，在这样的实施例中，Ga离子和B离子两者在S/D 104 中仍然可以共存。在另一实施例中，操作16将Ga离子和B离子注入到暴露的S/D104中。在该实施例中，注入B离子增加了S/D 104中的B含量。如图6A和图6B所示，操作16在S/D 104的顶部中产生Ga注入层124。在一个实施例中，器件100包括p型器件和n型器件。还在该实施例中，在操作16中，方法10形成覆盖n型器件并且暴露p型器件的掩模元件(未示出)。
在一些实施例中，Ga注入层124沿着Z方向的深度D1在约5nm至约 15nm的范围内。Ga离子可以在Ga注入层124内均匀或不均匀地分布(例如，其离子密度具有梯度分布)。如果深度D1太大(例如，超过20nm)，则由Ga注入引入的缺陷可能不会被待讨论的退火工艺(例如，操作18) 完全修复。还在这些实施例中，可以通过在约0.5keV至约10keV范围内的能量实施操作16处的Ga离子注入。通常，较小的注入能量产生较小的深度D1。在一些实施方式中，以通过在约5E14个离子/平方厘米(ions/cm2或简称为cm-2)至约8E15cm-2范围内(例如，在约5E14cm-2至约1E15cm-2) 的Ga离子剂量实施操作16处的Ga离子注入。Ga离子剂量的该选定范围在各种实施例中是有益的。如果离子剂量太低，则Ga注入(用于降低S/D 接触电阻)的影响可以忽略不计。如果离子剂量太高，则注入的Ga离子可能不会完全溶解到S/D104的SiGe合金中，从而增加SiGe合金中的缺陷。
在其中还在操作16处注入硼(B)离子的实施例中，Ga离子注入与B 离子注入可以一起实施或者可以分开实施。例如，可以通过在约1E15cm-2至约1E16cm-2的范围内(例如从约1E15cm-2至约2E15cm-2)的离子剂量以约0.5keV至约10keV之间的掺杂能量首先实施B离子注入，接着进行如上所述的Ga离子注入。在一些实施方式中，可以颠倒B离子注入和Ga离子注入的顺序，其中首先实施Ga离子注入。在一些其他实施例中，同时实施Ga离子注入和B离子注入。例如，在操作16处，可以通过在约1E15cm-2与约2E15cm-2之间的硼离子剂量以及在约5E14cm-2与约1E15cm-2之间的镓离子剂量以约0.5keV与约10keV之间的掺杂能量对S/D104进行注入。
在操作18处，方法10(图1A)对器件100实施第一退火工艺。在本实施例中，第一退火工艺被设计为使S/D 104中的SiGe合金再结晶，SiGe 合金在操作16期间可能已经被非晶化(变得更多非晶形的)。在本发明中，术语“SiGe再结晶”等是指SiGe合金通过去除由镓/硼离子注入引起的空位、非晶层和/或晶体缺陷而进行自修复(例如，在热处理期间)以变得更少非晶形的工艺。SiGe合金非晶形越少，它可以提供的导电性越好。在本实施例中，在约400摄氏度(℃)至约600℃(例如约525℃至约575℃) 范围内的温度下，并且在约10秒至约50秒(例如约20秒至约40秒)的范围内的持续时间段内实施第一退火工艺。在具体实例中，可以在约550℃下在约30秒的时间段内实施第一退火工艺。在各种实施例中，当退火温度较高时，退火持续时间可以较短，并且当退火温度较低时，退火持续时间可以较长。如下所述，选择退火温度和持续时间以有利于本发明的各个方面。
一个方面涉及栅极堆叠件106的完整性(integrity)。由于在本实施例中栅极堆叠件106可以包括一种或多种金属，所以第一退火工艺在足够低的温度下实施以便不损坏栅极堆叠件106。例如，在低于栅极堆叠件106 中的金属材料的熔点的温度下实施第一退火工艺。另一方面涉及S/D 104 中的SiGe再结晶。如果退火温度太低，则SiGe合金可能无法修复由Ga 离子注入引入的缺陷，或者退火工艺可能花费时间太长而无法经济有效地用于半导体制造。因此，第一退火工艺的温度被控制在上述范围内。第一退火工艺也用于另一目的(第一退火工艺导致Ga原子或离子分离并移动到 S/D 104的顶部)。Ga和硅通常形成共晶键。这些共价键在第一退火工艺的温度的条件下很容易断裂。一旦共价键断裂，Ga原子或离子就倾向于移动到S/D 104的顶部。因此，在操作18之后，Ga注入层124变得更薄。图 7A和图7B示出了第一退火工艺之后的半导体器件100。S/D 104内的分布有Ga的深度D2小于D1，例如小40％至60％。例如，在一个实施例中，其中D1为约15nm，D2可以在约6nm至约8nm的范围内。如后面将讨论的那样，分离的Ga原子或离子有助于降低S/D接触电阻。
操作18还可以清洁S/D 104的表面以使其为后续硅化工艺做好准备。例如，操作18可以使用干式清洁工艺或湿式清洁工艺。例如，干式清洁工艺可以使用SiConi蚀刻，其中，干式清洁工艺是涉及将目标同时暴露于 H2、NF3和NH3等离子体副产物的远程等离子体辅助干蚀刻工艺。例如，湿式清洁工艺可以涉及使用稀释的氢氟酸(DHF)溶液来清洁S/D 104的表面。
在操作20处，方法10(图1A)将层126沉积到开口116中，作为硅化工艺的部分。参考图8A和图8B，沉积层126以与包括SiGe合金和Ga 原子的S/D 104物理接触。在一个实施例中，层126包括具有一种或多种金属的导电材料。例如，层126可以包括钛(Ti)。附加或可选地，层126 可以包括钽(Ta)、镍(Ni)、铂(Pt)、镱(Yb)、铱(Ir)、铒(Er)、钴(Co)或它们的组合(例如，两种或多种金属的合金)。可以使用CVD、 PVD、ALD或其他合适的方法来沉积层126。在一个实施例中，可以在沉积层126之前去除蚀刻掩模114。
在操作22处，方法10(图1A)对器件100实施第二退火工艺以引起层126与S/D 104之间的反应，由此产生硅化物部件128(图9A和图9B)。在一个实施例中，在约400℃至约600℃(例如在约525℃至约575℃)范围内的温度条件下在约5秒至约30秒(例如在约10秒至约20秒)的范围内的持续时间段内实施第二退火工艺。在具体实例中，可以在约550℃的温度条件下在约15秒的时间段内实施第二退火工艺。在各种实施例中，当第二退火温度较高时，第二退火持续时间可以较短，并且当第二退火温度较低时，第二退火持续时间可以较长。选择第二退火工艺的温度以保持如上面参考操作18所讨论的栅极堆叠件106的完整性，第二退火工艺的温度仍然足够高以引起层126中的金属材料与S/D 104中的半导体材料进行反应。在一个实施例中，第二退火工艺使得Ga离子进一步分离并且在S/D 104 中向上移动。因此，Ga注入层124的深度甚至变得更薄。换句话说，在该实施例中，深度D3(图9A)小于深度D2(图7A)。
在本实施例中，硅化物部件128包括具有Si和来自层126的一种或多种金属的一种或多种化合物，并且还可以包括Ge和/或Ga。例如，硅化物部件128可以包括硅化钛(TiSi)、硅化镍(NiSi)、镍-铂硅化物(NiPtSi)、镍-铂-锗硅化物(NiPtGeSi)、镍-锗硅化物(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其他合适的化合物。根据层126中的金属的类型，硅化物部件128可以包括或可以不包括金属和Ga的稳定的化合物。例如，当层126包括Ti时，部件128可以包括稳定的Ti-Si化合物，并且Ga原子可以在S/D 104(包括 Ga注入层124)与硅化物部件128之间的界面处分离。因为分离的Ga原子有助于通过阻止硼原子与硅化物部件128反应来降低电阻，所以这为本发明提供了益处。在S/D 104的外延生长期间或在Ga和B离子注入期间(步骤16)，可以将硼原子引入到S/D 104中。在没有分离的Ga原子的情况下，硼原子将与Ti或TiSi反应来形成稳定的化合物Ti-B2或Ti-Si-B，从而具有相对较高的薄层电阻。
在操作24处，方法10(图1A)去除层126的未反应部分，使硅化物部件128暴露在开口116中(图10A和图10B)。操作24可以包括湿蚀刻工艺、干蚀刻工艺、反应离子蚀刻工艺或其他合适的蚀刻工艺。操作24中的蚀刻工艺对层126中的材料具有选择性。
在操作26处，方法10(图1A)实施第三退火工艺以激活S/D 104中的掺杂剂(例如，Ga或Ga和B)。在本实施例中，在高于第一(操作18) 和第二(操作22)退火工艺的温度下实施第三退火工艺。在另一实施例中，第三退火工艺的温度被设计为保持栅极堆叠件106的完整性。例如，在低于栅极堆叠件106中的金属的熔点的温度下实施第三退火工艺。在一个实施例中，在约700℃至约950℃(例如约800℃至约900℃)范围内的温度条件下在约10秒至约20秒的范围内的持续时间段内并且通常使用尖峰退火实施第三退火工艺。操作26可以使用一种或多种退火工艺，例如微波退火(MWA)工艺、微秒退火(μSSA)工艺、快速热退火(RTA)工艺、动态尖峰退火(DSA)工艺、熔化激光退火(MLA)工艺、和/或其他合适的退火工艺。
在操作28处，方法10(图1A)通过在开口116中沉积一种或多种金属或金属化合物(例如，TiN)在硅化物部件128上方形成S/D接触塞(或简称为S/D接触件)130。在本实施例中，参考图11A和图11B，S/D接触件130沉积在S/D 104的顶面和侧表面上方。具体地，S/D接触件130与硅化物部件128直接接触，其中，硅化物部件128与具有SiGe合金的S/D 104 接合。Ga注入层124(具有分离的Ga原子)设置在硅化物部件128与SiGe 合金之间。在一个实施例中，硅化物部件128中也存在一些Ga含量。然而，硅化物部件128中的Ga浓度远低于Ga注入层124中的Ga浓度。例如，硅化物部件128中的Ga浓度可能仅为Ga注入层124中的Ga浓度的约5％至约20％。通过包括Ga离子注入(操作16)、第一退火工艺(操作18) 和硅化工艺(操作20至24)的本发明的各个方面来有利地降低S/D路径 (包括S/D接触件130、硅化物部件128、Ga注入层124、和S/D 104中的 SiGe合金)的总电阻。
在实施例中，S/D接触件130可以包括钨(W)、钴(Co)、铜(Cu)，其他金属、金属氮化物(例如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN))或它们的组合，并且可以通过CVD、PVD、镀敷和/或其他合适的工艺形成该S/D接触件。在一个实施例中，在沉积用于S/D接触件130的金属材料之前去除蚀刻掩模114。此外，可以实施CMP 工艺以平坦化器件100的顶面，去除金属材料的多余部分，并且去除蚀刻掩模114(如果时刻掩模没有被去除的话)。在图11A和图11B中示出了最终的结构。
方法10可以实施进一步的步骤以完成器件100的制造。例如，方法 10可以实施各种工艺以形成用于n型晶体管的S/D接触件，形成电耦合至栅极堆叠件106的栅极接触件，并且形成连接FinFET以及器件100的其他部分的金属互连件以形成完整的IC。此外，尽管图2A至图11B示出的实施例包括鳍103(因此可应用于FinFET)，但是本发明不限于此，并且所公开的技术可以应用于平面型晶体管或者其他类型的多栅极晶体管以用于减小那些晶体管中的S/D接触电阻。
尽管不旨在限制本发明，但是本发明的一个或多个实施例为半导体器件及其形成工艺提供了许多益处。例如，本发明的实施例通过以下步骤来降低源极/漏极(S/D)接触电阻：将镓(Ga)离子注入具有硅锗(SiGe) 合金的S/D中，随后进行低温退火工艺。SiGe合金中的Ge原子浓度被设计为增加Ga在SiGe合金中的溶解度并且减少其中的离子注入缺陷。低温退火工艺也可以去除SiGe合金中的缺陷。此外，所提供的主题可以容易地集成到现有的IC制造流程中，并且可以应用于许多不同的工艺节点。
在一个示例性方面中，本发明涉及一种方法。该方法包括提供结构，其中，该结构包括衬底；衬底上方的栅极结构；以及与栅极结构相邻的含有硅锗(SiGe)的源极/漏极(S/D)部件。该方法还包括将镓(Ga)注入到S/D中；在第一温度下实施第一退火工艺以再结晶SiGe；在第一退火工艺之后，在S/D上方沉积包括金属的导电材料；在第二温度下实施第二退火工艺，以引起金属和S/D之间的反应；以及在第三温度下实施第三退火工艺，以激活S/D中含有Ga的掺杂剂。
在实施例中，所述第三温度高于所述第一温度和所述第二温度。
在实施例中，所述第一温度在约400摄氏度至约600摄氏度的范围内。
在实施例中，所述第一温度和所述第二温度均在约400摄氏度至约600 摄氏度的范围内。
在实施例中，所述硅锗中的Ge：Si的比率大于1。
在实施例中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
在实施例中，所述镓注入施加在约5E14cm-2至约1E15cm-2的范围内的 Ga离子剂量。
在实施例中，形成半导体器件的方法还包括：在注入镓的同时将硼(B) 注入到所述源极/漏极中。
在实施例中，所述金属包括钛。
在实施例中，所述栅极结构包括高k介电层和金属栅电极。
在实施例中，在所述第二退火工艺之后并且在所述第三退火工艺之前，还包括：去除所述导电材料的未反应部分。
在实施例中，在所述第三退火工艺之后，还包括：在所述源极/漏极上方沉积另一导电材料。
在该方法的一个实施例中，第三温度高于第一和第二温度。在另一实施例中，第一温度在约400摄氏度至约600摄氏度的范围内。在又一实施例中，第一和第二温度都在约400摄氏度至约600摄氏度的范围内。
在该方法的一些实施例中，SiGe中的Ge：Si的比率大于1。在一个实施例中，SiGe中的Ge浓度在约55％至约75％的范围内。在一些实施例中， Ga注入施加在约5E14cm-2至约1E15cm-2的范围内的Ga离子剂量。
在一个实施例中，该方法还包括在注入Ga的同时将硼(B)注入到S/D 中。在另一实施例中，在第二退火工艺之后和第三退火工艺之前，该方法还包括去除导电材料的未反应部分。在另一实施例中，在第三退火工艺之后，该方法还包括在S/D上方沉积另一导电材料。
在一个实施例中，金属包括钛。在一些实施例中，栅极结构包括高k 介电层和金属栅电极。
在另一示例性方面，本发明涉及一种方法。该方法包括提供结构，其中，该结构含有衬底；衬底上方的栅极结构；与栅极结构相邻的包括硅锗 (SiGe)的源极/漏极(S/D)部件；以及位于栅极结构的侧壁上方并且位于S/D上方的一个或多个介电层。该方法还包括蚀刻一个或多个介电层以形成暴露S/D的开口；通过开口将镓(Ga)离子注入到S/D中；以及在SiGe 的再结晶温度下实施第一退火工艺。该方法还包括在第一退火工艺之后在 S/D上方沉积包括金属的材料；实施第二退火工艺以在S/D上方形成具有 Si和金属的化合物；实施第三退火工艺以激活S/D中包括Ga的掺杂剂；并且在化合物上方形成S/D接触塞。
在实施例中，所述硅锗的再结晶温度在约525摄氏度至约575摄氏度的范围内。
在实施例中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
在实施例中，所述第一退火工艺致使所述镓离子分离并且移动到所述源极/漏极的顶部。
在实施例中，在低于所述第三退火工艺的温度的大约相同温度下实施所述第一退火工艺和所述第二退火工艺。
在该方法的一个实施例中，SiGe的再结晶温度在约525摄氏度至约575 摄氏度的范围内。在一些实施例中，SiGe中的Ge浓度在约55％至约75％的范围内。在一些实施例中，第一退火工艺导致Ga离子分离并移动到S/D 的顶部。在一些实施例中，在低于第三退火工艺的温度的大约相同温度下实施第一退火工艺和第二退火工艺。
在又一示例性方面中，本发明涉及一种方法。该方法包括提供结构，其中，该结构含有衬底；衬底上方的高k金属栅极结构；和与高k金属栅极结构相邻的包括硅锗(SiGe)的源极/漏极(S/D)部件。该方法还包括将镓(Ga)离子和硼(B)离子注入到S/D中，并且在SiGe的再结晶温度下实施第一退火工艺。该方法还包括在第一退火工艺之后在S/D上方沉积包括金属的导电材料；实施第二退火工艺以在S/D上方形成具有Si和金属的一种或多种化合物；实施第三退火工艺以激活S/D中的包括Ga和B的掺杂剂；以及在一种或多种化合物上方形成S/D接触塞。
在实施例中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
在实施例中，在高于所述再结晶温度的温度条件下实施所述第三退火工艺。
在该方法的一个实施例中，SiGe中的Ge浓度在约55％至约75％的范围内。在一个实施例中，在高于再结晶温度的温度下实施第三退火工艺。
以上论述了若干实施例的特征，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
提供结构，所述结构包括：
衬底；
栅极结构，位于所述衬底上方；和
源极/漏极(S/D)部件，与所述栅极结构相邻并包括硅锗(SiGe)；
将镓(Ga)注入到所述源极/漏极中；
在第一温度的条件下实施第一退火工艺以再结晶所述硅锗，其中，所述第一退火工艺致使所述镓分离并且移动到所述源极/漏极的顶部；
在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的导电材料；
在第二温度的条件下实施第二退火工艺以引起所述金属和所述源极/漏极之间的反应；以及
在第三温度的条件下实施第三退火工艺以激活所述源极/漏极中包括镓的掺杂剂。
2.根据权利要求1所述的形成半导体器件的方法，其中，所述第三温度高于所述第一温度和所述第二温度。
3.根据权利要求1所述的形成半导体器件的方法，其中，所述第一温度在约400摄氏度至约600摄氏度的范围内。
4.根据权利要求1所述的形成半导体器件的方法，其中，所述第一温度和所述第二温度均在约400摄氏度至约600摄氏度的范围内。
5.根据权利要求1所述的形成半导体器件的方法，其中，所述硅锗中的Ge：Si的比率大于1。
6.根据权利要求1所述的形成半导体器件的方法，其中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
7.根据权利要求1所述的形成半导体器件的方法，其中，所述镓注入施加在约5E14cm-2至约1E15cm-2的范围内的Ga离子剂量。
8.根据权利要求1所述的形成半导体器件的方法，还包括：
在注入镓的同时将硼(B)注入到所述源极/漏极中。
9.根据权利要求1所述的形成半导体器件的方法，其中，所述金属包括钛。
10.根据权利要求1所述的形成半导体器件的方法，其中，所述栅极结构包括高k介电层和金属栅电极。
11.根据权利要求1所述的形成半导体器件的方法，在所述第二退火工艺之后并且在所述第三退火工艺之前，还包括：
去除所述导电材料的未反应部分。
12.根据权利要求11所述的形成半导体器件的方法，在所述第三退火工艺之后，还包括：
在所述源极/漏极上方沉积另一导电材料。
13.一种形成半导体器件的方法，包括：
提供结构，所述结构包括：
衬底；
栅极结构，位于所述衬底上方；
源极/漏极(S/D)部件，与所述栅极结构相邻并包括硅锗(SiGe)；和
一个或多个介电层，位于所述栅极结构的侧壁上方和所述源极/漏极上方；
蚀刻所述一个或多个介电层以形成暴露所述源极/漏极的开口；
通过所述开口将镓(Ga)离子注入到所述源极/漏极中；
在所述硅锗的再结晶温度的条件下实施第一退火工艺，其中，所述第一退火工艺致使所述镓离子分离并且移动到所述源极/漏极的顶部；
在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的材料；
实施第二退火工艺以在所述源极/漏极上方形成具有Si和所述金属的化合物；
实施第三退火工艺以激活所述源极/漏极中包括镓的掺杂剂；以及
在所述化合物上方形成源极/漏极接触塞。
14.根据权利要求13所述的形成半导体器件的方法，其中，所述硅锗的再结晶温度在约525摄氏度至约575摄氏度的范围内。
15.根据权利要求13所述的形成半导体器件的方法，其中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
16.根据权利要求13所述的形成半导体器件的方法，其中，在约400℃至约600℃范围内的温度下，并且在约10秒至约50秒的范围内的持续时间段内实施所述第一退火工艺。
17.根据权利要求13所述的形成半导体器件的方法，其中，在低于所述第三退火工艺的温度的大约相同温度下实施所述第一退火工艺和所述第二退火工艺。
18.一种形成半导体器件的方法，包括：
提供结构，所述结构包括：
衬底；
高k金属栅极结构，位于所述衬底上方；和
源极/漏极(S/D)部件，与所述高k金属栅极结构相邻并且包括硅锗(SiGe)；
将镓(Ga)离子和硼(B)离子注入到所述源极/漏极中；
在所述硅锗的再结晶温度的条件下实施第一退火工艺，其中，所述第一退火工艺致使所述镓离子分离并且移动到所述源极/漏极的顶部；
在所述第一退火工艺之后，在所述源极/漏极上方沉积包括金属的导电材料；
实施第二退火工艺以在所述源极/漏极上方形成具有Si和所述金属的一种或多种化合物；
实施第三退火工艺以激活所述源极/漏极中的包括镓和硼的掺杂剂；以及
在所述一种或多种化合物上方形成源极/漏极接触塞。
19.根据权利要求18所述的形成半导体器件的方法，其中，所述硅锗中的Ge浓度在约55％至约75％的范围内。
20.根据权利要求18所述的形成半导体器件的方法，其中，在高于所述再结晶温度的温度条件下实施所述第三退火工艺。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879124B2 (en) * 2017-11-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method to form a fully strained channel region
US10164048B1 (en) 2017-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming source/drain contacts
DE102018106581B4 (de) * 2017-11-30 2020-07-09 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleiter-Bauelement und Verfahren zu dessen Herstellung
US10453947B1 (en) * 2018-06-12 2019-10-22 Vanguard International Semiconductor Corporation Semiconductor structure and high electron mobility transistor with a substrate having a pit, and methods for fabricating semiconductor structure
US11127817B2 (en) * 2018-07-13 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of semiconductor device structure by implantation
TWI782101B (zh) * 2018-09-27 2022-11-01 聯華電子股份有限公司 半導體結構及其製作方法
EP3716314A1 (fr) * 2019-03-29 2020-09-30 Commissariat à l'Energie Atomique et aux Energies Alternatives Prise de contact sur du germanium
US11133223B2 (en) 2019-07-16 2021-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Selective epitaxy
US11145726B2 (en) * 2019-10-16 2021-10-12 Applied Materials, Inc. Doped through-contact structures
US11380768B2 (en) * 2020-05-28 2022-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11888064B2 (en) * 2020-06-01 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US20210408258A1 (en) * 2020-06-25 2021-12-30 Intel Corporation Integrated circuit structures including a titanium silicide material
US11742210B2 (en) 2020-06-29 2023-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Deposition window enlargement
US11355587B2 (en) 2020-08-06 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain EPI structure for device boost
US20220051905A1 (en) * 2020-08-12 2022-02-17 Tokyo Electron Limited Formation of low-temperature and high-temperature in-situ doped source and drain epitaxy using selective heating for wrap-around contact and vertically stacked device architectures
US11798846B2 (en) * 2020-08-14 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Contact plug
US11532522B2 (en) 2021-01-19 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain EPI structure for improving contact quality
US11626495B2 (en) 2021-02-26 2023-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance
US20230420456A1 (en) * 2022-06-27 2023-12-28 Intel Corporation Sige:gab source or drain structures with low resistivity

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099404A1 (en) * 2005-10-28 2007-05-03 Sridhar Govindaraju Implant and anneal amorphization process
CN105720091A (zh) * 2010-12-21 2016-06-29 英特尔公司 穿过沟槽的选择性锗p接触金属化
US20170213889A1 (en) * 2016-01-22 2017-07-27 International Business Machines Corporation Low Resistance Source Drain Contact Formation
US20170221894A1 (en) * 2016-02-03 2017-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Field Effect Transistor Contact with Reduced Contact Resistance

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258485A (ja) * 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
DE102006051494B4 (de) * 2006-10-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst
EP2113940A1 (en) 2008-04-30 2009-11-04 Imec A method for producing NMOS and PMOS devices in CMOS processing
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9142642B2 (en) 2012-02-10 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for doped SiGe source/drain stressor deposition
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US20140065799A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9196522B2 (en) * 2013-10-16 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with buried insulator layer and method for forming
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
KR102219678B1 (ko) * 2014-08-12 2021-02-25 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9397008B1 (en) * 2015-04-21 2016-07-19 United Microelectronics Corp. Semiconductor device and manufacturing method of conductive structure in semiconductor device
KR102422430B1 (ko) * 2015-07-16 2022-07-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9831090B2 (en) 2015-08-19 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor device having gate spacer protection layer
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9633999B1 (en) 2015-11-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor mid-end-of-line (MEOL) process
US10490552B2 (en) 2015-12-29 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device having flat-top epitaxial features and method of making the same
US9614086B1 (en) 2015-12-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Conformal source and drain contacts for multi-gate field effect transistors
US9812453B1 (en) 2017-02-13 2017-11-07 Globalfoundries Inc. Self-aligned sacrificial epitaxial capping for trench silicide
US10269800B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical gate semiconductor device with steep subthreshold slope
US11037924B2 (en) * 2017-11-21 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming source/drain contacts
US10164048B1 (en) * 2017-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming source/drain contacts

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070099404A1 (en) * 2005-10-28 2007-05-03 Sridhar Govindaraju Implant and anneal amorphization process
CN105720091A (zh) * 2010-12-21 2016-06-29 英特尔公司 穿过沟槽的选择性锗p接触金属化
US20170213889A1 (en) * 2016-01-22 2017-07-27 International Business Machines Corporation Low Resistance Source Drain Contact Formation
US20170221894A1 (en) * 2016-02-03 2017-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Field Effect Transistor Contact with Reduced Contact Resistance

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