CN114927471A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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Publication number
CN114927471A
CN114927471A CN202210224216.0A CN202210224216A CN114927471A CN 114927471 A CN114927471 A CN 114927471A CN 202210224216 A CN202210224216 A CN 202210224216A CN 114927471 A CN114927471 A CN 114927471A
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Prior art keywords
layer
dielectric
dielectric layer
source
etching
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CN202210224216.0A
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Inventor
饶孟桓
黄麟淯
王圣璁
苏焕杰
庄正吉
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体结构的形成方法包含：提供具有多个源极/漏极电极与在多个源极/漏极电极上方的一第一介电层的结构；形成覆盖第一介电层的第一区域的第一蚀刻遮罩；对第一介电层执行第一蚀刻工艺，使得多个第一沟槽形成于多个源极/漏极电极上方；以具有不同于第一介电层的材料的第二介电层填充多个第一沟槽；去除第一蚀刻遮罩；对第一介电层的第一区域执行包括等向性蚀刻的第二蚀刻工艺，使得第二沟槽形成于多个源极/漏极电极中的第一个上方；沉积金属层进入至少第二沟槽中；以及对金属层执行一化学机械研磨(CMP)。

Description

半导体结构的形成方法
技术领域
本发明实施例涉及半导体技术，且特别涉及一种用于源极/漏极接触件的工艺与结构。
背景技术
半导体集成电路(integrated circuit，IC)经历了指数型成长。在集成电路(IC)材料和设计的科技进步已经产出许多代的集成电路(IC)，且每一代的集成电路(IC)具有比上一代更小且更复杂的电路。在集成电路(IC)的演变过程中，随着几何尺寸(如可使用制造工艺创造的最小的组件(component)(或线))的减少，功能密度(例如每个芯片面积上的内连线装置数目)已普遍性地增加。这样的微缩化工艺普遍地通过增加生产效率与降低相关成本来提供益处。这种微缩化也增加了处理与制造集成电路(IC)的复杂性，并且为了实现这些进步，需要在集成电路(IC)的处理与制造上进行类似的发展。
举例来说，当微缩化持续超过32nm或更小，靠近S/D接触件之中的隔离成为了问题。不佳的隔离可能导致时间相依介电崩溃(time dependent dielectric breakdown，TDDB，时间相关的介电击穿)的失败。非常需要用于增加靠近S/D接触件之中的隔离的方法与结构。
发明内容
本发明实施例提供了一种半导体结构的形成方法，包含：提供结构，结构具有多个源极/漏极电极与在多个源极/漏极电极上方的第一介电层；形成第一蚀刻遮罩，其覆盖第一介电层的第一区域；在第一蚀刻遮罩就位(in place)的情况下，对第一介电层执行第一蚀刻工艺，使得多个第一沟槽形成于多个源极/漏极电极上方；以第二介电层填充多个第一沟槽，第二介电层具有不同于第一介电层的材料；去除第一蚀刻遮罩；在去除第一蚀刻遮罩之后，对第一介电层的第一区域执行第二蚀刻工艺，使得第二沟槽形成于多个源极/漏极电极中的第一个上方，其中第二蚀刻工艺包括等向性蚀刻；沉积金属层进入至少第二沟槽中；以及对金属层执行化学机械研磨(CMP)。
本发明实施例提供了一种半导体结构的形成方法，包含：提供结构，结构具有多个栅极电极、于多个栅极电极上方的多个介电盖、多个源极/漏极电极、与于多个源极/漏极电极上方的第一介电层；形成第一蚀刻遮罩，其覆盖第一介电层的第一部分；在第一蚀刻遮罩就位的情况下，对第一介电层执行非等向性蚀刻工艺，使得多个第一沟槽形成于多个源极/漏极电极上方；以第二介电层填充多个第一沟槽，第二介电层具有不同于第一介电层的材料；对第二介电层与第一蚀刻遮罩执行第一化学机械研磨(CMP)工艺，直到暴露第一介电层的第一部分；对第一介电层的第一部分执行等向性蚀刻工艺，使得第二沟槽形成于多个源极/漏极电极中的第一个上方；沉积金属层进入到第二沟槽；以及对金属层执行第二CMP工艺。
本发明实施例提供了一种半导体结构，包含：半导体基板；第一、第二与第三源极/漏极电极，于半导体基板上方，其中第一与第二源极/漏极电极比第三源极/漏极电极窄；蚀刻停止层，其中蚀刻停止层的第一、第二、第三部分分别设置于第一、第二与第三源极/漏极电极上方；第一源极/漏极接触件，设置于第一源极/漏极电极正上方，且在蚀刻停止层的第一部分的侧壁之间，其中第一源极/漏极接触件具有大致上垂直的侧壁；第二源极/漏极接触件，设置于第三源极/漏极电极正上方；以及介电层，横向设置于蚀刻停止层的第二部分的侧壁之间，且横向设置于第二源极/漏极接触件与蚀刻停止层的第三部分的侧壁之间。
附图说明
以下将配合附图详述本公开的各方面。应强调的是，依据在业界的标准做法，各种特征并未按照比例绘制且仅用以说明例示。事实上，可能任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1A与1B是根据本发明实施例的一些实施例，示出用于形成半导体装置的方法的流程图。
图2A、3A、4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A、和15A是根据本发明实施例的一些实施例，示出根据图1A与1B中的方法，在各种制造阶段期间的半导体装置的一部分的上视图。
图2B、3B、4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、和15B是根据本发明实施例的一些实施例，示出根据图1A与图1B中的方法，在各种制造阶段期间沿着图2A-15A的B-B线的半导体装置的一部分的剖面图。
图16是根据本发明实施例的一实施例，示出沿着图14A的B-B线的半导体装置的一部分的剖面图。
图17是根据本发明实施例的另一实施例，示出沿着图14A的B-B线的半导体装置的一部分的剖面图。
符号说明
10：方法
12,14,16,18,20,22,24,26,28,30,32：操作
200：半导体装置
200-1,200-2：区域
201：基板
215：通道层
240：栅极堆叠
247：栅极间隔物
255：内间隔物
260：源极/漏极电极(S/D电极)
260W：源极/漏极电极(S/D电极)
269：CESL
270：ILD层
271：介电填充层
271'：部分
272：沟槽
274：沟槽
275：S/D接触件
276：沟槽
280：硅化物部件
282：金属层
349：栅极介电层
350：栅极电极
352：SAC层
356：介电盖
357：胶层
359：栅极导孔
360：蚀刻遮罩
361：图案化硬遮罩
361'：硬遮罩层
363：光刻胶图案
363'：光刻胶层
364：蚀刻遮罩
365：开口
H1：高度
W1,W2,W3,W4,W5,W6：宽度
T1,T2：厚度
具体实施方式
以下内容提供了很多不同的实施例或范例，用于实施本发明实施例的不同部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明实施例。举例来说，叙述中若提及第一部件形成于第二部件之上，可能包含第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。
再者，此处可能使用空间上的相关用语，例如“在……之下”、“在……下方”、“下方的”、“在……上方”、“上方的”和其他类似的用语可用于此，以便描述本发明实施例中一部件与其他部件之间的关系。此空间上的相关用语除了包含附图示出的方位外，也包含使用或操作中的装置的不同方位。当装置被转至其他方位(旋转90度或其他方位)时，则在此所使用的空间相对描述可同样依旋转后的方位来解读。此外，当用“约”，“近似”等描述数字或数字范围时，该用语旨在包括在合理范围内的数字，包括所描述的数字，例如所述数量的+/-10％或本领域技术人员理解的其他值。例如，术语“约5nm”包括4.5nm至5.5nm、4.0nm至5.0nm的尺寸范围。
本发明实施例大致上涉及一种半导体装置及其制造方法，尤其涉及源极/漏极(source/drain，S/D)接触件及其形成方法。源极/漏极接触件是指着落(land on)在晶体管的源极电极及/或漏极电极上的金属接触件或金属化合物。在某些情况下，它们也称为MD。形成S/D接触件通常包含多种工艺。其中一种工艺是在S/D电极上方蚀刻介电层，以便可以暴露S/D电极以连接到S/D接触件。介电层的蚀刻可以是非等向性或等向性。当使用非等向性蚀刻(例如通过等离子体轰击(plasma bombardment))时，它通常会在金属栅极(metalgates，MG)的顶部上的介电保护层(称为SAC层)中造成一些损失。结果，SAC层变成圆形(rounded)或锥形(tapered)。在沉积用于S/D接触件的金属之后，此圆形SAC层将导致相邻S/D接触件之间的横向距离减小，并可能导致TDDB失败。本发明实施例的目的是通过使用包含对S/D电极上方的介电层进行等向性蚀刻的工艺来解决上述问题。此外，在通过等向性蚀刻工艺蚀刻介电层时，可以分别处理相同集成电路(IC)上的隔离区域(晶体管分布稀疏(sparsely distributed))和密集区域(晶体管分布密集(densely distributed))，以实现对两区域的蚀刻轮廓的良好控制。
所公开的方法和结构可以应用于具有FinFET、全绕式(gate-all-around，GAA)晶体管或其他类型的晶体管的集成电路(IC)。GAA晶体管是指具有围绕晶体管通道的栅极堆叠(其包含栅极电极和栅极介电层)的晶体管，例如垂直堆叠的全绕式水平纳米线(vertically-stacked gate-all-around horizontal nanowire)或纳米片MOSFET装置。本发明所属技术领域中技术人员应当理解的是，他们可以容易地使用本发明实施例作为设计或修改其他结构的基础，以实现与本文介绍的实施例相同的目的及/或实现相同的优点。本发明实施例的各个方面将参考图1A-图17进一步讨论。
图1A和图1B根据本发明实施例的各种方面，示出了形成半导体装置200(或半导体结构200)的方法10的流程图。方法10仅是范例，并且不旨在限制本发明实施例超出权利要求中明确记载的内容。可以在方法10之前、期间和之后提供额外的操作，并且对于上述方法的额外实施例，可以取代、消除或重新定位所描述的一些操作。下面结合图2A-图17描述方法10，图2A-图17示出了制造工艺的各种阶段中的半导体装置200的部分。特别是图2A、3A、4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A和15A是半导体装置200的一部分的上视图；且图2B、3B、4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、15B、16和17是沿图2A-图15A的“B-B”线的半导体装置200的部分的剖面图。“B-B”线是沿着通道长度(或栅极长度(gate length，Lg))的方向。提供半导体装置200是用于说明的目的，并且不一定将本发明实施例限制为任何数量的装置、任何数量的区域、或者结构或区域的任何配置。此外，半导体装置200可以是在IC或其一部分的处理期间制造的中间装置，其可以包含静态随机存取存储器(staticrandom access memory，SRAM)及/或逻辑电路、被动元件(如电阻器、电容器和电感器)、及主动元件(如p型场效应晶体管(PFET)、n型FET(NFET)、多栅极FET(如FinFET和全绕式栅极装置)、金属氧化物半导体场效应晶体管(metal-oxide semiconductor field effecttransistors，MOSFET)、互补金属氧化物半导体(complementary metal-oxidesemiconductor，CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储器单元及其组合)。半导体装置200在图2A-图17中被示出为具有GAA晶体管。在替代实施例中，半导体装置200可以具有FinFET或其他类型的晶体管。为了清楚起见，图2A-图17已经被简化以更好地理解本发明实施例的发明构思。可以在半导体装置200中添加额外的部件，并且可以在半导体装置200的其他实施例中取代、修改或消除下面描述的一些部件。
在操作12处，方法10(图1A)提供半导体装置200的中间结构，其中的一实施例如图2A和图2B所示。参照图2A和图2B，半导体装置200包含基板201和在基板201中或上的各种部件。在所描绘的实施例中，半导体装置200包含在基板201的S/D区域上方的S/D电极260。在一实施例中，基板201包含从基材基板(base substrate)突出的各种半导体鳍片，并且S/D电极260设置在半导体鳍片上方。在这方面，图2B中所示的基板201的部分是半导体鳍片的一部分并且“x”方向是半导体鳍片的长度方向。尽管未示出，但半导体装置200包含隔离结构(如浅沟槽隔离(STI))以隔离如半导体鳍片的主动区域。
在一实施例中，基板201是块状(bulk)硅基板(即，包含块状单结晶硅)。在不同的实施例中，基板201可以包含其他半导体材料，例如锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其组合。在一替代实施例中，基板201是绝缘体上半导体基板，例如绝缘体覆硅(silicon-on-insulator，SOI)基板、绝缘体覆硅锗(silicon germanium-on-insulator，SGOI)基板或绝缘体覆锗(germanium-on-insulator，GOI)基板。
S/D电极260包含磊晶生长的半导体材料，例如磊晶生长的硅、锗或硅锗。S/D电极260可以通过任何磊晶工艺形成，包含化学气相沉积(chemical vapor deposition，CVD)技术(例如，气相磊晶及/或超高真空CVD)、分子束磊晶、其他合适的磊晶生长工艺或其组合。S/D电极260可以掺杂有n型掺质及/或p型掺质。在一些实施例中，对于n型晶体管，S/D电极260包含硅并且可以掺杂有碳、磷、砷、其他n型掺质或其组合(例如，形成Si:C磊晶S/D部件、Si:P磊晶S/D部件或Si:C:P磊晶S/D部件)。在一些实施例中，对于p型晶体管，S/D电极260包含硅锗或锗，并且可以掺杂硼、其他p型掺质或其组合(例如，形成Si:Ge:B磊晶S/D部件)。S/D电极260可以包含具有不同程度的掺质密度的多个磊晶半导体层。在一些实施例中，执行退火工艺(例如，快速热退火(rapid thermal annealing，RTA)及/或激光退火(laserannealing))以活化磊晶S/D电极260中的掺质。
仍然参照图2A和图2B，半导体装置200还包含悬置(suspend)在基板201上方并沿“x”方向连接S/D电极260的一或多个通道层215，在S/D电极260之间并环绕每个通道层215的栅极堆叠240、在S/D电极260和栅极堆叠240之间的内间隔物255、以及在栅极堆叠240的侧壁上方和最顶的通道层215上方的栅极间隔物(或外栅极间隔物)247。在栅极堆叠240中，半导体装置200还包含自对准盖(self-aligned capping，SAC)层352。在一些实施方式中(如图2B所描绘)，胶层357可以直接沉积在栅极堆叠240上，以提高栅极堆叠240与上述膜层之间的附着力。在半导体装置200是FinFET装置的一实施例中，通道层215合并为一个通道层(半导体鳍片通道)，并且省略了内间隔物255。进一步，在这样的FinFET实施例中，栅极堆叠240各自啮合(engage)半导体鳍片通道的顶部和侧壁，并且在图2B的剖面图中，栅极堆叠240将仅在半导体鳍片通道的顶部上。
在一些实施例中，通道层215包含适用于晶体管通道的半导体材料，例如硅、硅锗或其他半导体材料。在各种实施例中，通道层215可以呈棒状、条状、片状或其他形状。在一实施例中，通道层215是包含通道层215和逐层交替堆叠的其他(牺牲)半导体层的半导体层的初始堆叠的一部分。牺牲半导体层和通道层215包含不同的材料成分(例如不同的半导体材料、不同的组成原子百分比及/或不同的组成重量百分比)以实现蚀刻选择性。在形成栅极堆叠240的栅极取代工艺期间，去除牺牲半导体层，留下悬置在基板201上方的通道层215。在一些实施例中，例如，半导体装置200可以在每个晶体管中包含3-8个通道层215。
在一些实施例中，内间隔物255包括低介电常数(low-k)介电材料(例如，k<7)，其包含硅、氧、碳、氮、其他合适的材料或其组合(例如，氧化硅、氮化硅、氧氮化硅、碳化硅或氧碳氮化硅)。内间隔物255可以通过沉积和蚀刻工艺形成。举例来说，在蚀刻S/D沟槽之后，且在从S/D沟槽磊晶生长S/D电极260之前，可以使用蚀刻工艺使相邻通道层215之间的牺牲半导体层凹陷以形成垂直在相邻的通道层215之间的间隙(gap)。然后，沉积一种或多种介电材料(例如使用化学气相沉积(chemical vapor deposition，CVD)或原子层沉积(atomiclayer deposition，ALD))以填充间隙。执行另一蚀刻工艺以去除间隙外的介电材料，从而形成内间隔物255。
在所描绘的实施例中，每个栅极堆叠240包含栅极介电层349和栅极电极350。栅极介电层349可以包含高介电常数(high-k)介电材料，例如HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba，Sr)TiO3(BST)、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高介电常数介电材料或其组合。栅极介电层349可以通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法形成。在一些实施例中，每个栅极堆叠240还包含在栅极介电层349和通道层215之间的界面层。界面层可以包含二氧化硅、氮氧化硅或其他合适的材料。在一些实施例中，栅极电极350包含n型或p型功函数金属层和金属填充层。举例来说，n型功函数金属层可以包含具有足够低的有效功函数的金属，例如钛、铝、碳化钽、碳化氮化钽、氮化硅钽或其组合。举例来说，p型功函数金属层可以包含具有足够大的有效功函数的金属，例如氮化钛、氮化钽、钌、钼、钨、铂或其组合。举例来说，金属填充层可以包含铝、钨、钴、铜及/或其他合适的材料。栅极电极350可以通过CVD、PVD、电镀及/或其他合适的工艺形成。由于栅极堆叠240包含高介电常数介电层和金属层，它们也被称为高介电常数金属栅极。
在一些实施例中，栅极间隔物247包含介电材料，例如包含硅、氧、碳、氮、其他合适的材料或其组合(例如，氧化硅、氮化硅、氮氧化硅(SiON)、碳化硅、碳氮化硅(SiCN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN))的介电材料。在实施例中，栅极间隔物247可以包含La2O3、Al2O3、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Y2O3、AlON、TaCN、ZrSi或其他合适的材料。举例来说，包含硅和氮的介电层，例如氮化硅层，可以沉积在虚设栅极堆叠(其随后被高介电常数金属栅极240取代)上方并且随后被蚀刻(例如，非等向性蚀刻)以形成栅极间隔物247。在一些实施例中，栅极间隔物247包含多层结构，例如包含氮化硅的第一介电层和包含氧化硅的第二介电层。在一些实施例中，与栅极堆叠240相邻地形成多于一组的间隔物，例如密封间隔物、偏移间隔物(offset spacer)、牺牲间隔物、虚设间隔物及/或主间隔物。在实施例中，栅极间隔物247可以具有例如，约1nm至约40nm的厚度。
在一些实施例中，胶层357可以包含钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，例如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD形成。
在一些实施例中，SAC层352包含Si3N4、SiCN、SiC、SiOC、SiOCN、HfO2、ZrO2、ZrAlOx、HfAlOx、HfSiOx、Al2O3或其他合适的材料。SAC层352保护栅极堆叠240免于受到用于蚀刻S/D接触孔的蚀刻和CMP工艺，这将被讨论。SAC层352可以通过以下方式形成：使栅极堆叠240凹陷并且可选地使栅极间隔物247凹陷；在凹陷的栅极堆叠240上方和可选地在凹陷的栅极间隔物247上方沉积一种或多种介电材料；以及对一种或多种介电材料进行CMP工艺。在一些实施例中，SAC层352可以具有0nm(不存在)到大约50nm的厚度。
在所描绘的实施例中，半导体装置200还包含与栅极间隔物247相邻且于S/D电极260上方的接触蚀刻停止层(contact etch stop layer，CESL)269，以及于CESL 269上方的层间介电(inter-layer dielectric，ILD)层270。在实施例中，CESL 269可以包含Si3N4、SiCN、SiC、SiOC、SiOCN、HfO2、ZrO2、ZrAlOx、HfAlOx、HfSiOx、Al2O3或其他合适的材料；并且可以通过CVD、PVD、ALD或其他合适的方法形成。ILD层270可以包含四乙基正硅酸盐(tetraethylorthosilicate，TEOS)形成的氧化物(例如，使用CVD使TEOS与氧反应以沉积氧化硅)、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如，硼磷硅玻璃(borophosphosilicateglass，BPSG)、氟硅酸盐玻璃(fluoride-doped silicate glass，FSG)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼掺杂的硅酸盐玻璃(boron-doped silicate glass，BSG)等、低介电常数介电材料、其他合适的介电材料或其组合。每个ILD层270都可以通过等离子体辅助CVD(plasma enhanced CVD，PECVD)、流动CVD(flowable CVD，FCVD)或其他合适的方法形成。
仍然参照图2A和图2B，半导体装置200还包含设置在栅极电极350上或设置在胶层357上(如果存在的话)的栅极导孔359。栅极导孔359可以包含导电阻障层和导电阻障层上方的金属填充层。导电阻障层可以包含钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，例如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD及/或其他合适的工艺形成。金属填充层可以包含钨(W)、钴(Co)、钼(Mo)、钌(Ru)、镍(Ni)、铜(Cu)或其他金属，并且可以通过CVD、PVD、ALD、电镀或其他合适的工艺形成。在一些实施例中，在栅极导孔359中省略了导电阻障层。
进一步如图2B所示，半导体装置200包含不同的区域，包含区域200-1和200-2。举例来说，区域200-1中的晶体管比区域200-2中的晶体管排列得更密集。在这方面上，区域200-1可以被称为密集区域，并且区域200-2可以被称为隔离区域(或稀疏区域)。在本实施例中，区域200-2中的晶体管大于区域200-1中的晶体管。举例来说，区域200-2中的S/D电极260比区域200-1中的S/D电极260宽(沿着“x”方向)。为方便起见，区域200-2中的S/D电极260被标记为260W。进一步地，区域200-2中的通道层215比区域200-1中的通道层215长(沿“x”方向)；并且区域200-2中的栅极堆叠240比区域200-1中的栅极堆叠240长(沿“x”方向)。换言之，区域200-2中的晶体管具有比区域200-1中的晶体管更大的栅极长度。因为晶体管在两个区域200-1和200-2中具有不同的尺寸，所以将讨论对这两个区域不同地或分开地执行一些工艺步骤。
在操作14处，方法10(图1A)在区域200-1中的一些源极/漏极电极260上方形成蚀刻遮罩360，例如图4A和图4B中所示。蚀刻遮罩360覆盖ILD层270的一部分，ILD层270将被蚀刻以形成暴露区域200-1中的下方源极/漏极电极260的接触孔。蚀刻遮罩360包含图案化硬遮罩361上方的光刻胶图案363。操作14包含多种工艺，包括沉积、光微影和蚀刻工艺。举例来说，如图3A和图3B所示，硬遮罩层361'沉积(例如，通过CVD)在半导体装置200上方并且光刻胶层363'形成(例如，通过旋涂)在硬遮罩层361'上方。硬遮罩层361'可以包含氮化硅或其他合适的材料。在一些实施例中，抗反射涂层(anti-reflective coating，ARC)层或其他层可以沉积在光刻胶层363'和硬遮罩层361'之间。然后，操作14执行光微影工艺，其包含将光刻胶层363'暴露于辐射能(例如，紫外(ultraviolet，UV)光、深紫外(deep UV，DUV)光或极紫外(extreme ultraviolet，EUV)光)并在显影溶液中显影暴露的光刻胶层363'。显影后，光刻胶层363'被图案化成光刻胶图案363，如图4A和图4B所示。然后通过光刻胶图案363蚀刻硬遮罩层361'以产生图案化硬遮罩361。在本实施例中，蚀刻遮罩360覆盖区域200-1的部分而不覆盖区域200-2。
在操作16处，在蚀刻遮罩360就位的情况下，方法10(图1A)蚀刻半导体装置200以形成沟槽272，如图5A和图5B所示。在本实施例中，操作16对半导体装置200应用一个或多个非等向性干蚀刻工艺。使用非等向性干蚀刻工艺，使蚀刻符合蚀刻遮罩360的形状和尺寸。进一步地，调整(tune)一个或多个非等向性干蚀刻工艺以对ILD层270的材料具有选择性，而几乎不蚀刻通过蚀刻遮罩360暴露的其他材料，上述蚀刻遮罩360包含栅极导孔359、SAC层352和CESL 269。蚀刻遮罩360可以是在蚀刻工艺期间部分消耗。当操作16完成时，形成沟槽272，其具有CESL 269作为它们的底表面和侧壁表面。即使没有明确示出，在“y”方向上，沟槽272可以具有ILD层270(在蚀刻遮罩360之下)作为它们的侧壁表面。
在一些实施例中，由于操作16中的蚀刻工艺，SAC层352和CESL 269面向沟槽272的上角(upper corner)可以变成圆形。因此，随后沉积的介电填充层271可以横向延伸(沿“x”方向)到CESL 269和SAC层352正上方的区域。举例来说，如图17所示，介电填充层271的部分271'在CESL 269和SAC层352正上方延伸。
在操作18处，方法10(图1A)在半导体装置200上方沉积介电填充层(或介电填充物)271并填充沟槽272，例如图6A和图6B中所示。在所描绘的实施例中，在沉积介电填充层271之前去除光刻胶图案363(例如，通过光刻胶剥离)。然而，图案化硬遮罩361(或其一部分)保留并且被介电填充层271覆盖。在这个制造阶段没有去除图案化硬遮罩361，因此它仍然保护ILD层270的下面部分。另一方面，在这个制造阶段去除图案化硬遮罩361可能会不经意地蚀刻ILD层270的下面部分，这可能影响随后形成的S/D接触件的轮廓。在本实施例中，介电填充层271包含与ILD层270中包含的材料不同的材料，以便在后续蚀刻工艺中实现蚀刻选择性(在下面的操作22中讨论)。在一实施例中，介电填充层271包含Si3N4、SiCN、SiC、SiOC、SiOCN、HfO2、ZrO2、ZrAlOx、HfAlOx、HfSiOx、Al2O3或其组合。介电填充层271可以使用CVD、FCVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、其他合适的方法或其组合来沉积。
在操作20处，方法10(图1A)对介电填充层271和图案化硬遮罩361执行CMP工艺，直到暴露ILD层270，例如图7A和图7B中所示。在一实施例中，ILD层270用作CMP停止层。参照图7A和图7B，从半导体装置200的顶表面去除介电填充层271和图案化硬遮罩361。介电填充层271的剩余部分填充沟槽272。暴露ILD层270以进行进一步处理。
在操作22处，方法10(图1A)使用等向性蚀刻工艺蚀刻ILD层270以形成沟槽274，例如图8A和图8B所示。使用本发明实施例的等向性蚀刻工艺，沟槽274形成有垂直或大致上垂直的侧壁。沿着“y”方向的沟槽274的侧壁是CESL 269(参见图8B)并且沿着“x”方向的沟槽274的侧壁是介电填充层271(参见图8A)。如将要讨论的，金属化合物282/280将被填充到沟槽274中以形成S/D接触件275，如图14B所示。由于沟槽274具有垂直或大致上垂直的侧壁，相邻S/D电极260上的S/D接触件275沿“x”方向和“y”方向彼此保持最大可能距离。这大幅地改善了半导体装置200的TDDB(时间相依介电崩溃)性能。在一些方法中，通过非等向性蚀刻工艺，例如等离子体干蚀刻，蚀刻用于S/D接触件的沟槽。非等向性蚀刻工艺涉及对暴露表面的离子轰击。因此，面向沟槽的CESL 269和SAC层352的角将变圆形。对于具有这种圆顶角的沟槽，随后形成的S/D接触件将横向延伸进入到CESL 269和SAC层352上方的区域，这将减少相邻S/D接触件之间的距离并导致不理想的TDDB性能。此外，这种非等向性蚀刻工艺也可能不期望地降低SAC层352的高度。
在本实施例中，操作22的等向性蚀刻工艺为干蚀刻工艺，其施加一种或多种化学品与ILD层270反应。此外，干蚀刻工艺对ILD层270中的材料具有选择性。换言之，干蚀刻工艺中的一种或多种化学品与ILD层270的反应性比与包含SAC层352、栅极导孔359、CESL 269和介电填充层271的其他层的反应性大得多。在一些实施例中，等向性蚀刻工艺中ILD层270与其他层之间的蚀刻选择性为约50:1或更大。换言之，等向性蚀刻工艺蚀刻ILD层270的速度比蚀刻其他层快50倍(或更多)。在一实施例中，等向性蚀刻工艺应用HF、NH3、NF3或其组合作为蚀刻化学品。此类化学品为以上讨论的各个膜层提供所期望的蚀刻选择性。此外，在一些实施例中，等向性蚀刻工艺可以应用水蒸气(H2O)作为催化剂，这取决于所使用的蚀刻化学品和各个膜层中的材料。更进一步地，等向性蚀刻工艺可以使用N2、Ar或其组合作为一种或多种蚀刻化学品的载气。通过等向性蚀刻工艺，沟槽274形成为具有垂直或大致上垂直的侧壁，例如如图8B所示。
在操作24处，方法10(图1B)在半导体装置200上方形成另一个蚀刻遮罩364，例如图9A-图9B和图10A-图10B中所示。参照图9A-图9B，蚀刻遮罩364沉积在半导体装置200上方并填充沟槽274。在一实施例中，蚀刻遮罩364包含旋涂在半导体装置200上方的光刻胶层。在另一实施例中，蚀刻遮罩364包含在半导体装置200上方并填充沟槽274的抗反射涂层(ARC)层，并且还包含在ARC层上方旋涂的光刻胶层。参照图10A-图10B，图案化蚀刻遮罩364以在区域200-2中提供开口365(示出一个)，例如，使用光微影工艺和可选的蚀刻工艺。提供开口365于S/D电极260W上方。此外，开口365沿“x”方向形成为比下面的S/D电极260W窄。这有利地为着落于S/D电极260W上的S/D接触件提供足够的开口并且与附近的栅极导孔359保持足够的距离以减小耦合电容(coupling capacitance)。开口365暴露位于S/D电极260W正上方的介电填充层271。
在操作26处，方法10(图1B)通过开口365蚀刻介电填充层271以在介电填充层271中形成沟槽276，例如图11A-图11B所示。沟槽276暴露在S/D电极260W正上方的CESL 269。在一实施例中，操作26应用非等向性蚀刻工艺使得沟槽276形成有垂直或大致上垂直的侧壁。进一步地，使用非等向性蚀刻工艺有助于保持沟槽276的尺寸以与开口365的尺寸(从上视图)大致上匹配(match)。如果使用等向性蚀刻工艺，则沟槽276的尺寸将趋于大于开口365的尺寸(从上视图)。因为蚀刻遮罩364保护面向沟槽276的介电填充层271的顶角，这些顶角保持尖锐的边缘(sharp edges)，而不是变圆形。非等向性蚀刻工艺对介电填充层271中的材料是具有选择性的，并且对CESL 269几乎没有蚀刻。结果，CESL 269暴露在沟槽276的底部。
在操作28处，方法10(图1B)例如使用光刻胶剥离及/或其他方法去除蚀刻遮罩364。这重新获得了沟槽274，例如图12A-图12B中所示。然后，操作28对暴露在沟槽274和276中的CESL 269执行非等向性蚀刻工艺，借此去除在沟槽274和276中并且在S/D电极260和260W正上方的CESL 269的部分，如图12A-图12B所示。由于使用非等向性蚀刻工艺，CESL269保留在沟槽274和276的侧壁上。S/D电极260和260W的顶表面暴露在沟槽274和276中以用于进一步处理。调整非等向性蚀刻工艺为对CESL 269中的材料具有选择性，并且对SAC层352、栅极导孔359、介电填充层271几乎没有蚀刻。在一些实施例中，操作28通过去除其上的任何氧化或污染物，进一步清洗S/D电极260和260W的顶表面以用于随后形成硅化物。
在操作30处，方法10(图1B)在沟槽274和276中形成S/D接触件275并且电连接到S/D电极260和260W。参照图13A-图13B，操作30在沟槽274和276中形成硅化物部件280。为了形成硅化物部件280，操作30可以将一种或多种金属沉积进入到沟槽274和276中，对半导体装置200执行退火工艺，以引起一种或多种金属与S/D电极260和260W之间的反应，以产生硅化物部件280，并去除一种或多种金属的未反应部分，将硅化物部件280留在沟槽274和276中。一种或多种金属可包含钛(Ti)、钽(Ta)、钨(W)、镍(Ni)、铂(Pt)、镱(Yb)、铱(Ir)、铒(Er)、钴(Co)、其他贵金属、其他难熔金属(refractory metal)、稀土金属或其合金，并且可以使用CVD、PVD、ALD或其他合适的方法进行沉积。硅化物部件280可以包含硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、镍铂硅化物(NiPtSi)、镍铂锗硅化物(NiPtGeSi)、镍锗硅化物(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其他合适的化合物。
在形成硅化物部件280之后，操作30将金属层282沉积到沟槽274和276中并与硅化物部件280直接接触，如图13A-图13B所示。金属层282完全填充沟槽274和276。在实施例中，金属层282可以包含钨(W)、钴(Co)、钼(Mo)、钌(Ru)、铜(Cu)、镍(Ni)、钛(Ti)、钽(Ta)、铝(Al)、氮化钛(TiN)、氮化钽(TaN)或其他金属，并且可以通过CVD、PVD、ALD、电镀或其他合适的工艺形成。然后，操作30执行CMP工艺以去除半导体装置200的顶表面上方的金属层282的多余材料，例如图14A-图14B所示，借此形成S/D接触件275。S/D接触件275包含硅化物部件280和金属层282的部分，它们是金属化合物(metallic compound)或金属化合物(metalcompound)。
在操作32处，方法10(图1B)对半导体装置200执行进一步制造。在一实施例中，操作32在S/D接触件275上方形成介电盖356，例如图15A-图15B中所示。在一实施例中，介电盖356包含La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合适的材料。介电盖356保护S/D接触件275免于受到蚀刻和CMP工艺，并将S/D接触件275与形成在其上的内连线结构隔离(除了在S/D接触件275垂直连接到内连线结构的区域中)。在一些实施例中，SAC层352和介电盖356包含不同的材料以实现蚀刻选择性。在一些替代实施例中，半导体装置200包含SAC层352，但不包含介电盖356。在一些其他替代实施例中，半导体装置200包含介电盖356，但不包含SAC层352。在一些实施例中，例如，介电盖356可以具有0nm(不存在)到大约50nm的厚度。操作32还可以形成连接到S/D接触件275的S/D接触件导孔、形成在S/D接触件275上方的多层内连线、等等。
图16示出了半导体装置200中各种部件的一些尺寸。例如，区域200-1中的S/D电极260上的金属层282具有高度H1和宽度W3。在一实施例中，高度H1在约15nm到约40nm的范围内，并且宽度W3在8nm到约30nm的范围内。区域200-2中S/D电极260W上的金属层282比区域200-1中S/D电极260上的金属层282更宽且更高。区域200-2中的S/D电极260W上的金属层282具有宽度W6。在一实施例中，宽度W6在大约10nm到大约40nm的范围内。
区域200-1中的介电填充层271具有宽度Wl。在一实施例中，宽度W1在约8nm至约30nm的范围内。宽度W1大致上等于宽度W3。介电填充层271的部分横向设置在区域200-2中的CESL 269和金属层282之间并且在S/D电极260W正上方。介电填充层271的这些部分中的每个都具有宽度W5。在一实施例中，宽度W5在约2nm至约30nm的范围内。
区域200-1中的SAC层352具有宽度W2。在一实施例中，宽度W2在大约8nm到大约40nm的范围内。区域200-2中的SAC层352具有宽度W4(也参见图15A中的W4)。在一实施例中，宽度W4在大约20nm到大约80nm的范围内。宽度W4大于宽度W2。举例来说，在一些实施例中，W4与W2的比例可以在2到4的范围内。
CESL 269具有厚度Tl。在一实施例中，厚度T1在约0.5nm至约5nm的范围内。每个硅化物部件280均具有厚度T2。在一实施例中，厚度T2在约0.5nm至约5nm的范围内。
图17示出了半导体装置200的替代实施例，其中在操作16的期间形成具有圆角的沟槽272。结果，介电填充层271包含在CESL 269和SAC层352正上方延伸的部分271'。
尽管不旨在进行限制，但本发明实施例的一个或多个实施例为半导体装置及其形成工艺提供了许多益处。例如，本发明实施例提供了一种在半导体装置的密集区域和隔离区域中形成源极/漏极接触件的工艺。S/D接触件在两个区域中都形成有垂直或大致上垂直的侧壁，这有利于增加相邻S/D接触件之间的距离并改善半导体装置的TDDB性能。所提供的标的可以很容易地整合到现有的IC制造工艺中，并且可以应用于许多不同的工艺节点。
本发明实施例提供了一种半导体结构的形成方法，包含：提供结构，结构具有多个源极/漏极电极与在多个源极/漏极电极上方的第一介电层；形成第一蚀刻遮罩，其覆盖第一介电层的第一区域；在第一蚀刻遮罩就位(in place)的情况下，对第一介电层执行第一蚀刻工艺，使得多个第一沟槽形成于多个源极/漏极电极上方；以第二介电层填充多个第一沟槽，第二介电层具有不同于第一介电层的材料；去除第一蚀刻遮罩；在去除第一蚀刻遮罩之后，对第一介电层的第一区域执行第二蚀刻工艺，使得第二沟槽形成于多个源极/漏极电极中的第一个上方，其中第二蚀刻工艺包括等向性蚀刻；沉积金属层进入至少第二沟槽中；以及对金属层执行化学机械研磨(CMP)。
在一些实施例中，去除第一蚀刻遮罩的步骤包括：对第二介电层与第一蚀刻遮罩执行另一CMP工艺，直到暴露第一介电层的第一区域。
在一些实施例中，在执行第二蚀刻工艺的步骤之后，且在执行沉积金属层的步骤之前，还包括：沉积第二蚀刻遮罩层于结构上方，并填充第二沟槽；图案化第二蚀刻遮罩层以提供开口；通过开口对结构执行第三蚀刻工艺，使得第三沟槽形成于多个源极/漏极电极中的第二个上方；以及去除第二遮罩层，以重新获得第二沟槽，其中金属层沉积进入第二沟槽与第三沟槽中。
在一些实施例中，第三沟槽比第二沟槽宽，且第三蚀刻工艺包括非等向性蚀刻。
在一些实施例中，结构还包括：蚀刻停止层，于多个源极/漏极电极与第一介电层之间，方法还包括：在沉积金属层之前，蚀刻蚀刻停止层以暴露多个源极/漏极电极中的第一个与第二个。
在一些实施例中，等向性蚀刻包括施加一种或多种与第一介电层的反应性比与第二介电层的反应性更强的化学品(chemicals)。
在一些实施例中，一种或多种的化学品包括HF、NH3、NF3、或其组合。
在一些实施例中，等向性蚀刻还包括使用N2、Ar、或其组合作为载气用于一种或多种化学品。
在一些实施例中，等向性蚀刻还包括将水蒸气(H2O)与一种或多种化学品一起施加。
本发明实施例提供了一种半导体结构的形成方法，包含：提供结构，结构具有多个栅极电极、于多个栅极电极上方的多个介电盖(dielectric caps)、多个源极/漏极电极、以及于多个源极/漏极电极上方的第一介电层；形成第一蚀刻遮罩，其覆盖第一介电层的第一部分；在第一蚀刻遮罩就位的情况下，对第一介电层执行非等向性蚀刻工艺，使得多个第一沟槽形成于多个源极/漏极电极上方；以第二介电层填充多个第一沟槽，第二介电层具有不同于第一介电层的材料；对第二介电层与第一蚀刻遮罩执行第一化学机械研磨(CMP)工艺，直到暴露第一介电层的第一部分；对第一介电层的第一部分执行等向性蚀刻工艺，使得第二沟槽形成于多个源极/漏极电极中的第一个上方；沉积金属层进入到第二沟槽；以及对金属层执行第二CMP工艺。
在一些实施例中，非等向性蚀刻工艺对第一介电层比对多个介电盖更有选择性。
在一些实施例中，第一介电层包括TEOS形成的氧化物、未掺杂的硅酸盐玻璃、或掺杂的氧化硅，且第二介电层包括：Si3N4、SiCN、SiC、SiOC、SiOCN、HfO2、ZrO2、ZrAlOx、HfAlOx、HfSiOx、Al2O3或其组合。
在一些实施例中，等向性蚀刻包括施加一种或多种与第一介电层的反应性比与第二介电层的反应性更强的化学品。
在一些实施例中，一种或多种的化学品包括HF、NH3、NF3、或其组合，其中等向性蚀刻还包括使用N2、Ar、或其组合作为载气用于一种或多种化学品。
在一些实施例中，等向性蚀刻还包括施加水蒸气(H2O)作为蚀刻催化剂。
在一些实施例中，在执行等向性蚀刻工艺的步骤之后，且在执行沉积金属层的步骤之前，还包括：形成第二蚀刻遮罩于结构上方，其中第二蚀刻遮罩提供多个源极/漏极电极中的第二个上方的开口；通过开口对结构执行另一非等向性蚀刻工艺，使得第三沟槽形成于多个源极/漏极电极中的第二个上方，其中第三沟槽比多个源极/漏极电极中的第二个窄；以及去除第二蚀刻遮罩，其中金属层沉积进入第二沟槽与第三沟槽中。
本发明实施例提供了一种半导体结构，包含：半导体基板；第一、第二与第三源极/漏极电极，于半导体基板上方，其中第一与第二源极/漏极电极比第三源极/漏极电极窄；蚀刻停止层，其中蚀刻停止层的第一、第二、第三部分分别设置于第一、第二与第三源极/漏极电极上方；第一源极/漏极接触件，设置于第一源极/漏极电极正上方，且在蚀刻停止层的第一部分的侧壁之间，其中第一源极/漏极接触件具有大致上垂直的侧壁；第二源极/漏极接触件，设置于第三源极/漏极电极正上方；以及介电层，横向设置于蚀刻停止层的第二部分的侧壁之间，且横向设置于第二源极/漏极接触件与蚀刻停止层的第三部分的侧壁之间。
在一些实施例中，第二源极/漏极接触件比第一源极/漏极接触件宽。
在一些实施例中，介电层包括Si3N4、SiCN、SiC、SiOC、SiOCN、HfO2、ZrO2、ZrAlOx、HfAlOx、HfSiOx、Al2O3或其组合。
在一些实施例中，第一与第二源极/漏极接触件中的每个都包括硅化物层与于硅化物层上的金属层，其中金属层包括W、Ru、Co、Cu、Ti、TiN、Ta、TaN、Mo、Ni或其组合。
以上概述数个实施例的部件，以便在本发明所属技术领域中技术人员可以更加理解本发明实施例的观点。在本发明所属技术领域中技术人员应理解，他们能轻易地以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中技术人员也应理解，此类等效的结构并无悖离本发明的构思与范围，且他们能在不违背本发明的构思和范围下，做各式各样的改变、取代和替换。因此，本发明的保护范围当视权利要求所界定为准。

Claims (1)

1.一种半导体结构的形成方法，包括：
提供一结构，该结构具有多个源极/漏极电极与在该些源极/漏极电极上方的一第一介电层；
形成一第一蚀刻遮罩，其覆盖该第一介电层的一第一区域；
在该第一蚀刻遮罩就位的情况下，对该第一介电层执行一第一蚀刻工艺，使得多个第一沟槽形成于该些源极/漏极电极上方；
以一第二介电层填充该些第一沟槽，该第二介电层具有不同于该第一介电层的一材料；
去除该第一蚀刻遮罩；
在去除该第一蚀刻遮罩之后，对该第一介电层的该第一区域执行一第二蚀刻工艺，使得一第二沟槽形成于该些源极/漏极电极中的第一个上方，其中该第二蚀刻工艺包括一等向性蚀刻；
沉积一金属层进入至少该第二沟槽中；以及
对该金属层执行一化学机械研磨。
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