CN109830538A - Ldmos器件及其制造方法 - Google Patents

Ldmos器件及其制造方法 Download PDF

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CN109830538A
CN109830538A CN201910056315.0A CN201910056315A CN109830538A CN 109830538 A CN109830538 A CN 109830538A CN 201910056315 A CN201910056315 A CN 201910056315A CN 109830538 A CN109830538 A CN 109830538A
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CN109830538B (zh
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种LDMOS器件，包括：由形成于半导体衬底上的第一导电类型掺杂层的选定区域组成的漂移区，包括依次形成于第一导电类型掺杂层表面的栅介质层和栅导电材料层组成的栅极结构；第二导电类型掺杂的自对准沟道区由以栅极结构的第一侧面为自对准条件的带角度离子注入形成的掺杂区组成。本发明还公开了一种LDMOS器件的制造方法。本发明沟道的长度不受光刻工艺影响，能最大限度降低沟道长度，形成超低导通电阻；还能提高沟道长度的分布的均匀性并从而能提高器件性能的均匀性。

Description

LDMOS器件及其制造方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种横向扩散金属氧化物半导体(LDMOS)器件；本发明还涉及一种LDMOS器件的制造方法。
背景技术
低导通电阻是开关LDMOS器件所追求的主要目标，更低的导通电阻可以大幅度降低开关功耗。器件的导通电阻和击穿电压是一对相互制约的参数，现有技术中，在保持击穿电压不变的情况下降低导通电阻的方法包括：
(1)通过RESURF(Reduced Surface Field)设计，尽可能使LDMOS漂移区的电场分布均匀化，这样可适当增加漂移区掺杂浓度。
(2)尽可能缩小器件的尺寸，包括漂移区长度和沟道长度。在中等应用电压如小于30V的条件下，导通沟道电阻占器件导通电阻较大的比例，缩小沟道长度可以有效减小导通电阻。
不同于CMOS器件，LDMOS器件的漂移区是不能作阱掺杂，所以器件的阱、反穿通掺杂或阈值电压调整掺杂的形成区域必须通过光刻定义在器件漂移区以外，之后再进行离子注入形成；这些掺杂区的光刻和栅极结构如多晶硅栅的光刻一起决定多晶硅栅下之下的沟道的实际长度，沟道是在多晶硅栅上加大于阈值电压的栅极电压时形成于被多晶硅栅所覆盖的沟道区的表面的一层反型层。两次光刻对有源区各自的套准精度决定了沟道长度的控制精度。
超低导通电阻的LDMOS要求有超短的沟道长度，两次光刻的套准误差可能使得器件特性发生很大变化，如击穿电压下降、器件漏电或导通电阻增大等。
下面结合附图1A说明现有技术的缺点，如图1A所示，是现有LDMOS器件的结构示意图，现有LDMOS器件包括：
漂移区102，由第一导电类型掺杂层102的选定区域组成，所述第一导电类型掺杂层102形成于半导体衬底101上。
通常，所述半导体衬底101为硅衬底。所述漂移区102不能采用阱掺杂工艺形成；所述第一导电类型掺杂层102由形成于所述半导体衬底101表面的全面离子注入层组成或者由形成于所述半导体衬底101表面上的第一导电类型外延层组成，所述第一导电类型掺杂层102会延伸到整个所述半导体衬底101的表面，图1A中显示的所述第一导电类型掺杂层102都为所述漂移区102，故都采用标记102表示。
栅极结构，包括依次形成于所述第一导电类型掺杂层102表面的栅介质层105和栅导电材料层106，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面。通常，所述栅导电材料层106为多晶硅栅。所述栅介质层105为栅氧化层，
LDMOS器件还包括第二导电类型阱103，所述第二导电类型阱103通过光刻定义并加离子注入工艺形成于所述第一导电类型掺杂层102中，所述第二导电类型阱103 的第二侧面和对应的所述漂移区102的第一侧面接触。
现有方法中，沟道区直接采用第二导电类型阱103组成。被所述栅极结构覆盖的所述第二导电类型阱103的表面用于形成沟道。
在所述漂移区102中形成有漂移区场氧104，所述栅极结构的第二侧面延伸到所述漂移区场氧104表面上。
所述LDMOS器件还包括第一导电类型重掺杂的源区107和漏区108。
所述源区107形成于所述第二导电类型阱103的顶部区域且和所述栅极结构的第一侧面自对准。
所述漏区108形成于所述漂移区场氧104的第二侧外的所述漂移区102中。
在所述源区107的第一侧面外的所述第二导电类型阱103的顶部区域形成有第二导电类型重掺杂的沟道引出区109。
图1所示的LDMOS器件能为N型LDMOS器件和P型LDMOS器件；LDMOS器件为N 型LDMOS器件时，第一导电类型为N型，第二导电类型为P型。在其他实施例中也能为：LDMOS器件为P型LDMOS器件时，第一导电类型为P型，第二导电类型为N型。
由图1所示可知，由于被所述栅极结构覆盖的所述第二导电类型阱103的表面用于形成沟道，故实际的沟道长度如Lc101a所示，沟道长度Lc101a由所述第二导电类型阱103的光刻工艺和所述栅极结构的光刻工艺一起来定义，这会带来如下缺点：
首先，两次光刻定义会限制沟道长度Lc101a的缩小，从而也就限制了器件的导通电阻的缩小。
其次、两次光刻之间需要互相套准，故会存在套准误差，套准误差会使沟道长度产生偏差，例如同一半导体衬底101上的不同区域上的沟道长度会不相同，如图1B 中显示的沟道长度Lc101b就和沟道长度Lc101a不同；同样，采用相同工艺形成于不同半导体衬底101上的沟道长度也会不同。所以，会使器件的沟道长度不均匀，从而能使得器件特性发生很大变化，如击穿电压下降、器件漏电或导通电阻增大等。
发明内容
本发明所要解决的技术问题是提供一种LDMOS器件，能最大限度降低沟道长度，形成超低导通电阻。为此，本发明还提供一种LDMOS器件的制造方法。
为解决上述技术问题，本发明提供的LDMOS器件包括：
漂移区，由第一导电类型掺杂层的选定区域组成，所述第一导电类型掺杂层形成于半导体衬底上。
栅极结构，包括依次形成于所述第一导电类型掺杂层表面的栅介质层和栅导电材料层，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面。
第二导电类型掺杂的自对准沟道区，形成于所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层的表面，所述自对准沟道区由以所述栅极结构的第一侧面为自对准条件的带角度离子注入形成的掺杂区组成，被所述栅极结构覆盖的所述自对准沟道区的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。
进一步的改进是，LDMOS器件还包括第二导电类型阱，所述第二导电类型阱形成于通过光刻定义的所述第一导电类型掺杂层中，所述第二导电类型阱的第二侧面和对应的所述漂移区的第一侧面接触。
所述自对准沟道区的底部表面延伸到所述第二导电类型阱中。
进一步的改进是，在所述第二导电类型阱的表面区域中还形成有反穿通(APT) 离子注入区。
进一步的改进是，所述LDMOS器件还包括第一导电类型的源侧轻掺杂区(LDD)，所述源侧轻掺杂区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区的底部表面延伸到所述第二导电类型阱中，所述源侧轻掺杂区的第二侧面和所述自对准沟道区的第一侧面相接触。
进一步的改进是，在所述漂移区中形成有漂移区场氧，所述栅极结构的第二侧面延伸到所述漂移区场氧表面上。
在所述栅极结构的第一侧面和第二侧面上形成有侧墙。
所述LDMOS器件还包括第一导电类型重掺杂的源区和漏区。
所述源区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面的侧墙自对准，所述源区的底部表面延伸到所述第二导电类型阱中，所述所述源区的第二侧面和所述源侧轻掺杂区的第一侧面相接触。
所述漏区形成于所述漂移区场氧的第二侧外的所述漂移区中。
进一步的改进是，在所述源区的第一侧面外的所述第二导电类型阱的顶部区域形成有第二导电类型重掺杂的沟道引出区。
进一步的改进是，所述自对准沟道区的带角度离子注入为袋形(Pocket)离子注入。
进一步的改进是，所述半导体衬底为硅衬底，所述栅导电材料层为多晶硅栅。
所述第一导电类型掺杂层由形成于所述半导体衬底表面的全面离子注入层组成；或者，所述第一导电类型掺杂层由形成于所述半导体衬底表面上的第一导电类型外延层组成。
为解决上述技术问题，本发明提供的LDMOS器件的制造方法包括如下步骤：
步骤一、在半导体衬底上形成第一导电类型掺杂层，漂移区由所述第一导电类型掺杂层的选定区域组成。
步骤二、形成栅极结构，包括如下分步骤：
步骤21、在所述第一导电类型掺杂层表面形成栅介质层和栅导电材料层。
步骤22、光刻定义出所述栅极结构的形成区域，采用刻蚀工艺依次对所述栅导电材料层和所述栅介质层进行刻蚀形成所述栅极结构，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面。
步骤三、在所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层的表面形成第二导电类型掺杂的自对准沟道区，所述自对准沟道区是采用以所述栅极结构的第一侧面为自对准条件的带角度离子注入工艺形成，被所述栅极结构覆盖的所述自对准沟道区的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。
进一步的改进是，在形成所述栅极结构之前还包括形成第二导电类型阱的步骤，包括分步骤：
光刻定义出所述第二导电类型阱形成区域。
进行第二导电类型离子注入并进行热退火形成在所述第一导电类型掺杂层的选定区域中形成所述第二导电类型阱；所述第二导电类型阱的第二侧面和对应的所述漂移区的第一侧面接触。
所述自对准沟道区的底部表面延伸到所述第二导电类型阱中。
进一步的改进是，在形成所述第二导电类型阱区之后还包括进行反穿通离子注入在所述第二导电类型阱的表面区域中形成反穿通离子注入区的步骤。
之后还包括在所述漂移区中形成漂移区场氧的步骤，所述栅极结构的第二侧面延伸到所述漂移区场氧表面上。
进一步的改进是，步骤三之后还包括如下步骤：
步骤四、进行第一导电类型的轻掺杂离子注入形成源侧轻掺杂区，所述源侧轻掺杂区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区的底部表面延伸到所述第二导电类型阱中，所述源侧轻掺杂区的第二侧面和所述自对准沟道区的第一侧面相接触。
步骤五、在所述栅极结构的第一侧面和第二侧面上形成侧墙。
步骤六、进行第一导电类型重掺杂的源漏注入形成源区和漏区；所述源区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面的侧墙自对准，所述源区的底部表面延伸到所述第二导电类型阱中，所述所述源区的第二侧面和所述源侧轻掺杂区的第一侧面相接触。
所述漏区形成于所述漂移区场氧的第二侧外的所述漂移区中。
进一步的改进是，还包括如下步骤：
步骤七、进行第二导电类型重掺杂的离子注入在所述源区的第一侧面外的所述第二导电类型阱的顶部区域形成沟道引出区。
进一步的改进是，所述自对准沟道区的带角度离子注入为袋形离子注入。
进一步的改进是，所述半导体衬底为硅衬底，所述栅导电材料层为多晶硅栅。步骤一中，所述第一导电类型掺杂层通过在所述半导体衬底表面进行全面离子注入形成；或者，所述第一导电类型掺杂层由采用外延工艺形成于所述半导体衬底表面上的第一导电类型外延层组成。
本发明的沟道区采用和栅极结构的第一侧面自对准的自对准沟道区，自对准沟道区通过以栅极结构的第一侧面为自对准条件的带角度离子注入形成，带角度离子注入会使形成的自对准沟道区延伸到栅极结构的第一侧面内侧的底部的第一导电类型掺杂层的表面，被栅极结构覆盖的自对准沟道区的表面用于形成沟道，这就使得本发明的沟道的长度完全由带角度离子注入自对准定义，从而不受光刻工艺影响，其中光刻工艺的影响包括两个方面：
第一、现有技术中，沟道的实际长度完全由两次光刻如阱区的光刻和多晶硅栅的光刻来决定，本发明中不需要采用光刻工艺来定义沟道长度，故本发明能降低最大限度降低沟道长度，形成超低导通电阻。
第二、现有技术中，同一半导体衬底上往往集成有多个LDMOS器件，不同LDMOS 器件的沟道的实际长度之间具有差异，差异大小由两次光刻工艺分别对有源区的套准精度决定，这会使得现有技术中各区域的沟道的实际长度的差异各不相同，也即对沟道的长度精度的控制较差；而本发明中，沟道长度和光刻工艺的套准精度无关，故能提高沟道长度的分布的均匀性，即能提高对沟道长度的精度的控制，这能提高器件性能的均匀性。
另外，由于本发明能在缩小沟道长度的同时提高沟道长度的精度，故避免现有技术中在缩小沟道长度时由于沟道长度的均匀性变差而对器件的性能产生的不利影响，本发明能使器件的击穿电压得到保持或提高，能使器件的漏电得到保持或降低。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1A是现有LDMOS器件的结构示意图；
图1B是和图1A所对应的LDMOS器件具有沟道长度偏移的现有LDMOS器件；
图2是本发明实施例LDMOS器件的结构示意图；
图3A-图3E是本发明实施例方法各步骤中的器件结构示意图。
具体实施方式
如图2所示，是本发明实施例LDMOS器件的结构示意图，本发明实施例LDMOS器件包括：
漂移区2，由第一导电类型掺杂层2的选定区域组成，所述第一导电类型掺杂层 2形成于半导体衬底1上。
本发明实施例中，所述半导体衬底1为硅衬底。所述第一导电类型掺杂层2由形成于所述半导体衬底1表面的全面离子注入层组成，也即所述第一导电类型掺杂层2 会延伸到整个所述半导体衬底1的表面，图2中显示的所述第一导电类型掺杂层2都为所述漂移区2，故都采用标记2表示。在其他实施例中也能为：所述第一导电类型掺杂层2由形成于所述半导体衬底1表面上的第一导电类型外延层组成。
栅极结构，包括依次形成于所述第一导电类型掺杂层2表面的栅介质层5和栅导电材料层6，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面。本发明实施例中，所述栅导电材料层6为多晶硅栅。所述栅介质层5为栅氧化层，
第二导电类型掺杂的自对准沟道区10，形成于所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层2的表面，所述自对准沟道区10由以所述栅极结构的第一侧面为自对准条件的带角度离子注入形成的掺杂区组成，被所述栅极结构覆盖的所述自对准沟道区10的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。较佳选择为，所述自对准沟道区10的带角度离子注入为袋形离子注入。
LDMOS器件还包括第二导电类型阱3，所述第二导电类型阱3形成于通过光刻定义的所述第一导电类型掺杂层2中，所述第二导电类型阱3的第二侧面和对应的所述漂移区2的第一侧面接触。
所述自对准沟道区10的底部表面延伸到所述第二导电类型阱3中。
在所述第二导电类型阱3的表面区域中还形成有反穿通离子注入区。
所述LDMOS器件还包括第一导电类型的源侧轻掺杂区11，所述源侧轻掺杂区11 形成于所述第二导电类型阱3的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区11的底部表面延伸到所述第二导电类型阱3中，所述源侧轻掺杂区11 的第二侧面和所述自对准沟道区10的第一侧面相接触。
在所述漂移区2中形成有漂移区场氧4，所述栅极结构的第二侧面延伸到所述漂移区场氧4表面上。
在所述栅极结构的第一侧面和第二侧面上形成有侧墙12。
所述LDMOS器件还包括第一导电类型重掺杂的源区7和漏区8。
所述源区7形成于所述第二导电类型阱3的顶部区域且和所述栅极结构的第一侧面的侧墙12自对准，所述源区7的底部表面延伸到所述第二导电类型阱3中，所述所述源区7的第二侧面和所述源侧轻掺杂区11的第一侧面相接触。
所述漏区8形成于所述漂移区场氧4的第二侧外的所述漂移区2中。
在所述源区7的第一侧面外的所述第二导电类型阱3的顶部区域形成有第二导电类型重掺杂的沟道引出区9。
本发明实施例LDMOS器件为N型LDMOS器件，第一导电类型为N型，第二导电类型为P型。在其他实施例中也能为：LDMOS器件为P型LDMOS器件，第一导电类型为 P型，第二导电类型为N型。
本发明实施例的沟道区采用和栅极结构的第一侧面自对准的自对准沟道区10，自对准沟道区10通过以栅极结构的第一侧面为自对准条件的带角度离子注入形成，带角度离子注入会使形成的自对准沟道区10延伸到栅极结构的第一侧面内侧的底部的第一导电类型掺杂层2的表面，被栅极结构覆盖的自对准沟道区10的表面用于形成沟道，这就使得本发明实施例的沟道的长度完全由带角度离子注入自对准定义，从而不受光刻工艺影响，其中光刻工艺的影响包括两个方面：
第一、现有技术中，沟道的实际长度完全由两次光刻如阱区的光刻和多晶硅栅的光刻来决定，本发明实施例中不需要采用光刻工艺来定义沟道长度，故本发明能降低最大限度降低沟道长度，形成超低导通电阻。
第二、现有技术中，同一半导体衬底1上往往集成有多个LDMOS器件，不同LDMOS 器件的沟道的实际长度之间具有差异，差异大小由两次光刻工艺分别对有源区7的套准精度决定，这会使得现有技术中各区域的沟道的实际长度的差异各不相同，也即对沟道的长度精度的控制较差；而本发明实施例中，沟道长度和光刻工艺的套准精度无关，故能提高沟道长度的分布的均匀性，即能提高对沟道长度的精度的控制，这能提高器件性能的均匀性。
另外，由于本发明实施例能在缩小沟道长度的同时提高沟道长度的精度，故避免现有技术中在缩小沟道长度时由于沟道长度的均匀性变差而对器件的性能产生的不利影响，本发明实施例能使器件的击穿电压得到保持或提高，能使器件的漏电得到保持或降低。
如图3A至图3E所示，是本发明实施例方法各步骤中的器件结构示意图，本发明实施例LDMOS器件的制造方法包括如下步骤：
步骤一、如图3A所示，在半导体衬底1上形成第一导电类型掺杂层2，漂移区2 由所述第一导电类型掺杂层2的选定区域组成。
本发明实施例方法中，所述半导体衬底1为硅衬底。
所述第一导电类型掺杂层2通过在所述半导体衬底1表面进行全面离子注入形成。在其他实施例中也能为：所述第一导电类型掺杂层2由采用外延工艺形成于所述半导体衬底1表面上的第一导电类型外延层组成。
在后续形成所述栅极结构之前还包括形成第二导电类型阱3的步骤，包括分步骤：
光刻定义出所述第二导电类型阱3形成区域。
进行第二导电类型离子注入并进行热退火形成在所述第一导电类型掺杂层2的选定区域中形成所述第二导电类型阱3；所述第二导电类型阱3的第二侧面和对应的所述漂移区2的第一侧面接触。
在形成所述第二导电类型阱3区之后还包括进行反穿通离子注入在所述第二导电类型阱3的表面区域中形成反穿通离子注入区的步骤。
之后还包括在所述漂移区2中形成漂移区场氧4的步骤，所述栅极结构的第二侧面延伸到所述漂移区场氧4表面上。
步骤二、如图3B所示，形成栅极结构，包括如下分步骤：
步骤21、在所述第一导电类型掺杂层2表面形成栅介质层5和栅导电材料层6。本发明实施例方法中，所述栅导电材料层6为多晶硅栅，采用多晶硅淀积工艺形成。所述栅介质层5为栅氧化层，通常，栅氧化层采用热氧化工艺形成。
步骤22、光刻定义出所述栅极结构的形成区域，采用刻蚀工艺依次对所述栅导电材料层6和所述栅介质层5进行刻蚀形成所述栅极结构，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面。
步骤三、如图3C所示，在所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层2的表面形成第二导电类型掺杂的自对准沟道区10，所述自对准沟道区 10是采用以所述栅极结构的第一侧面为自对准条件的带角度离子注入工艺形成，被所述栅极结构覆盖的所述自对准沟道区10的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。
所述自对准沟道区10的底部表面延伸到所述第二导电类型阱3中。
本发明实施例方法中，所述自对准沟道区10的带角度离子注入为袋形离子注入。
步骤三之后还包括如下步骤：
步骤四、如图3C所示，进行第一导电类型的轻掺杂离子注入形成源侧轻掺杂区11，所述源侧轻掺杂区11形成于所述第二导电类型阱3的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区11的第二侧面和所述自对准沟道区10的第一侧面相接触。如图2所示，所述源侧轻掺杂区11在后续工艺中会经历热过程并从而扩散，扩散后的所述源侧轻掺杂区11的底部表面延伸到所述第二导电类型阱3中。
步骤五、如图3D所示，在所述栅极结构的第一侧面和第二侧面上形成侧墙12。
步骤六、如图3E所示，进行第一导电类型重掺杂的源漏注入形成源区7和漏区8；所述源区7形成于所述第二导电类型阱3的顶部区域且和所述栅极结构的第一侧面的侧墙12自对准，所述源区7的底部表面延伸到所述第二导电类型阱3中，所述所述源区7的第二侧面和所述源侧轻掺杂区11的第一侧面相接触。
所述漏区8形成于所述漂移区场氧4的第二侧外的所述漂移区2中。
还包括如下步骤：
步骤七、进行第二导电类型重掺杂的离子注入在所述源区7的第一侧面外的所述第二导电类型阱3的顶部区域形成沟道引出区9。
本发明实施例方法中，LDMOS器件为N型LDMOS器件，第一导电类型为N型，第二导电类型为P型。在其他实施例方法中，也能为：LDMOS器件为P型LDMOS器件，第一导电类型为P型，第二导电类型为N型。
本发明实施例方法中，将LDMOS器件的沟道区的掺杂分两步完成，第一步在栅极结构的栅介质层5和栅导电材料层即多晶硅栅6形成之前，通过光刻定义所述第二导电类型阱即P型阱3，进行P型阱3的离子注入和反穿通离子注入，P型阱3可显著改善器件的可靠性，扩大器件的安全工作范围，反穿通离子注入形成的反穿通离子注入区则保证在极短沟道下不会发生穿通；第二步是在多晶硅栅刻蚀完成形成器件的栅极结构以后通过自对准离子注入完成，这步和低压NMOS的LDD离子注入和Pocket离子注入一起完成，从源区端沿着多晶硅栅的边缘即多晶硅栅6的第一侧面的边缘进行 Pocket离子注入，这会在整个沟道区即包括了所述P型阱3和所述反穿通离子注入区的沟道区的表面形成阈值电压调整的掺杂层即所述自对准沟道区10，沟道长度由所述自对准沟道区10的长度决定也即由Pocket离子注入决定；LDD注入则保证了源极和沟道的良好互联。因为Pocket离子注入和LDD离子注入都是多晶硅栅自对准注入，沟道区表面的沟道长度将不受光刻套准影响，极大提高了器件特性均匀性，同时也可以允许把沟道长度做到更短。另外低压器件如低于NMOS管的LDD是非常低能量的离子注入，结深也很浅，确保在极短沟道长度时不发生穿通。由于pocket离子注入和LDD离子注入与低压NMOS共享，不需要加额外的光刻。
本发明实施例方法形成的LDMOS器件中P型阱3的离子注入和APT离子注入对LDMOS器件的特性不敏感，即使该层光刻有对准偏差，不会对LDMOS器件的电学有很大影响。而器件的重要特征参数表面沟道长度由自对准pocket离子注入形成，没有光刻偏差问题，改善了器件的均匀性。同时可以允许将器件的沟道长度设计成很短，已达到超低导通电阻的目标。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (15)

1.一种LDMOS器件，其特征在于，包括：
漂移区，由第一导电类型掺杂层的选定区域组成，所述第一导电类型掺杂层形成于半导体衬底上；
栅极结构，包括依次形成于所述第一导电类型掺杂层表面的栅介质层和栅导电材料层，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面；
第二导电类型掺杂的自对准沟道区，形成于所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层的表面，所述自对准沟道区由以所述栅极结构的第一侧面为自对准条件的带角度离子注入形成的掺杂区组成，被所述栅极结构覆盖的所述自对准沟道区的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。
2.如权利要求1所述的LDMOS器件，其特征在于：LDMOS器件还包括第二导电类型阱，所述第二导电类型阱形成于通过光刻定义的所述第一导电类型掺杂层中，所述第二导电类型阱的第二侧面和对应的所述漂移区的第一侧面接触；
所述自对准沟道区的底部表面延伸到所述第二导电类型阱中。
3.如权利要求2所述的LDMOS器件，其特征在于：在所述第二导电类型阱的表面区域中还形成有反穿通离子注入区。
4.如权利要求2所述的LDMOS器件，其特征在于：所述LDMOS器件还包括第一导电类型的源侧轻掺杂区，所述源侧轻掺杂区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区的底部表面延伸到所述第二导电类型阱中，所述源侧轻掺杂区的第二侧面和所述自对准沟道区的第一侧面相接触。
5.如权利要求4所述的LDMOS器件，其特征在于：在所述漂移区中形成有漂移区场氧，所述栅极结构的第二侧面延伸到所述漂移区场氧表面上；
在所述栅极结构的第一侧面和第二侧面上形成有侧墙；
所述LDMOS器件还包括第一导电类型重掺杂的源区和漏区；
所述源区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面的侧墙自对准，所述源区的底部表面延伸到所述第二导电类型阱中，所述所述源区的第二侧面和所述源侧轻掺杂区的第一侧面相接触；
所述漏区形成于所述漂移区场氧的第二侧外的所述漂移区中。
6.如权利要求5所述的LDMOS器件，其特征在于：在所述源区的第一侧面外的所述第二导电类型阱的顶部区域形成有第二导电类型重掺杂的沟道引出区。
7.如权利要求1所述的LDMOS器件，其特征在于：所述自对准沟道区的带角度离子注入为袋形离子注入。
8.如权利要求1至7中任意权项所述的LDMOS器件，其特征在于：所述半导体衬底为硅衬底，所述栅导电材料层为多晶硅栅；
所述第一导电类型掺杂层由形成于所述半导体衬底表面的全面离子注入层组成；或者，所述第一导电类型掺杂层由形成于所述半导体衬底表面上的第一导电类型外延层组成。
9.一种LDMOS器件的制造方法，其特征在于，包括如下步骤：
步骤一、在半导体衬底上形成第一导电类型掺杂层，漂移区由所述第一导电类型掺杂层的选定区域组成；
步骤二、形成栅极结构，包括如下分步骤：
步骤21、在所述第一导电类型掺杂层表面形成栅介质层和栅导电材料层；
步骤22、光刻定义出所述栅极结构的形成区域，采用刻蚀工艺依次对所述栅导电材料层和所述栅介质层进行刻蚀形成所述栅极结构，所述栅极结构具有由光刻工艺定义的第一侧面和第二侧面；
步骤三、在所述栅极结构的第一侧面内侧的底部的所述第一导电类型掺杂层的表面形成第二导电类型掺杂的自对准沟道区，所述自对准沟道区是采用以所述栅极结构的第一侧面为自对准条件的带角度离子注入工艺形成，被所述栅极结构覆盖的所述自对准沟道区的表面用于形成沟道，所述沟道的长度由所述带角度离子注入自对准定义从而不受光刻工艺影响。
10.如权利要求9所述的LDMOS器件的制造方法，其特征在于：在形成所述栅极结构之前还包括形成第二导电类型阱的步骤，包括分步骤：
光刻定义出所述第二导电类型阱形成区域；
进行第二导电类型离子注入并进行热退火形成在所述第一导电类型掺杂层的选定区域中形成所述第二导电类型阱；所述第二导电类型阱的第二侧面和对应的所述漂移区的第一侧面接触；
所述自对准沟道区的底部表面延伸到所述第二导电类型阱中。
11.如权利要求10所述的LDMOS器件的制造方法，其特征在于：在形成所述第二导电类型阱区之后还包括进行反穿通离子注入在所述第二导电类型阱的表面区域中形成反穿通离子注入区的步骤；
之后还包括在所述漂移区中形成漂移区场氧的步骤，所述栅极结构的第二侧面延伸到所述漂移区场氧表面上。
12.如权利要求11所述的LDMOS器件的制造方法，其特征在于：步骤三之后还包括如下步骤：
步骤四、进行第一导电类型的轻掺杂离子注入形成源侧轻掺杂区，所述源侧轻掺杂区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面自对准，所述源侧轻掺杂区的底部表面延伸到所述第二导电类型阱中，所述源侧轻掺杂区的第二侧面和所述自对准沟道区的第一侧面相接触；
步骤五、在所述栅极结构的第一侧面和第二侧面上形成侧墙；
步骤六、进行第一导电类型重掺杂的源漏注入形成源区和漏区；所述源区形成于所述第二导电类型阱的顶部区域且和所述栅极结构的第一侧面的侧墙自对准，所述源区的底部表面延伸到所述第二导电类型阱中，所述所述源区的第二侧面和所述源侧轻掺杂区的第一侧面相接触；
所述漏区形成于所述漂移区场氧的第二侧外的所述漂移区中。
13.如权利要求11所述的LDMOS器件的制造方法，其特征在于，还包括如下步骤：
步骤七、进行第二导电类型重掺杂的离子注入在所述源区的第一侧面外的所述第二导电类型阱的顶部区域形成沟道引出区。
14.如权利要求9所述的LDMOS器件的制造方法，其特征在于：所述自对准沟道区的带角度离子注入为袋形离子注入。
15.如权利要求9至14中任意权项所述的LDMOS器件的制造方法，其特征在于：所述半导体衬底为硅衬底，所述栅导电材料层为多晶硅栅；
步骤一中，所述第一导电类型掺杂层通过在所述半导体衬底表面进行全面离子注入形成；或者，所述第一导电类型掺杂层由采用外延工艺形成于所述半导体衬底表面上的第一导电类型外延层组成。
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