CN109818607A - Level shift circuit - Google Patents
Level shift circuit Download PDFInfo
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- CN109818607A CN109818607A CN201910034187.XA CN201910034187A CN109818607A CN 109818607 A CN109818607 A CN 109818607A CN 201910034187 A CN201910034187 A CN 201910034187A CN 109818607 A CN109818607 A CN 109818607A
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- level shift
- shift circuit
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 10
- 239000001301 oxygen Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 230000005611 electricity Effects 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The invention discloses a kind of level shift circuits, including bias voltage to provide unit, the first NMOS tube, the second NMOS tube, the first PMOS tube, the second PMOS tube, third PMOS tube and the 4th PMOS tube；Bias voltage provides unit and is adapted to provide for bias voltage；For the grid of first NMOS tube as first input end, the source electrode of the first NMOS tube connect the first power supply line, the drain electrode of the drain electrode connection third PMOS tube of the first NMOS tube with the source electrode of the second NMOS tube；The grid that the grid of third PMOS tube connects the 4th PMOS tube is simultaneously suitable for receiving bias voltage, and the source electrode of third PMOS tube connects the drain electrode of the first PMOS tube, the grid of the second PMOS tube and as the first output end；The grid of second NMOS tube is as the second input terminal, the drain electrode of drain electrode the 4th PMOS tube of connection of the second NMOS tube；The source electrode of 4th PMOS tube connects the drain electrode of the second PMOS tube, the grid of the first PMOS tube and as second output terminal；The source electrode of first PMOS tube connect second source line with the source electrode of the second PMOS tube.Level shift circuit provided by the invention can avoid thickness grid oxygen technique.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of level shift circuit.
Background technique
Level shift circuit is widely used in as the intermediate bridge between low-voltage control circuit and high-voltage driving circuit
In middle low power power supply, display driving, electric consumption on lighting sub-ballast and motor driven converter constant power integrated circuit.It is typical
Level shift circuit as shown in Figure 1, the level shift circuit include the first NMOS tube N1, the second NMOS tube N2, first
PMOS tube P1 and the second PMOS tube P2.
First input end VI, first NMOS of the grid of the first NMOS tube N1 as the level shift circuit
The source electrode of the source electrode of pipe N1 and the second NMOS tube N2 are all connected with the first power supply line VSS, the drain electrode of the first NMOS tube N1
Connect the drain electrode of the first PMOS tube P1, the grid of the second PMOS tube P2 and as the level shift circuit first
Output end VO；Second input terminal VIB of the grid of the second NMOS tube N2 as the level shift circuit, described second
The drain electrode of NMOS tube N2 connects the drain electrode of the second PMOS tube P2, the grid of the first PMOS tube P1 and as the level
The second output terminal VOB of shift circuit；The source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are all connected with
Second source line VDD, the supply voltage that the second source line VDD is provided are higher than the power supply that the first power supply line VSS is provided
Voltage.The working principle of the level shift circuit is as follows:
When the first input end VI receives logic-low signal " 0 ", the second input terminal VIB receives logically high electricity
When ordinary mail number " 1 ", the first NMOS tube N1 and the second PMOS tube P2 cut-off, the second NMOS tube N2 and described first
PMOS tube P1 conducting, the voltage of the second output terminal VOB are pulled low to the low power supply electricity that the first power supply line VSS is provided
Pressure, the voltage of the first output end VO are pulled to the high power supply voltage that the second source line VDD is provided；
When the first input end VI receives logic-low signal " 1 ", the second input terminal VIB receives logically high electricity
When ordinary mail number " 0 ", the first NMOS tube N1 and the second PMOS tube P2 conducting, the second NMOS tube N2 and described first
PMOS tube P1 cut-off, the voltage of the second output terminal VOB are pulled to the high power supply electricity that the second source line VDD is provided
Pressure, the voltage of the first output end VO are pulled low to the low supply voltage that the first power supply line VSS is provided.
To guarantee that the level shift circuit works normally, the high voltage PMOS pipe in the level shift circuit is (i.e. described
The first PMOS tube P1 and second PMOS tube P2) grid voltage endurance capability must not drop below the second source line VDD and provide
High power supply voltage.Therefore, the high voltage PMOS pipe in the level shift circuit must be using thicker oxide layer as grid oxygen
Change layer, just needs additional increase thick grid oxygen technique together during fabrication, and thick grid oxygen technique will lead to the mutual conductance decline of device, shadow
Device performance is rung, and process complexity and production cost are also increase accordingly.
Summary of the invention
To be solved by this invention is that existing level shift circuit needs additionally to increase during fabrication thick grid oxygen work together
The problem of skill.
The present invention is achieved through the following technical solutions:
A kind of level shift circuit, including bias voltage provide unit, the first NMOS tube, the second NMOS tube, the first PMOS
Pipe, the second PMOS tube, third PMOS tube and the 4th PMOS tube；
The bias voltage provides unit and is adapted to provide for bias voltage；
First input end of the grid of first NMOS tube as the level shift circuit, first NMOS tube
Source electrode and the source electrode of second NMOS tube are all connected with the first power supply line, and the drain electrode of first NMOS tube connects the third
The drain electrode of PMOS tube；
The grid of the third PMOS tube connects the grid of the 4th PMOS tube and is suitable for receiving the bias voltage, institute
The source electrode for stating third PMOS tube connects the drain electrode of first PMOS tube, the grid of second PMOS tube and as the level
First output end of shift circuit；
Second input terminal of the grid of second NMOS tube as the level shift circuit, second NMOS tube
Drain electrode connects the drain electrode of the 4th PMOS tube；
The source electrode of 4th PMOS tube connects the grid and work of the drain electrode of second PMOS tube, first PMOS tube
For the second output terminal of the level shift circuit；
The source electrode of first PMOS tube and the source electrode of second PMOS tube are all connected with second source line.
Optionally, the level shift circuit further includes third NMOS tube, the 5th PMOS tube and the 6th PMOS tube；
The grid of the third NMOS tube connects the grid of first NMOS tube, the source electrode connection of the third NMOS tube
First power supply line, the drain electrode of the third NMOS tube connect the drain electrode of the 6th PMOS tube；
The grid of 6th PMOS tube connects the grid of the third PMOS tube, the source electrode connection of the 6th PMOS tube
The drain electrode of 5th PMOS tube；
The grid of 5th PMOS tube connects the grid of first PMOS tube, the source electrode connection of the 5th PMOS tube
The second source line.
Optionally, the level shift circuit further includes phase inverter；
The input terminal of the phase inverter connects the first input end of the level shift circuit, the output end of the phase inverter
Connect the second input terminal of the level shift circuit.
Optionally, the voltage value of the bias voltage meets vdd-vcc-vthp < vb < vdd-vcc, wherein vb is institute
The voltage value of bias voltage is stated, vdd is the voltage value for the supply voltage that the second source line provides, and vcc is level shifting
The voltage value of the received high level signal of first input end of position circuit, vthp are the electricity of the threshold voltage of the third PMOS tube
Pressure value.
Optionally, it includes M pull-up PMOS tube, N number of pull-down NMOS pipe and biased electrical that the bias voltage, which provides unit,
Stream source, M and N are positive integer；
The source electrode of 1st pull-up PMOS tube connects the second source line, the source electrode connection of m-th of pull-up PMOS tube the
(m-1) grid of the drain electrode of a pull-up PMOS tube and (m-1) a pull-up PMOS tube, m-th pull up the drain electrode connection of PMOS tube
M-th pulls up the grid of PMOS tube, the grid of the drain electrode of the 1st pull-down NMOS pipe and the 1st pull-down NMOS pipe and as institute
It states bias voltage and the output end of unit is provided, the drain electrode of n-th of pull-down NMOS pipe connects the with the grid of n-th of pull-down NMOS pipe
(n-1) source electrode of a pull-down NMOS pipe, the source electrode of n-th pull-down NMOS pipe connects one end of the bias current sources, described inclined
The other end for setting current source connects first power supply line, 1 < m≤M, 1 < n≤N.
Optionally, the supply voltage that the second source line provides is higher than the supply voltage that first power supply line provides.
Optionally, first power supply line is ground wire.
Optionally, the first input end of the level shift circuit is suitable for receiving high level signal, the level shift electricity
Second input terminal on road is suitable for receiving low level signal, and the amplitude of the high level signal is less than what the second source line provided
Supply voltage.
Optionally, the first input end of the level shift circuit is suitable for receiving low level signal, the level shift electricity
Second input terminal on road is suitable for receiving high level signal, and the amplitude of the high level signal is less than what the second source line provided
Supply voltage.
Optionally, the amplitude of the high level signal is the supply voltage of low-voltage control circuit, the low level signal
Amplitude is the supply voltage that first power supply line provides.
Compared with prior art, the present invention having the following advantages and benefits:
Level shift circuit provided by the invention, by increasing by two high pressures on the basis of typical level shift circuit
PMOS tube and bias voltage provide unit, provide unit as the bias voltage and provide needed for two newly-increased PMOS tube of driving
Bias voltage limits the low level of two newly-increased PMOS source ends, that is, improves the grid electricity of original two high voltage PMOS pipes
Pressure controls the gate source voltage of original two high voltage PMOS pipes in low-tension supply voltage range, guarantees level shift circuit
Normal function.Since the gate source voltage of original two high voltage PMOS pipes and two newly-increased PMOS tube is all controlled in low tension
In the voltage range of source, thus low pressure grid oxygen technique can be used in all devices, increases additional thick grid oxygen when device being avoided to manufacture
Technique reduces production cost.Further, the bias voltage provides unit due to the presence of bias current sources, limits institute
The overall power for stating level shift circuit will not additionally increase when increasing the current drive capability of the level shift circuit
The power consumption of circuit.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings:
Fig. 1 is the circuit diagram of typical level shift circuit；
Fig. 2 is the circuit diagram of the level shift circuit of an embodiment of the present invention；
Fig. 3 is the circuit diagram of the level shift circuit of another embodiment of the present invention.
Specific embodiment
Just as described in the background art, level shift circuit shown in FIG. 1 at work, the high voltage PMOS pipe of conducting
Grid be pulled low to the low supply voltage that the first power supply line VSS is provided, the low power supply that the first power supply line VSS is provided
Voltage is usually 0V, thus the voltage difference between the grid and source electrode of the high voltage PMOS pipe be connected is very big, it is necessary to which use is thicker
Oxide layer as gate oxide.Based on this, the present invention provides a kind of level shift circuit, is set by effective biasing circuit
Meter, meets the gate source voltage restrictive condition of high voltage PMOS pipe, realizes the low pressure grid oxygen technological design of circuit.
To make the objectives, technical solutions, and advantages of the present invention clearer, below with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation for explaining only the invention, are not made
For limitation of the invention.
Embodiment 1
Fig. 2 is the circuit diagram of the level shift circuit of the present embodiment, and the level shift circuit includes that bias voltage provides
Unit 21, the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2, third PMOS tube P3 and
Four PMOS tube P4.
Specifically, the bias voltage provides unit 21 and is adapted to provide for bias voltage Vb, and the bias voltage Vb is for driving
Move the third PMOS tube P3 and the 4th PMOS tube P4.It should be noted that the specific voltage of the bias voltage Vb
Value can be configured according to actual circuit parameter, as long as it can ensure that driving the third PMOS tube P3 and the 4th PMOS
Pipe P4 conducting, to controlling the gate source voltage of the first PMOS tube P1 and the second PMOS tube P2 in low-tension supply voltage
In range.In the present embodiment, the voltage value of the bias voltage meets vdd-vcc-vthp < vb < vdd-vcc,
In, vb is the voltage value of the bias voltage, and vdd is the voltage value for the supply voltage that the second source line provides, vcc
For the voltage value of the received high level signal of first input end of the level shift circuit, vthp is the third PMOS tube
The voltage value of threshold voltage.
First input end V1, first NMOS of the grid of the first NMOS tube N1 as the level shift circuit
The source electrode of the source electrode of pipe N1 and the second NMOS tube N2 are all connected with the first power supply line VSS, the drain electrode of the first NMOS tube N1
Connect the drain electrode of the third PMOS tube P3.The first power supply line VSS is usually ground wire, and the supply voltage provided is 0V.
The grid of the third PMOS tube P3 connects the grid of the 4th PMOS tube P4 and is suitable for receiving the biased electrical
Vb is pressed, the source electrode of the third PMOS tube P3 connects the grid of the drain electrode of the first PMOS tube P1, the second PMOS tube P2
And the first output end VO as the level shift circuit.
Second input terminal VIB of the grid of the second NMOS tube N2 as the level shift circuit, described second
The drain electrode of NMOS tube N2 connects the drain electrode of the 4th PMOS tube P4.In level shift circuit work, described first is defeated
Enter to hold V1 received signal to control described in the first NMOS tube N1 conducting, the second input terminal VIB received signal control
Second NMOS tube N2 cut-off；End alternatively, the first input end V1 received signal controls the first NMOS tube N1, is described
Second input terminal VIB received signal controls the second NMOS tube N2 conducting.That is, the first input end V1 is received
Signal and the second input terminal VIB received signal can inversion signal each other, if the first input end V1 receive it is high
Level signal, then the second input terminal VIB receives low level signal；If the first input end V1 receives low level signal,
Then the second input terminal VIB receives high level signal.
The source electrode of the 4th PMOS tube P4 connects the grid of the drain electrode of the second PMOS tube P2, the first PMOS tube P1
Pole and second output terminal VOB as the level shift circuit.
The source electrode of the source electrode of the first PMOS tube P1 and the second PMOS tube P2 are all connected with second source line VDD, institute
The supply voltage for stating second source line VDD offer is higher than the supply voltage that the first power supply line VSS is provided.It needs to illustrate
It is that the specific voltage value for the supply voltage that the second source line VDD is provided drives energy according to needed for subsequent high-voltage driving circuit
Power determines.
The present embodiment also provides the bias voltage and provides a kind of physical circuit of unit 21, and the bias voltage provides single
Member 21 includes that M pull-up PMOS tube, N number of pull-down NMOS pipe and bias current sources Ib, M and N are positive integer.
Wherein, the source electrode of the 1st pull-up PMOS tube connects the second source line VDD, the source electrode of m-th of pull-up PMOS tube
The drain electrode of (m-1) a pull-up PMOS tube and the grid of (m-1) a pull-up PMOS tube are connected, m-th pulls up the leakage of PMOS tube
Pole connects the grid of the grid of m-th pull-up PMOS tube, the drain electrode of the 1st pull-down NMOS pipe and the 1st pull-down NMOS pipe simultaneously
The output end of unit 21 is provided as the bias voltage, the output end that the bias voltage provides unit 21 is described for exporting
Bias voltage Vb, the drain electrode of n-th of pull-down NMOS pipe connect (n-1) a pull-down NMOS with the grid of n-th of pull-down NMOS pipe
The source electrode of pipe, the source electrode of n-th pull-down NMOS pipe connect one end of the bias current sources Ib, and the bias current sources Ib's is another
One end connects the first power supply line VSS, 1 < m≤M, 1 < n≤N.
In the present embodiment, providing unit 21 with the bias voltage includes 3 pull-up PMOS tube, 1 pull-down NMOS pipe
And for the bias current sources Ib, the source electrode of the 1st pull-up PMOS tube P21 connects the second source line VDD, the 2nd
The source electrode of pull-up PMOS tube P22 connects draining for the 1st pull-up PMOS tube P21 and pulls up the grid of PMOS tube P21 with the 1st, and the 3rd
The source electrode of a pull-up PMOS tube P23 connects the drain electrode of the 2nd pull-up PMOS tube P22 and the grid of the 2nd pull-up PMOS tube P22,
3rd pull-up PMOS tube P23 drain electrode connection the 3rd pull-up PMOS tube P23 grid, pull-down NMOS pipe N21 drain electrode and
The grid of pull-down NMOS pipe N21 simultaneously provides the output end of unit 21 as the bias voltage, and the source electrode of pull-down NMOS pipe N21 connects
One end of the bias current sources Ib is connect, the other end of the bias current sources Ib connects the first power supply line VSS.
Further, since the first input end V1 received signal and the second input terminal VIB received signal are mutual
For inversion signal, thus the level shift circuit can also include phase inverter A1.The input terminal of the phase inverter A1 connects institute
First input end VI is stated, the output end of the phase inverter A1 connects the second input terminal VIB.By the phase inverter A1 to institute
It states first input end VI received signal and carries out reverse phase, the second input terminal VIB received signal can be obtained.
The working principle of the level shift circuit of the present embodiment is illustrated below:
When the first input end VI receives logic-low signal " 0 ", the second input terminal VIB receives logically high electricity
When ordinary mail number " 1 ", the first NMOS tube N1, the second PMOS tube P2 and third PMOS tube P3 cut-off, described the
Two NMOS tube N2, the first PMOS tube P1 and the 4th PMOS tube P4 conducting, the voltage quilt of the second output terminal VOB
It is pulled low to the source voltage of the 4th PMOS tube P4, the voltage of the first output end VO is pulled to the second source line
The high power supply voltage that VDD is provided；
When the first input end VI input logic low level signal " 1 ", the high electricity of the second input terminal VIB input logic
When ordinary mail number " 0 ", the first NMOS tube N1, the second PMOS tube P2 and third PMOS tube P3 conducting, described the
Two NMOS tube N2, the first PMOS tube P1 and the 4th PMOS tube P4 cut-off, the voltage quilt of the second output terminal VOB
The high power supply voltage provided to the second source line VDD is drawn high, the voltage of the first output end VO is pulled low to described the
The source voltage of three PMOS tube P3.
It should be noted that the amplitude of the high level signal and the amplitude of the low level signal according to actual needs into
Row setting, if guarantee the high level signal can control the first NMOS tube N1 or described second NMOS tube N2 conducting,
The low level signal can control the first NMOS tube N1 or described second NMOS tube N2 cut-off.In the present embodiment
In, the amplitude of the high level signal is the supply voltage of low-voltage control circuit, and the amplitude of the low level signal is described the
The supply voltage that one power supply line VSS is provided.
Level shift circuit provided in this embodiment, by increasing the third on the basis of typical level shift circuit
PMOS tube P3, the 4th PMOS tube P4 and the bias voltage provide unit 21, provide unit 21 by the bias voltage
Bias voltage Vb needed for driving the third PMOS tube P3 and the 4th PMOS tube P4 is provided, the third PMOS tube is limited
The low level of P3 and the 4th PMOS tube P4 source improve the grid of the first PMOS tube P1 and the second PMOS tube P2
Pole tension controls the gate source voltage of the first PMOS tube P1 and the second PMOS tube P2 in low-tension supply voltage range,
Guarantee the normal function of level shift circuit.Since the gate source voltage of all PMOS tube is all controlled in low-tension supply voltage range
It is interior, thus identical low pressure grid oxygen technique can be used in all devices, increases additional thick grid oxygen technique when device being avoided to manufacture,
Reduce production cost.
Embodiment 2
Fig. 3 is the circuit diagram of the level shift circuit of the present embodiment, compared with the embodiment of Fig. 2, the level shift electricity
Road further includes third NMOS tube N3, the 5th PMOS tube P5 and the 6th PMOS tube P6.
The grid of the third NMOS tube N3 connects the grid of the first NMOS tube N1, the source of the third NMOS tube N3
Pole connects the first power supply line VSS, and the drain electrode of the third NMOS tube N3 connects the drain electrode of the 6th PMOS tube P6.It is described
The grid of 6th PMOS tube P6 connects the grid of the third PMOS tube P3, the source electrode connection of the 6th PMOS tube P6 described the
The drain electrode of five PMOS tube P5.The grid of the 5th PMOS tube P5 connects the grid of the first PMOS tube P1, and the described 5th
The source electrode of PMOS tube P5 connects the second source line VDD.Level shift circuit provided in this embodiment, the third NMOS tube
N3, the 5th PMOS tube P5 and the 6th PMOS tube P6 constitute buffer circuit, and the drain electrode of the 5th PMOS tube P5 is made
For the output end of the buffer circuit.
The working principle of the level shift circuit of the present embodiment is illustrated below:
When the first input end VI receives logic-low signal " 0 ", the second input terminal VIB receives logically high electricity
When ordinary mail number " 1 ", the first NMOS tube N1, the third NMOS tube N3, the second PMOS tube P2, the third PMOS tube
P3 and the 6th PMOS tube P6 cut-off, the second NMOS tube N2, the first PMOS tube P1, the 4th PMOS tube P4
And the 5th PMOS tube P5 conducting, the voltage of the second output terminal VOB are pulled low to the source of the 4th PMOS tube P4
Pole tension, the voltage of the first output end VO are pulled to the high power supply voltage that the second source line VDD is provided, and described the
The drain voltage of five PMOS tube P5 is pulled to the high power supply voltage that the second source line VDD is provided；
When the first input end VI input logic low level signal " 1 ", the high electricity of the second input terminal VIB input logic
When ordinary mail number " 0 ", the first NMOS tube N1, the third NMOS tube N3, the second PMOS tube P2, the third PMOS tube
P3 and the 6th PMOS tube P6 conducting, the second NMOS tube N2, the first PMOS tube P1, the 4th PMOS tube P4
And the 5th PMOS tube P5 cut-off, the voltage of the second output terminal VOB are pulled to the second source line VDD and provide
High power supply voltage, the voltage of the first output end VO is pulled low to the source voltage of the third PMOS tube P3, described
The drain voltage of five PMOS tube P5 is pulled low to the source voltage of the 6th PMOS tube P6.
Level shift circuit provided in this embodiment can improve the level shift electricity by increasing the buffer circuit
The output signal on road, while the current drive capability of the level shift circuit can be increased.Also, since the bias voltage mentions
For the presence of unit 21, when increasing the current drive capability of the level shift circuit will not extra circuits power consumption.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of level shift circuit, which is characterized in that including bias voltage provide unit, the first NMOS tube, the second NMOS tube,
First PMOS tube, the second PMOS tube, third PMOS tube and the 4th PMOS tube；
The bias voltage provides unit and is adapted to provide for bias voltage；
First input end of the grid of first NMOS tube as the level shift circuit, the source electrode of first NMOS tube
It is all connected with the first power supply line with the source electrode of second NMOS tube, the drain electrode of first NMOS tube connects the third PMOS tube
Drain electrode；
The grid of the third PMOS tube connects the grid of the 4th PMOS tube and is suitable for receiving the bias voltage, and described the
The source electrode of three PMOS tube connects the drain electrode of first PMOS tube, the grid of second PMOS tube and as the level shift
First output end of circuit；
Second input terminal of the grid of second NMOS tube as the level shift circuit, the drain electrode of second NMOS tube
Connect the drain electrode of the 4th PMOS tube；
The source electrode of 4th PMOS tube connects the drain electrode of second PMOS tube, the grid of first PMOS tube and as institute
State the second output terminal of level shift circuit；
The source electrode of first PMOS tube and the source electrode of second PMOS tube are all connected with second source line.
2. level shift circuit according to claim 1, which is characterized in that further include third NMOS tube, the 5th PMOS tube
And the 6th PMOS tube；
The grid of the third NMOS tube connects the grid of first NMOS tube, described in the source electrode connection of the third NMOS tube
First power supply line, the drain electrode of the third NMOS tube connect the drain electrode of the 6th PMOS tube；
The grid of 6th PMOS tube connects the grid of the third PMOS tube, described in the source electrode connection of the 6th PMOS tube
The drain electrode of 5th PMOS tube；
The grid of 5th PMOS tube connects the grid of first PMOS tube, described in the source electrode connection of the 5th PMOS tube
Second source line.
3. level shift circuit according to claim 1 or 2, which is characterized in that further include phase inverter；
The input terminal of the phase inverter connects the first input end of the level shift circuit, the output end connection of the phase inverter
Second input terminal of the level shift circuit.
4. level shift circuit according to claim 1 or 2, which is characterized in that the voltage value of the bias voltage meets
Vdd-vcc-vthp < vb < vdd-vcc, wherein vb is the voltage value of the bias voltage, and vdd is that the second source line mentions
The voltage value of the supply voltage of confession, vcc are the voltage of the received high level signal of first input end of the level shift circuit
Value, vthp are the voltage value of the threshold voltage of the third PMOS tube.
5. level shift circuit according to claim 1 or 2, which is characterized in that it includes M that the bias voltage, which provides unit,
A pull-up PMOS tube, N number of pull-down NMOS pipe and bias current sources, M and N are positive integer；
The source electrode of 1st pull-up PMOS tube connects the second source line, and the source electrode of m-th of pull-up PMOS tube connects (m-1)
The drain electrode of a pull-up PMOS tube and the grid of (m-1) a pull-up PMOS tube, the drain electrode that m-th pulls up PMOS tube connect m-th
Pull up the grid of PMOS tube, the grid of the drain electrode of the 1st pull-down NMOS pipe and the 1st pull-down NMOS pipe and as the biasing
The drain electrode of the output end of voltage providing unit, n-th of pull-down NMOS pipe connects (n-1) with the grid of n-th of pull-down NMOS pipe
The source electrode of a pull-down NMOS pipe, the source electrode of n-th pull-down NMOS pipe connect one end of the bias current sources, the bias current
The other end in source connects first power supply line, 1 < m≤M, 1 < n≤N.
6. level shift circuit according to claim 1 or 2, which is characterized in that the power supply that the second source line provides
Voltage is higher than the supply voltage that first power supply line provides.
7. level shift circuit according to claim 6, which is characterized in that first power supply line is ground wire.
8. level shift circuit according to claim 1, which is characterized in that the first input end of the level shift circuit
Suitable for receiving high level signal, the second input terminal of the level shift circuit is suitable for receiving low level signal, the high level
The amplitude of signal is less than the supply voltage that the second source line provides.
9. level shift circuit according to claim 1, which is characterized in that the first input end of the level shift circuit
Suitable for receiving low level signal, the second input terminal of the level shift circuit is suitable for receiving high level signal, the high level
The amplitude of signal is less than the supply voltage that the second source line provides.
10. level shift circuit according to claim 8 or claim 9, which is characterized in that the amplitude of the high level signal is low
The supply voltage of control circuit is pressed, the amplitude of the low level signal is the supply voltage that first power supply line provides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910034187.XA CN109818607A (en) | 2019-01-15 | 2019-01-15 | Level shift circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910034187.XA CN109818607A (en) | 2019-01-15 | 2019-01-15 | Level shift circuit |
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| Publication Number | Publication Date |
|---|---|
| CN109818607A true CN109818607A (en) | 2019-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910034187.XA Pending CN109818607A (en) | 2019-01-15 | 2019-01-15 | Level shift circuit |
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| Country | Link |
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| CN (1) | CN109818607A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388499B1 (en) * | 2001-01-19 | 2002-05-14 | Integrated Device Technology, Inc. | Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology |
| CN102437730A (en) * | 2011-12-24 | 2012-05-02 | 西安启芯微电子有限公司 | Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
| CN103684412A (en) * | 2012-09-05 | 2014-03-26 | Ls产电株式会社 | Level shift device |
| CN107735740A (en) * | 2015-08-31 | 2018-02-23 | 赛普拉斯半导体公司 | Biasing circuit for the level shifter with isolation |
-
2019
- 2019-01-15 CN CN201910034187.XA patent/CN109818607A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388499B1 (en) * | 2001-01-19 | 2002-05-14 | Integrated Device Technology, Inc. | Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology |
| CN102437730A (en) * | 2011-12-24 | 2012-05-02 | 西安启芯微电子有限公司 | Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter |
| CN103684412A (en) * | 2012-09-05 | 2014-03-26 | Ls产电株式会社 | Level shift device |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
| CN107735740A (en) * | 2015-08-31 | 2018-02-23 | 赛普拉斯半导体公司 | Biasing circuit for the level shifter with isolation |
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Application publication date: 20190528 |
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