CN102437730A - Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter - Google Patents

Abstract

The invention discloses an anti-ringing circuit applied to a high-voltage boosting type DC-DC (Direct Current to Direct Current) converter, mainly solving the problem that the anti-ringing circuit in the prior art cannot work under high-voltage conditions. The circuit comprises a control circuit, a level shift circuit, a high-voltage PMOS (P-channel Metal Oxide Semiconductor) tube M3 and a high-voltage PMOS tube M4, wherein source electrodes of the high-voltage PMOS tubes M3 and M4 are connected with each other; an output voltage VH is connected with the input end of the level shift circuit; drain electrodes of the high-voltage PMOS tubes M3 and M4 are respectively connected with two ends of an inductor; output signals of the control circuit are connected with grid electrodes of the high-voltage PMOS tubes M3 and M4, so as to control the conduction and the stopping of the M3 and the M4 and eliminate ringing; and the input end of the control circuit is connected with the level shift circuit, so as to assure that voltage differences between the source electrodes and the grid electrodes of the high-voltage PMOS tubes M3 and M4 are not more than 5 V and prevent the high-voltage PMOS tubes M3 and M4 from being punctured due to the overlarge voltage differences between the source electrodes and the grid electrodes. The anti-ringing circuit provided by the invention can work under the high-voltage conditions so that the ringing phenomenon can be eliminated, the noises are reduced, the electromagnetic interferences on the system are reduced, and the performance of the DC-DC converter is improved; and therefore, the anti-ringing circuit can be applied to the high-voltage boosting type DC-DC converter.

Description

Be applied to the antivibration bell circuit in the high voltage step-up type DC-DC transducer

Technical field

The invention belongs to the electronic circuit technology field, relate to analog integrated circuit, particularly a kind of antivibration bell circuit that is applied in the high voltage step-up type DC-DC transducer.

Background technology

The DC-DC converter can keep very high efficient in very wide input and output voltage scope, be applied in widely in all kinds of portable type electronic products.But because the DC-DC converter is operated on off state; Bigger output noise maybe be to some sensitive circuits; Impact such as radio circuit, when especially DC-DC is operated in the inductive current DCM, when switching tube is closed; The LC loop that is made up of inductance and parasitic capacitance can produce the serious higher-order of oscillation, forms ring.The existence of ring can produce noise and electromagnetic interference problem, influences the operate as normal of system.Therefore be necessary to adopt special antivibration bell circuit to carry out the ring decay.Wherein the most frequently used method is the purpose that the perhaps parallelly connected small resistor of inductance shorted on both ends is reached the antivibration bell.

Existing antivibration bell circuit is mainly used in the boosting type converter of some buck DC-DC transducers or low pressure, and is as shown in Figure 1, and wherein antivibration bell circuit mainly comprises control circuit, and PMOS manages M ₃And PMOS pipe M ₄In the time of antivibration bell circuit working, control circuit output signal V _CBe zero level, make PMOS pipe M ₃With PMOS pipe M ₄Conducting, and then make inductance two terminal shortcircuits, reach the purpose of antivibration bell; When antivibration bell circuit is out-of-work, control circuit output signal V _CVoltage equals PMOS pipe M ₃With PMOS pipe M ₄Source voltage, make PMOS pipe M ₃With PMOS pipe M ₄End, do not influence the operate as normal of DC-DC transducer.

PMOS pipe M among Fig. 1 in the antivibration bell circuit ₃With PMOS pipe M ₄What adopt is low pressure PMOS pipe, can only bear the pressure reduction of 5V between the source electrode of low pressure PMOS pipe and the drain electrode, also can only bear the pressure reduction of 5V between source electrode and the grid, therefore can only be applied in the DC-DC transducer that input and output are low pressure.But, even PMOS is managed M ₃With PMOS pipe M ₄Change the high voltage PMOS pipe into, such structure can not be applied in the high voltage step-up type DC-DC converter.High voltage can be born because normally used high voltage PMOS pipe has only between source electrode and the drain electrode, and the pressure reduction of 5V can only be born between source electrode and the grid.In the time of antivibration bell circuit working, PMOS manages M ₃With PMOS pipe M ₄Grid be 0 level, and PMOS pipe M ₃With PMOS pipe M ₄Source level after the conducting is a high pressure but, thereby makes source electrode and the pressure reduction between the grid of PMOS pipe greater than 5V, causes PMOS pipe over-voltage breakdown, damages circuit.

Summary of the invention

The objective of the invention is to above-mentioned deficiency of the prior art; A kind of antivibration bell circuit that is applied in the high voltage step-up type DC-DC transducer is proposed; During so that work under the situation of step-up DC-DC transducer high pressure, can eliminate ringing, reduce noise; Reduction improves the performance of DC-DC transducer to the electromagnetic interference of system.

For realizing above-mentioned purpose, the antivibration bell circuit that is used for high voltage step-up type DC-DC transducer of the present invention comprises that control circuit, PMOS manage M ₃With PMOS pipe M ₄, this PMOS pipe M ₃And M ₄Source electrode link to each other output voltage V _HBe connected to the input of level shift circuit, drain electrode connects the two ends of inductance respectively; The output signal V of control circuit _CBe connected to high voltage PMOS pipe M ₃And M ₄Grid, be used to control M ₃And M ₄Conducting with end, eliminate ring; It is characterized in that: PMOS manages M ₃With PMOS pipe M ₄All adopt between source electrode and drain electrode withstand voltage greater than the high voltage PMOS pipe of 12V; The input of control circuit is connected with level shift circuit, is used to guarantee the output signal V of control circuit _CThe pressure reduction that logic just changes is no more than 5V, prevents high voltage PMOS pipe M ₃And M ₄Puncture because of the pressure reduction of source electrode and grid is excessive;

Described level shift circuit comprises that withstand voltage is greater than the high pressure NMOS pipe M of 12V between bias current source circuit, drain electrode and source electrode ₅, two high voltage PMOS pipe M ₈, M ₉All manage M with two each utmost point withstand voltages less than the low pressure PMOS of 5V ₆, M ₇This high pressure NMOS pipe M ₅Drain electrode connect the output voltage V of DC-DC _OUT, grid meets high voltage PMOS pipe M ₃And M ₄The output voltage V of source electrode _H, source electrode and low pressure PMOS pipe M ₆, M ₇Be connected to high voltage PMOS pipe M after the series connection ₈Source electrode; High voltage PMOS pipe M ₈Grid and high voltage PMOS pipe M ₉Grid connect high voltage PMOS pipe M ₉Drain electrode connecting to neutral level, the source electrode output voltage V _L, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈Drain electrode and high voltage PMOS pipe M ₉Source electrode link to each other, for these two high voltage PMOS pipes provide constant current.

Described bias current source circuit comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all less than 5V low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅With two low pressure PMOS pipe M ₁₆, M ₁₇

Said high pressure NMOS pipe M ₁₀With low pressure NMOS pipe M ₁₃Be connected in series high pressure NMOS pipe M ₁₁With low pressure NMOS pipe M ₁₄Be connected in series; High pressure NMOS pipe M ₁₂With low pressure NMOS pipe M ₁₅Be connected in series; Three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂Grid link to each other three low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅Grid link to each other, source electrode connecting to neutral level constitutes common-source common-gate current mirror; High pressure NMOS pipe M ₁₂Drain electrode be connected to high voltage PMOS pipe M ₈Drain electrode, be high voltage PMOS pipe M ₈Constant current I is provided ₂

Said high voltage PMOS pipe M ₁₈With low pressure PMOS pipe M ₁₆Be connected in series high voltage PMOS pipe M ₁₉With low pressure PMOS pipe M ₁₇Be connected in series; High voltage PMOS pipe M ₁₈With M ₁₉Grid link to each other, low pressure PMOS manages M ₁₆And M ₁₇Grid link to each other, source electrode connects the output voltage V of DC-DC _OUT, constitute common-source common-gate current mirror; High voltage PMOS pipe M ₁₈Drain electrode be connected to high pressure NMOS pipe M ₁₁Drain electrode, high voltage PMOS pipe M ₁₉Drain electrode be connected to high voltage PMOS pipe M ₉Source electrode, be high voltage PMOS pipe M ₉Constant current I is provided ₃

Described control circuit comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃And M ₄Source voltage V _HBetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃And M ₄Grid.

Described comparator comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃With current source I ₄This high pressure NMOS pipe M ₂₀, M ₂₁As the input of this comparator to pipe, high pressure NMOS pipe M ₂₀Grid meet input control signal K, high pressure NMOS pipe M ₂₁Grid meet the output signal XK of inverter INV; Current source I ₄One termination zero level, the other end are connected to this high pressure NMOS pipe M ₂₀And M ₂₁Source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂And M ₂₃Grid link to each other, source electrode meets high voltage PMOS pipe M ₃And M ₄Source voltage V _H, form the active electric current mirror, as the load of comparator; Low pressure PMOS manages M ₂₂Drain electrode be connected to high pressure NMOS pipe M ₂₀Drain electrode, low pressure PMOS manages M ₂₃Drain electrode be connected to high pressure NMOS pipe M ₂₁Drain electrode, as the output of comparator.

Described clamp circuit comprises three low pressure PMOS pipe M ₂₄, M ₂₅And M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄Source voltage V _HAnd between the output of comparator, their grid is connected with separately drain electrode respectively, constitutes diode, and the comparator output voltage is carried out clamp.

Described output circuit comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉With 2 low pressure NMOS pipe M ₂₈, M ₃₀This low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Grid link to each other and be connected to the output of comparator, low pressure PMOS manages M ₂₇Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₂₈Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Drain electrode link to each other, and be connected to low pressure PMOS pipe M ₂₉With low pressure NMOS pipe M ₃₀Grid; Low pressure PMOS manages M ₂₉Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₃₀Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₉With low pressure NMOS pipe M ₃₀Drain electrode link to each other the voltage V of output _CBe connected to high voltage PMOS pipe M ₃With high voltage PMOS pipe M ₄Grid.

The present invention compared with prior art has the following advantages:

The present invention is owing to adopted the high voltage PMOS pipe to replace low pressure PMOS pipe; And the input at control circuit is connected with level shift circuit, and the pressure reduction that can guarantee high voltage PMOS tube grid and source electrode can work antivibration bell circuit in its withstand voltage under the condition of high pressure; Eliminate the ringing of high voltage step-up type DC-DC transducer; Reduced noise, reduced electromagnetic interference, improved the performance of DC-DC transducer system.

Description of drawings

Fig. 1 is the step-up DC-DC commutator principle figure that has traditional antivibration bell circuit;

Fig. 2 is the step-up DC-DC commutator principle figure that has antivibration bell circuit of the present invention;

Fig. 3 is level shift circuit structure chart among the present invention;

Fig. 4 is control circuit structure chart among the present invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is further described.

With reference to figure 2, high voltage step-up type DC-DC transducer mainly comprises antivibration bell circuit of the present invention, high pressure NMOS pipe M ₁, high voltage PMOS pipe M ₂, inductance L and output capacitance C; The one termination input power supply VIN of inductance L, the other end is connected to high pressure NMOS pipe M ₁With high voltage PMOS pipe M ₂Drain electrode, high pressure NMOS pipe M ₁Grid meet drive signal VC1, source electrode connecting to neutral level; High voltage PMOS pipe M ₂Grid meet drive signal VC2, source electrode connects the end of output capacitance C, as the output of step-up DC-DC.With reference to the maximum voltage value in the DC-DC converter application, confirm the withstand voltage of high voltage PMOS pipe, withstand voltage is greater than 12V usually.

Said antivibration bell circuit of the present invention comprises control circuit, level shift circuit, high voltage PMOS pipe M ₃And M ₄D1 and D2 are respectively high voltage PMOS pipe M ₃And M ₄Parasitic diode; This PMOS pipe M ₃And M ₄Source electrode link to each other output voltage V _HBe connected to the input of level shift circuit, drain electrode connects the two ends of inductance L respectively; The output signal V of this control circuit _CBe connected to high voltage PMOS pipe M ₃And M ₄Grid, control MX and M ₄Conducting with end, eliminate ring; This level shift circuit is provided with two inputs and an output, and first input end meets high voltage PMOS pipe M ₃And M ₄Source voltage V _H, the output voltage V of the second input termination DC-DC transducer _OUT, the output voltage V of output _LBe connected to control circuit, so that the output signal V of control circuit to be provided _CLogic low, guarantee the output signal V of control circuit _CThe pressure reduction that logic just changes is no more than 5V, prevents high voltage PMOS pipe M ₃And M ₄Puncture because of the pressure reduction of source electrode and grid is excessive.

With reference to figure 3, described level shift circuit comprises bias current source circuit, high pressure NMOS pipe M ₅, two high voltage PMOS pipe M ₈, M ₉All manage M with two each utmost point withstand voltages less than the low pressure PMOS of 5V ₆, M ₇This high pressure NMOS pipe M ₅Drain electrode connect the output voltage V of DC-DC _OUT, grid meets high voltage PMOS pipe M ₃And M ₄The output voltage V of source electrode _H, source electrode and low pressure PMOS pipe M ₆, M ₇Be connected to high voltage PMOS pipe M after the series connection ₈Source electrode; High voltage PMOS pipe M ₈Grid and high voltage PMOS pipe M ₉Grid connect high voltage PMOS pipe M ₉Drain electrode connecting to neutral level, the source electrode output voltage V _L, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈Drain electrode and high voltage PMOS pipe M ₉Source electrode link to each other, for these two high voltage PMOS pipes provide constant current.The level shift circuit output voltage V _LFor:

V _L＝V _H-V _GS5-V _SG6-V _SG7-V _SG8+V _SG9 (1)

Wherein, V _GS5Be high pressure NMOS pipe M ₅Grid-source voltage, V _SG6Be low pressure PMOS pipe M ₆Source electrode-grid voltage, V _SG7Be low pressure PMOS pipe M ₇Source electrode-grid voltage, V _SG8Be high voltage PMOS pipe M ₈Source electrode-grid voltage, V _SG9Be high voltage PMOS pipe M ₉Source electrode-grid voltage.

Said bias current source circuit comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all managed M less than the low pressure NMOS of 5V ₁₃, M ₁₄, M ₁₅With two low pressure PMOS pipe M ₁₆, M ₁₇

High pressure NMOS pipe M ₁₀With low pressure NMOS pipe M ₁₃Be connected in series high pressure NMOS pipe M ₁₁With low pressure NMOS pipe M ₁₄Be connected in series; High pressure NMOS pipe M ₁₂With low pressure NMOS pipe M ₁₅Be connected in series three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂Grid link to each other, the grid of three low pressure NMOS pipes links to each other, source electrode connecting to neutral level constitutes common-source common-gate current mirror; Current source I ₁Be connected to high pressure NMOS pipe M behind the series resistance R ₁₀Drain electrode, high pressure NMOS pipe M ₁₂Drain electrode be connected to high voltage PMOS pipe M ₈Drain electrode, be high voltage PMOS pipe M ₈Constant current I is provided ₂:

$I_2\≈\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}\frac{W_8}{L_8}{(V_{\mathrm{SG}8}-V_{\mathrm{TH}8})}^2---\left(2\right)$

Wherein, μ _PBe carrier mobility, C _OXBe the gate oxide electric capacity of unit are, V _TH8Be high voltage PMOS pipe M ₈Threshold voltage, L ₈And W ₈Be respectively high voltage PMOS pipe M ₈Channel length and width.

High voltage PMOS pipe M ₁₈With low pressure PMOS pipe M ₁₆Be connected in series high voltage PMOS pipe M ₁₉With low pressure PMOS pipe M ₁₇Be connected in series; High voltage PMOS pipe M ₁₈With M ₁₉Grid link to each other, low pressure PMOS manages M ₁₆And M ₁₇Grid link to each other, source electrode connects the output voltage V of DC-DC _OUT, constitute common-source common-gate current mirror; High voltage PMOS pipe M ₁₈Drain electrode be connected to high pressure NMOS pipe M ₁₁Drain electrode, high voltage PMOS pipe M ₁₉Drain electrode be connected to high voltage PMOS pipe M ₉Source electrode, be high voltage PMOS pipe M ₉Constant current I is provided ₃:

$I_3\≈\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}\frac{W_9}{L_9}{(V_{\mathrm{SG}9}-V_{\mathrm{TH}9})}^2---\left(3\right)$

Wherein, V _TH9Be high voltage PMOS pipe M ₉Threshold voltage, L ₉And W ₉Be respectively high voltage PMOS pipe M ₉Channel length and width.

Low pressure NMOS manages M ₁₄And M ₁₅Breadth length ratio identical, low pressure PMOS manages M ₁₆And M ₁₇Breadth length ratio identical, thereby make image current I ₂And I ₃Be worth identical.Because high voltage PMOS pipe M ₈And M ₉Be complementary, the length of raceway groove is identical with width, so their threshold voltage V _TH8And V _TH9Also identical.Can get according to formula (2) and formula (3):

V _SG8＝V _SG9 (4)

With formula (4) substitution formula (1), can obtain the level shift circuit output voltage V _L:

V _L≈V _H-V _GS5-V _SG6-V _SG7 (5)

Electric current I is set ₂Value, make V _GS5+ V _SG6+ V _SG7Less than 5V, i.e. level shift circuit output voltage V _LWith high voltage PMOS pipe M ₃, M ₄Source voltage V _HPressure reduction be no more than 5V; Again because high pressure NMOS pipe M5 and low pressure PMOS pipe M ₆, M ₇All be in conducting state, therefore have

3V _TH＜V _GS5+V _SG6+V _SG7＜5 (6)

V wherein _THBe the threshold voltage of metal-oxide-semiconductor conducting.

With reference to figure 4, described control circuit comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃And M ₄Source voltage V _HBetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃And M ₄Grid.

Described comparator comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃With current source I ₄This high pressure NMOS pipe M ₂₀, M ₂₁As the input of this comparator to pipe, high pressure NMOS pipe M ₂₀Grid meet input control signal K, high pressure NMOS pipe M ₂₁Grid meet the output signal XK of inverter INV; Current source I ₄One termination zero level, the other end are connected to this high pressure NMOS pipe M ₂₀And M ₂₁Source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂And M ₂₃Grid link to each other, source electrode meets high voltage PMOS pipe M ₃And M ₄Source voltage V _H, form the active electric current mirror, as the load of comparator; Low pressure PMOS manages M ₂₂Drain electrode be connected to high pressure NMOS pipe M ₂₀Drain electrode, low pressure PMOS manages M ₂₃Drain electrode be connected to high pressure NMOS pipe M ₂₁Drain electrode, as the output of comparator.

Described output circuit comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉With 2 low pressure NMOS pipe M ₂₈, M ₃₀This low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Grid link to each other and be connected to the output of comparator, low pressure PMOS manages M ₂₇Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₂₈Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Drain electrode link to each other, and be connected to low pressure PMOS pipe M ₂₉With low pressure NMOS pipe M ₃₀Grid; Low pressure PMOS manages M ₂₉Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₃₀Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₉With low pressure NMOS pipe M ₃₀Drain electrode link to each other the voltage V of output _CBe connected to the grid of high voltage PMOS pipe M3 and high voltage PMOS pipe M4.

When control signal K was zero level, the output signal XK of inverter INV was high level VDD, tail current I ₄High pressure NMOS pipe M all flows through ₂₁, the comparator output voltage reduces, and makes low pressure PMOS pipe M ₂₇With low pressure NMOS pipe M ₃₀Conducting, the output signal V of control circuit _CVoltage equal the output voltage V of level shift circuit _LWhen control signal K was high level VDD, the output signal XK of inverter INV was a zero level, tail current I ₄High pressure NMOS pipe M all flows through ₂₀, the comparator output voltage rises, and makes low pressure PMOS pipe M ₂₉With low pressure NMOS pipe M ₂₈Conducting, the output signal V of control circuit _CVoltage equal high voltage PMOS pipe M ₃And M ₄Source voltage V _H

Because the output of comparator is directly connected to low pressure PMOS pipe M ₂₇Grid, and low pressure PMOS pipe M ₂₇Source electrode meet high voltage PMOS pipe M ₃, M ₄Source voltage V _H, for preventing low pressure PMOS pipe M ₂₇Source electrode-grid pressure reduction excessive, and introduced clamp circuit.Described clamp circuit comprises three low pressure PMOS pipe M ₂₄, M ₂₅And M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄Source voltage V _HAnd between the output of comparator, their grid is connected with separately drain electrode respectively, constitutes diode, and clamp is carried out in the output of comparator, prevents low pressure PMOS pipe M ₂₇Grid voltage low excessively.

Operation principle of the present invention is following:

If step-up DC-DC transducer is operated in the inductive current DCM, high pressure NMOS pipe M ₁With high voltage PMOS pipe M ₂The switch alternate conduction, as long as two pipes do not end simultaneously, ring can not take place, the input signal K of antivibration bell circuit is a high level, the output signal V of control circuit _CVoltage equal high voltage PMOS pipe M ₃, M ₄Source voltage V _H, control signal V _CBe connected to high voltage PMOS pipe M ₃, M ₄Grid, so high voltage PMOS pipe M ₃, M ₄Source electrode-grid voltage equate that pressure reduction is 0, high voltage PMOS pipe M ₃, M ₄End two pipe source voltage terminal V _HThe voltage higher value that equals the inductance L two ends deducts the pressure drop on the diode, and because the anti-connection partially of diode, path thoroughly turn-offs, and does not influence the operate as normal of DC-DC.

If high pressure NMOS pipe M ₁With high voltage PMOS pipe M ₂When ending simultaneously, the input signal K of antivibration bell circuit is a zero level, the output signal V of control circuit _CVoltage equal the output voltage V of level shift circuit _L, can know voltage V according to the analysis in the level shift circuit _LWith high voltage PMOS pipe M ₃, M ₄Source voltage V _HDifference V _GS5+ V _SG6+ V _SG7Greater than 3V _TH, surpassed high voltage PMOS pipe M ₃And M ₄On state threshold voltage, make high voltage PMOS pipe M ₃And M ₄Conducting makes inductance L two terminal shortcircuits, has destroyed the LC loop that ring forms, and has eliminated ringing.

High voltage PMOS pipe M ₃And M ₄During conducting, can know the output voltage V of level shift circuit according to the operation principle of above-mentioned level shift circuit _LFollow high voltage PMOS pipe M ₃, M ₄Source voltage change, make high voltage PMOS pipe M ₃, M ₄Source electrode-grid pressure reduction V _GS5+ V _SG6+ V _SG7Maintenance is in high-voltage tube source electrode-gate withstand voltage value scope, thereby can prevents high voltage PMOS pipe M less than 5V ₃And M ₄Because of the overvoltage punch through damage.

Below only be a preferred example of the present invention, do not constitute, obviously under design of the present invention, can carry out different changes and improvement, but these are all at the row of protection of the present invention its circuit to any restriction of the present invention.

Claims (6)

1. an antivibration bell circuit that is applied in the high voltage step-up type DC-DC transducer comprises that control circuit, PMOS manage M ₃With PMOS pipe M ₄, this PMOS pipe M ₃And M ₄Source electrode link to each other output voltage V _HBe connected to the input of level shift circuit, drain electrode connects the two ends of inductance respectively; The output signal V of control circuit _CBe connected to high voltage PMOS pipe M ₃And M ₄Grid, be used to control M ₃And M ₄Conducting with end, eliminate ring; It is characterized in that: PMOS manages M ₃With PMOS pipe M ₄All adopt between source electrode and drain electrode withstand voltage greater than the high voltage PMOS pipe of 12V; The input of control circuit is connected with level shift circuit, is used to guarantee the output signal V of control circuit _CThe pressure reduction that logic just changes is no more than 5V, prevents high voltage PMOS pipe M ₃And M ₄Puncture because of the pressure reduction of source electrode and grid is excessive;

Described level shift circuit comprises that withstand voltage is greater than the high pressure NMOS pipe M of 12V between bias current source circuit, drain electrode and source electrode ₅, two high voltage PMOS pipe M ₈, M ₉All manage M with two each utmost point withstand voltages less than the low pressure PMOS of 5V ₆, M ₇This high pressure NMOS pipe M ₅Drain electrode connect the output voltage V of DC-DC _OUT, grid meets high voltage PMOS pipe M ₃And M ₄The output voltage V of source electrode _H, source electrode and low pressure PMOS pipe M ₆, M ₇Be connected to high voltage PMOS pipe M after the series connection ₈Source electrode; High voltage PMOS pipe M ₈Grid and high voltage PMOS pipe M ₉Grid connect high voltage PMOS pipe M ₉Drain electrode connecting to neutral level, the source electrode output voltage V _L, be connected to control circuit; This bias current source circuit has two outputs, respectively with high voltage PMOS pipe M ₈Drain electrode and high voltage PMOS pipe M ₉Source electrode link to each other, for these two high voltage PMOS pipes provide constant current.

2. antivibration bell circuit according to claim 1 is characterized in that described bias current source circuit, comprises current source I ₁, resistance R, three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂, two high voltage PMOS pipe M ₁₈, M ₁₉, three each utmost point withstand voltages are all less than 5V low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅With two low pressure PMOS pipe M ₁₆, M ₁₇

Said high pressure NMOS pipe M ₁₀With low pressure NMOS pipe M ₁₃Be connected in series high pressure NMOS pipe M ₁₁With low pressure NMOS pipe M ₁₄Be connected in series; High pressure NMOS pipe M ₁₂With low pressure NMOS pipe M ₁₅Be connected in series; Three high pressure NMOS pipe M ₁₀, M ₁₁, M ₁₂Grid link to each other three low pressure NMOS pipe M ₁₃, M ₁₄, M ₁₅Grid link to each other, source electrode connecting to neutral level constitutes common-source common-gate current mirror; High pressure NMOS pipe M ₁₂Drain electrode be connected to high voltage PMOS pipe M ₈Drain electrode, be high voltage PMOS pipe M ₈Constant current I is provided ₂

Said high voltage PMOS pipe M ₁₈With low pressure PMOS pipe M ₁₆Be connected in series high voltage PMOS pipe M ₁₉With low pressure PMOS pipe M ₁₇Be connected in series; High voltage PMOS pipe M ₁₈With M ₁₉Grid link to each other, low pressure PMOS manages M ₁₆And M ₁₇Grid link to each other, source electrode connects the output voltage V of DC-DC _OUT, constitute common-source common-gate current mirror; High voltage PMOS pipe M ₁₈Drain electrode be connected to high pressure NMOS pipe M ₁₁Drain electrode, high voltage PMOS pipe M ₁₉Drain electrode be connected to high voltage PMOS pipe M ₉Source electrode, be high voltage PMOS pipe M ₉Constant current I is provided ₃

3. antivibration bell circuit according to claim 1 is characterized in that described control circuit, comprises inverter INV, comparator, clamp circuit and output circuit; The input of inverter INV is connected with the positive input of comparator, and meets control signal K, and the output signal XK of inverter INV is connected to the reverse input end of comparator; The output of comparator and high voltage PMOS pipe M ₃And M ₄Source voltage V _HBetween be connected with clamp circuit; The input of output circuit is connected with the output of comparator, and output is connected to high voltage PMOS pipe M ₃And M ₄Grid.

4. antivibration bell circuit according to claim 3 is characterized in that described comparator, comprises two high pressure NMOS pipe M ₂₀, M ₂₁, two low pressure PMOS pipe M ₂₂, M ₂₃With current source I ₄This high pressure NMOS pipe M ₂₀, M ₂₁As the input of this comparator to pipe, high pressure NMOS pipe M ₂₀Grid meet input control signal K, high pressure NMOS pipe M ₂₁Grid meet the output signal XK of inverter INV; Current source I ₄One termination zero level, the other end are connected to this high pressure NMOS pipe M ₂₀And M ₂₁Source electrode, for comparator provides tail current; Low pressure PMOS manages M ₂₂And M ₂₃Grid link to each other, source electrode meets high voltage PMOS pipe M ₃And M ₄Source voltage V _H, form the active electric current mirror, as the load of comparator; Low pressure PMOS manages M ₂₂Drain electrode be connected to high pressure NMOS pipe M ₂₀Drain electrode, low pressure PMOS manages M ₂₃Drain electrode be connected to high pressure NMOS pipe M ₂₁Drain electrode, as the output of comparator.

5. antivibration bell circuit according to claim 3 is characterized in that described clamp circuit, comprises three low pressure PMOS pipe M ₂₄, M ₂₅And M ₂₆, these three low pressure PMOS pipes are connected in series in high voltage PMOS pipe M ₃, M ₄Source voltage V _HAnd between the output of comparator, their grid is connected with separately drain electrode respectively, constitutes diode, and the comparator output voltage is carried out clamp.

6. antivibration bell circuit according to claim 3 is characterized in that described output circuit, comprises 2 low pressure PMOS pipe M ₂₇, M ₂₉With 2 low pressure NMOS pipe M ₂₈, M ₃₀This low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Grid link to each other and be connected to the output of comparator, low pressure PMOS manages M ₂₇Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₂₈Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₇With low pressure NMOS pipe M ₂₈Drain electrode link to each other, and be connected to low pressure PMOS pipe M ₂₉With low pressure NMOS pipe M ₃₀Grid; Low pressure PMOS manages M ₂₉Source electrode meet high voltage PMOS pipe M ₃And M ₄Source voltage V _H, low pressure NMOS manages M ₃₀Source electrode connect the output voltage V of level shift circuit _L, low pressure PMOS manages M ₂₉With low pressure NMOS pipe M ₃₀Drain electrode link to each other the voltage V of output _CBe connected to high voltage PMOS pipe M ₃With high voltage PMOS pipe M ₄Grid.

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