CN109817701B - Emitter structure of heterojunction bipolar transistor and thinning method of emitter - Google Patents
Emitter structure of heterojunction bipolar transistor and thinning method of emitter Download PDFInfo
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- CN109817701B CN109817701B CN201811589623.1A CN201811589623A CN109817701B CN 109817701 B CN109817701 B CN 109817701B CN 201811589623 A CN201811589623 A CN 201811589623A CN 109817701 B CN109817701 B CN 109817701B
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Abstract
The invention provides a thinning method of an emitter of a heterojunction bipolar transistor, wherein a first etching stop layer and a second etching stop layer which are stacked from top to bottom are arranged between an emitter layer and an emitter cap layer; the selective etching ratios of the first etching stop layer and the second etching stop layer to different etching solutions are different; the thinning process comprises the steps of: 1) etching the emitter cap layer after depositing the emitter metal on the emitter cap layer; 2) etching the first etch stop layer without affecting the second etch stop layer; 3) etching the second etch stop layer and the emitter cap layer, wherein the first etch stop layer is not affected; 4) etching the first etch stop layer and the emitter layer without affecting the second etch stop layer; 5) and depositing a base electrode metal on the base electrode layer. Therefore, the emitter thinning process is completed without adding a photoresist or dielectric layer (dielectric) material to make a thinning etching mask.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor transistor.
Background
In the existing emitter thinning technology, a photoetching and etching procedure is utilized to etch an emitter layer when the area size of the emitter is defined, and in the emitter etching process, if the materials of the emitter layer and a cap layer are similar and are not easy to be identified by etching liquid, the thickness of the emitter layer to be reserved can be difficult to master in the etching process, so that the technical process is actually challenged.
In addition, the emitter thinning process procedure mainly includes self-aligned patterned thinning and Re-aligned patterned thinning, and the 2 emitter thinning processes all use Photoresist (PR) or dielectric (dielectric) material as a thinning etching mask, but in this way, additional process steps such as dielectric deposition (dielectric deposition) or thinning size pattern definition (pattern definition) are required to perform the subsequent emitter thinning process.
Disclosure of Invention
The invention provides a heterojunction bipolar transistor emitter structure and an emitter thinning method, which can complete an emitter thinning process under the condition of not needing an additional photoresist or dielectric layer (dielectric) material to make a thinning etching mask.
In order to solve the above technical problem, the present invention provides a heterojunction bipolar transistor emitter structure, comprising: the emitter cap layer is arranged on the base electrode layer; a first etching stop layer and a second etching stop layer which are stacked from top to bottom are arranged between the emitter layer and the emitter cap layer; the selective etching ratios of the first etching stop layer and the second etching stop layer to different etching solutions are different.
In a preferred embodiment: the materials of the first etch stop layer and the second etch stop layer include, but are not limited to: InGaP and GaAs, or AlGaAs and GaAs, or InP and InGaAs, or InP and InGaAsP, or InP and InAlAs, or InAlAs and InGaAs, or InAlP and GaAs.
In a preferred embodiment: the heterojunction bipolar transistor is a gallium arsenide-based or indium phosphide-based compound heterojunction bipolar transistor.
The invention also provides a thinning method of the emitter of the heterojunction bipolar transistor, wherein the emitter of the heterojunction bipolar transistor comprises the following steps: the emitter cap layer is arranged on the base electrode layer; the method is characterized in that: a first etching stop layer and a second etching stop layer which are stacked from top to bottom are arranged between the emitter layer and the emitter cap layer; the selective etching ratios of the first etching stop layer and the second etching stop layer to different etching solutions are different;
the thinning process comprises the steps of:
1) etching the emitter cap layer after depositing the emitter metal on the emitter cap layer;
2) etching the first etch stop layer without affecting the second etch stop layer;
3) etching the second etch stop layer and the emitter cap layer, wherein the first etch stop layer is not affected;
4) etching the first etch stop layer and the emitter layer without affecting the second etch stop layer;
5) and depositing a base electrode metal on the base electrode layer.
In a preferred embodiment: in steps 1 and 3, the etching solution is the same.
In a preferred embodiment: in steps 1 and 3, the etching solution selected is ammonia-water based acetic acid.
In a preferred embodiment: in steps 2 and 4, the etching solution is the same.
In a preferred embodiment: in steps 2 and 4, the etching solution selected is hydrochloric acid.
In a preferred embodiment: the materials of the first etch stop layer and the second etch stop layer include, but are not limited to: InGaP and GaAs, or AlGaAs and GaAs, or InP and InGaAs, or InP and InGaAsP, or InP and InAlAs, or InAlAs and InGaAs, or InAlP and GaAs.
In a preferred embodiment: the heterojunction bipolar transistor is a gallium arsenide-based or indium phosphide-based compound heterojunction bipolar transistor.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention provides an emitter structure of a heterojunction bipolar transistor and an emitter thinning method, which realize an emitter thinning process by utilizing the characteristic that different etching stop layers have different selective etching ratios to etching liquid. Compared with the existing emitter thinning process, the technical scheme does not need additional process steps such as dielectric layer deposition or thinning size pattern definition, and the like, can easily realize the emitter thinning process by two etching stop layers with different selective etching ratios, and does not influence the crystal film quality and the device characteristics.
Drawings
Fig. 1-5 are flow diagrams of a method of emitter thinning in a preferred embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings and the detailed implementation mode.
A method of thinning a heterojunction bipolar transistor emitter, the heterojunction bipolar transistor emitter comprising: a base electrode layer 1, an emitter layer 2 and an emitter cap layer 3 which are arranged from bottom to top in a laminated manner; a first etching stop layer 4 and a second etching stop layer 5 which are stacked from top to bottom are arranged between the emitter layer 2 and the emitter cap layer 3; the selective etching ratios of the first etching stop layer 4 and the second etching stop layer 5 to different etching solutions are different; in this embodiment, the material of the emitter cap layer 3 is gradually changed from GaAs to InGaAs, the material of the first etching stop layer 4 is InGaP, the material of the second etching stop layer 5 is GaAs, the material of the emitter layer 2 is InGaP, and the material of the base electrode layer 1 is GaAs. The heterojunction bipolar transistor is therefore a gallium arsenide based heterojunction bipolar transistor. As a simple alternative, this embodiment can also be applied to an indium phosphide-based compound heterojunction bipolar transistor.
The thinning process comprises the following steps:
1) after depositing emitter metal 6 on the emitter cap layer 3, etching the emitter cap layer 3 by using ammonia-water-based (NH4 OH-based) acid liquid; as shown in fig. 1.
2) Etching the first etch stop layer 4 using a hydrochloric acid-based (HCl-based) acid solution, the second etch stop layer 5 not being affected when etching the first etch stop layer 4 since the first etch stop layer 4 and the second etch stop layer 5 have different selective etching ratios with respect to the hydrochloric acid-based (HCl-based) acid solution;
3) etching the second etch stop layer 5 and the emitter cap layer 3 by using an ammonia-water-based (NH4 OH-based) acid solution, so that the undercut (undercut) type appearance of the emitter cap layer 5 is more obvious, and the first etch stop layer 4 is not affected in the process;
4) etching the first etching stop layer 4 and the emitter layer 2 by using a hydrochloric acid-based (HCl-based) acid solution, wherein during the etching process, undercut (undercut) type appearance still occurs on the emitter layer 2 and the first etching stop layer 4, and the second etching stop layer 5 is not affected;
5) a base electrode metal 7 is deposited on the base electrode layer 1.
As a simple alternative to this embodiment, the materials of the first etch stop layer 4 and the second etch stop layer 5 may also be AlGaAs and GaAs, or InP and InGaAs, or InP and InGaAsP, or InP and InAlAs, or InAlAs and InGaAs, or InAlP and GaAs.
The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and variations or technical scopes disclosed by the present invention can be easily conceived by those skilled in the art. Alternatives are intended to be included within the scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.
Claims (7)
1. A method for thinning an emitter of a heterojunction bipolar transistor is characterized in that: the heterojunction bipolar transistor emitter comprises: the emitter cap layer is arranged on the base electrode layer; the method is characterized in that: a first etching stop layer and a second etching stop layer which are stacked from top to bottom are arranged between the emitter layer and the emitter cap layer; the selective etching ratios of the first etching stop layer and the second etching stop layer to different etching solutions are different;
the thinning process comprises the steps of:
1) etching the emitter cap layer after depositing the emitter metal on the emitter cap layer;
2) etching the first etch stop layer without affecting the second etch stop layer;
3) etching the second etch stop layer and the emitter cap layer, wherein the first etch stop layer is not affected;
4) etching the first etch stop layer and the emitter layer without affecting the second etch stop layer;
5) and depositing a base electrode metal on the base electrode layer.
2. The method of claim 1, wherein: in steps 1 and 3, the etching solution is the same.
3. The method of claim 2, wherein: in steps 1 and 3, the etching solution selected is ammonia-water based acetic acid.
4. The method of claim 1, wherein: in steps 2 and 4, the etching solution is the same.
5. The method of claim 4, wherein: in the steps 2 and 4, the selected etching solution is hydrochloric acid.
6. The method of claim 4, wherein: the materials of the first etch stop layer and the second etch stop layer include, but are not limited to: InGaP and GaAs, or AlGaAs and GaAs, or InP and InGaAs, or InP and InGaAsP, or InP and InAlAs, or InAlAs and InGaAs, or InAlP and GaAs.
7. The method of claim 1, wherein: the heterojunction bipolar transistor is a gallium arsenide-based or indium phosphide-based compound heterojunction bipolar transistor.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5682046A (en) * | 1993-08-12 | 1997-10-28 | Fujitsu Limited | Heterojunction bipolar semiconductor device and its manufacturing method |
| CN1659693A (en) * | 2002-06-10 | 2005-08-24 | 单片集成电路半导体有限公司 | Method for producing a hetero-bipolar transistor and hetero-bipolar-transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4056226B2 (en) * | 2001-02-23 | 2008-03-05 | 株式会社ルネサステクノロジ | Semiconductor device |
| JP3866936B2 (en) * | 2001-06-18 | 2007-01-10 | シャープ株式会社 | Heterojunction bipolar transistor |
| JP3755658B2 (en) * | 2002-05-30 | 2006-03-15 | 横河電機株式会社 | Manufacturing method of HBT |
| US6727530B1 (en) * | 2003-03-04 | 2004-04-27 | Xindium Technologies, Inc. | Integrated photodetector and heterojunction bipolar transistors |
| US6806129B1 (en) * | 2003-05-09 | 2004-10-19 | Agilent Technologies, Inc. | Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors |
| KR100636595B1 (en) * | 2004-11-09 | 2006-10-23 | 한국전자통신연구원 | Fabrication method of heterojunction bipolar transistor |
| KR100687758B1 (en) * | 2005-12-08 | 2007-02-27 | 한국전자통신연구원 | Hetero junction bipolar transistor and method for manufacturing the same |
| CN103871858A (en) * | 2014-03-03 | 2014-06-18 | 中国电子科技集团公司第五十五研究所 | Manufacturing method for submicron electrode of indium phosphide-based heterojunction transistor |
| CN106683993A (en) * | 2016-12-26 | 2017-05-17 | 厦门市三安光电科技有限公司 | Preparation method for transistor ohmic contact electrode |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5682046A (en) * | 1993-08-12 | 1997-10-28 | Fujitsu Limited | Heterojunction bipolar semiconductor device and its manufacturing method |
| CN1659693A (en) * | 2002-06-10 | 2005-08-24 | 单片集成电路半导体有限公司 | Method for producing a hetero-bipolar transistor and hetero-bipolar-transistor |
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