CN109768085A - A kind of triode and preparation method thereof - Google Patents
A kind of triode and preparation method thereof Download PDFInfo
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- CN109768085A CN109768085A CN201811517969.0A CN201811517969A CN109768085A CN 109768085 A CN109768085 A CN 109768085A CN 201811517969 A CN201811517969 A CN 201811517969A CN 109768085 A CN109768085 A CN 109768085A
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Abstract
The present invention relates to a kind of triodes and preparation method thereof, which comprises the substrate of the first conduction type is provided, in the epitaxial layer of one conduction type of substrate surface growth regulation；The injection of the second conductive type ion is carried out in the epi-layer surface, forms the base area；The injection of the first conductive type ion is carried out in the base region surface, forms emitter region；The emitter region is etched, to leak out the edge of base area cruelly；The base contact area of the second conduction type is formed in the base region surface region leaked out cruelly, the base contact area and the emitter region have interval in the horizontal direction；Dielectric layer is formed, the dielectric layer includes the second part for being formed in the first part of the base region surface leaked out cruelly and being formed in part emitter region surface；It is respectively formed front metal layer and metal layer on back.The above method makes the current capacity of triode proposed by the present invention be greatly improved.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically a kind of production method of triode.
Background technique
Triode is that a kind of semiconductor devices of control electric current can be weak current because it is with Current amplifier effect
Signal zooms into biggish current signal, is the core element of electronic circuit.Triode is made on a block semiconductor silicon wafer
Bulk semiconductor is divided into three parts by the PN junction of two close proximities, two PN junctions, and middle section is base area, and two side portions are hairs
Penetrate area and collecting zone, usual emitter region doping concentration highest, followed by base area, adulterating most light is collecting zone.Each region
Electrode leads to client is referred to as emitter, collector and base area.It is divided into PNP triode and two kinds of NPN triode by doping type,
The Current amplifier ability of triode is indicated with amplification factor (symbol " β "), is equal to the ratio of collector current and base current
Value, this is the most important parameter of triode.
Traditional technology generallys use the surface area of increase device to increase the power of triode, then cooperates huge heat dissipation
The shortcomings that device, such mode it is clear that final electrical equipment is on the one hand caused to need huge volume, on the other hand its
The utilization rate of efficiency is not also high.
Summary of the invention
The embodiment of the invention provides a kind of production methods of triode, and device can be improved under the premise of not increasing area
The power of part.
In a first aspect, the embodiment of the invention provides a kind of production methods of triode, which comprises provide first
The substrate of conduction type, in the epitaxial layer of one conduction type of substrate surface growth regulation；The is carried out in the epi-layer surface
The injection of two conductive type ions forms the base area；The injection of the first conductive type ion, shape are carried out in the base region surface
At emitter region；The emitter region is etched, to leak out the edge of base area cruelly；Second is formed in the base region surface region leaked out cruelly to lead
The base contact area of electric type, the base contact area and the emitter region have interval in the horizontal direction；Dielectric layer is formed,
The dielectric layer includes being formed in the first part of the base region surface leaked out cruelly and being formed in part emitter region surface
Second part；It is respectively formed front metal layer and metal layer on back.
Second aspect, the embodiment of the present invention provide a kind of triode, and the triode includes: the lining of the first conduction type
Bottom, in the epitaxial layer of one conduction type of substrate surface growth regulation；It is formed in the second conduction type of the epi-layer surface
Base area；It is formed in the emitter region of the first conduction type of base region surface, the edge of the base area is not complete by the emitter region
Covering；It is formed in the base contact area of the first conduction type in the base region surface region not covered by the emitter region；Medium
Layer, the dielectric layer includes being formed in not by the first part for the base region surface that the emitter region covers and being formed in the hair
Penetrate the second part in area's part of the surface；Front metal layer and metal layer on back.
It is appreciated that the present invention can be in the triode operation by the above method, electric current longitudinally flows from the bottom up
It is dynamic, since transmitting junction area is very big, to make the current capacity of triode proposed by the present invention be greatly improved, simultaneously
The area of triode does not significantly increase, therefore does not also need additionally to increase radiator.Three pole provided in this embodiment simultaneously
The method and process of pipe is simple, at low cost.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
It constitutes a part of attached drawing of the invention to be used to provide further understanding of the present invention, schematic implementation of the invention
Example and its specification are used to explain the present invention, and do not constitute the improper restriction to not allowing you to invent.
Fig. 1 is the flow diagram of the method for the production triode that the embodiment of the present invention proposes；
Fig. 2 is the structural schematic diagram for the triode that the embodiment of the present invention proposes；
Fig. 3 to Fig. 9 is the schematic diagram of the section structure of the method for the production triode that the embodiment of the present invention proposes；
Description of symbols: 1, substrate；2, epitaxial layer；3, base area；4, emitter region；5, base contact area；6, dielectric layer；7,
Emitter；8, base stage；9, collector.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Referring to Fig. 1, Fig. 1 is the flow diagram of the method for the production triode that the embodiment of the present invention proposes, the present invention
A kind of production method of triode is provided, comprising:
Step S01: the substrate of the first conduction type is provided, in the extension of one conduction type of substrate surface growth regulation
Layer；
Step S02: the injection of the second conductive type ion is carried out in the epi-layer surface, forms the base area；
Step S03: the injection of the first conductive type ion is carried out in the base region surface, forms emitter region；
Step S04: etching the emitter region, to leak out the edge of base area cruelly；
Step S05: the base contact area of the second conduction type, the base area are formed in the base region surface region leaked out cruelly
Contact zone and the emitter region have interval in the horizontal direction；
Step S06: formed dielectric layer, the dielectric layer include be formed in the base region surface leaked out cruelly first part and
It is formed in the second part on part emitter region surface；
Step S07: front metal layer and metal layer on back are respectively formed.
It is appreciated that the present invention can be in the triode operation by the above method, electric current longitudinally flows from the bottom up
It is dynamic, since transmitting junction area is very big, to make the current capacity of triode proposed by the present invention be greatly improved, simultaneously
The area of triode does not significantly increase, therefore does not also need additionally to increase radiator.Three pole provided in this embodiment simultaneously
The method and process of pipe is simple, at low cost.
With reference to the accompanying drawings, the method for the above-mentioned formation transistor is elaborated.
For convenience of subsequent description, special to illustrate herein: technical solution of the present invention is related to designing and manufacturing for semiconductor devices,
Semiconductor refers to that a kind of electric conductivity can be controlled, conductive extensions can from insulator to the material changed between conductor, common half
Conductor material has silicon, germanium, GaAs etc., and silicon be in various semiconductor materials it is most powerful, be most widely used one
Kind.Semiconductor is divided into intrinsic semiconductor, P-type semiconductor and N-type semiconductor, and free from foreign meter and without lattice defect semiconductor is known as
Intrinsic semiconductor mixes triad (such as boron, indium, gallium) in pure silicon crystal, is allowed to replace silicon atom in lattice
Seat just forms P-type semiconductor, mixes pentad (such as phosphorus, arsenic) in pure silicon crystal, is allowed to replace silicon in lattice
The position of atom is formed N-type semiconductor, and P-type semiconductor is different with the conduction type of N-type semiconductor, in reality of the invention
It applies in example, the first conduction type is N-type, and the second conduction type is p-type, in an embodiment of the present invention, if without especially saying
Bright, the preferred Doped ions of every kind of conduction type are all that can be changed to the ion with same conductivity type.
Attached drawing 3 is please referred to, step S01 is executed: the substrate 1 of the first conduction type is provided, in the 1 surface growth regulation of substrate
The epitaxial layer 2 of one conduction type；Specifically, carrier of the substrate 1 as the device, primarily serves the effect of support.One
As in the case of, the material of the substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., in the present embodiment,
The substrate 1 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material.In some embodiment party of the invention
In formula, the substrate 1 is N-type substrate, and 1 resistivity of substrate is 0.001~0.005 Ω * cm, with a thickness of 250~350 μm,
In the present embodiment, the Doped ions of the substrate 1 are specially phosphonium ion, certainly, in other embodiments, the substrate
1 Doped ions can be also other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, the substrate 1 is as the present invention
The collector contact area of the triode of proposition.The pressure resistance of the thickness and concentration and device of the epitaxial layer 2 is closely related, in this hair
In bright some embodiments, 2 resistivity of epitaxial layer is 45~60 Ω * cm, and thickness is between 15~18 μm.Preferably,
The epitaxial layer 2 is formed by the relatively simple homoepitaxy of technique, i.e., the material of the described epitaxial layer 2 and the material of the substrate 1
Expect it is identical, when the material of substrate 1 be silicon when, the material of the epitaxial layer 2 is also silicon.The epitaxial layer 2 can be raw using extension
Regular way is formed in the upper surface of the substrate 1.The doping type of the epitaxial layer 2 is identical as the doping type of the substrate 1,
In present embodiment, the substrate 1 is n-type doping, and the epitaxial layer 2 is n-type doping, in other embodiments, if described
Substrate 1 is p-type doping, and the epitaxial layer 2 is p-type doping.In the present embodiment, the Doped ions of the epitaxial layer 2 are specific
For phosphonium ion, in other embodiments, the Doped ions of the epitaxial layer 2 can be also other pentavalent ions such as arsenic or antimony.More
Specifically, the epitaxial growth method can be vapor phase epitaxial growth, liquid phase epitaxial process, vacuum evaporation growth method, high frequency
Sputter growth method, molecular beam epitaxial growth method etc., preferably chemical vapor deposition method (or vapor phase epitaxial growth), chemistry
Vapor deposition method is a kind of to react and deposit into the work of solid thin layer or film on solid matrix surface with vapor reaction raw material
Skill, is a kind of epitaxial growth method of the transistor of comparative maturity, this method by silicon and doped chemical spray in the substrate 1 it
On, uniformity is reproducible, and step coverage is excellent.The perfection of silicon materials can be improved in chemical vapor deposition method simultaneously
Property, the integrated level of device is improved, raising minority carrier life time is reached, reduces the leakage current of storage element.It is to be appreciated that described outer
Prolong layer 2 as collecting zone of the invention, collecting zone is made by using epitaxy technique, integral thickness is highly uniform, than tradition
It is easier to control using the collecting zone of buried structure.It should also be noted that, triode provided by the invention due to collecting zone
Resistivity is higher, can undertake very high voltage, while its thickness does not increase, therefore its conducting resistance is not when triode operation
It can significantly increase.
Attached drawing 4 is please referred to, step S02 is executed: carrying out the injection of the second conductive type ion on 2 surface of epitaxial layer,
Form the base area 3；Further, in the present embodiment, by taking second conduction type is p-type as an example, in the extension
2 surface of layer carry out the injection of the second conductive type ion, and forming the base area 3 can specifically include: to 2 surface of epitaxial layer
Carry out the injection of boron ion, the implantation dosage 1.5E13-2.5E13/cm of the boron ion2, Implantation Energy is 100~120KeV；
The semiconductor structure of formation is sent into boiler tube and carries out High temperature diffusion, and then forms the base area 3.Wherein, the formation is partly led
Body structure refers to by carrying out the injection of the second conductive type ion on 2 surface of epitaxial layer in step S01 and step S02
The semiconductor structure formed afterwards.The boron ion can have indium, gallium plasma to replace.In embodiments of the present invention, enter
Boiler tube carry out High temperature diffusion temperature be 1125~1175 DEG C, the thermal process duration be 270~300 minutes, diffusion time according to
Junction depth determines that the purpose for carrying out the diffusion of High temperature diffusion is to form certain Impurity Distribution, and device is made to have reasonable table
Face concentration and junction depth, and this is also the main foundation of determining process conditions, the important process control parameter of diffusion has: temperature, when
Between and gas flow.It is to be appreciated that the base area 3 is injected using whole face, diffuseed to form, thickness is also highly uniform, because
This, transistor parameter stability provided by the invention is far superior to conventionally produced triode, is particularly suitable for large quantities of
Amount production.
Attached drawing 5 is please referred to, step S03 is executed: carrying out the injection of the first conductive type ion, shape on 3 surface of base area
At emitter region 4；Specifically, after the ion for injecting first conduction type, it is also desirable to realize and be injected to 3 surface of base area
The first conductive type ion high-temperature diffusion process, specifically, the emitter region 4 carry out High temperature diffusion temperature be 1125~
1175 DEG C, the diffusion time of the emitter region 4 determines according to the DC current amplification factor of triode.In present embodiment
In, first conduction type is N-type, specifically, the ion of first conduction type is phosphonium ion, in other embodiments
In can also be replaced by other pentavalent ions such as arsenic or antimony.In order to guarantee the current capacity of triode of the invention, preferably,
The implantation dosage of the phosphonium ion of the emitter region 4 is 6E15~8E15/cm2, Implantation Energy is 80~100KeV.
Attached drawing 6 is please referred to, step S04 is executed: the emitter region 4 is etched, to leak out the edge of base area 3 cruelly；Further,
Before etching the emitter region 4, need to realize that the photoetching offset plate figure for the emitter region 4 that definition needs to retain, the above process are referred to as
4 region of emitter region not being covered by the mask is etched away, is then gone again then using the photoetching offset plate figure as exposure mask for photoetching
Fall the photoetching offset plate figure.The etching mode includes dry etching and wet etching, wherein in the present embodiment, to institute
The etching mode for stating emitter region 4 is dry etching, and the dry etching includes photoablation, gaseous corrosion, plasma etching etc.,
And to have the advantages that easily to realize that automation, treatment process are not introduced into pollution, cleannes high for dry etching, more specifically, photoetching and
Etching technics includes: crystal column surface cleaning, drying, linging, spin coating photoresist, soft baking, is directed at exposure, rear baking, develops, dry firmly, carving
The processes such as erosion, detection, photoetching can be using the methods of contact exposure, proximity printing or projection exposures.In this embodiment party
In formula, what it is by etching removal is that institute is worked as since the emitter region 4 covers the base area 3 in the marginal portion of the emitter region 4
After the marginal portion removal for stating emitter region 4, the edge of the base area 3 is exposed, it is also necessary to is appreciated that, to the transmitting
The marginal portion in area 4 can all remove, and can also partially remove, and determine with specific reference to the requirement of device.
Attached drawing 7 is please referred to, step S05 is executed: forming the base of the second conduction type in 3 surface region of base area leaked out cruelly
Area contact zone 5, the base contact area 5 have interval with the emitter region 4 in the horizontal direction；The base contact area 5 is logical
Overdoping technique is formed, and the doping process includes thermal diffusion method and ion implantation, and thermal diffusion is that earliest use is also most simple
Single doping process, it utilizes the diffusion motion of atom at high temperature, makes foreign atom from dense impurity source into silicon
It spreads and forms certain distribution.Thermal diffusion method usually carries out in two steps: pre-deposited and main diffusion.Pre-deposited is in high temperature
It is lower that the doping window on silicon wafer is diffused using the impurity sources such as boron, phosphorus, layer is formed at window but is had
The impurity layer of higher concentration.Main diffusion is to be formed by surface impurity layer using pre-deposited to do impurity source, at high temperature by this layer
The process that impurity is spread into silicon body, the time usually promoted are longer.And ion implanting is adulterated using high-energy particle bombardment
Foreign atom or molecule are allowed to ionize, and further accelerate certain energy, are emitted directly toward it inside silicon wafer, then make by annealing
Impurity activation achievees the purpose that doping.Ion implanting can guarantee the consistency of junction depth, repeatability, so that it is guaranteed that device parameters
Consistency, and concentration distribution can be made steep by ion implanting.In an embodiment of the present invention, the base contact area 5
It is formed by ion implantation technology, in the present embodiment, the impurity that the base contact area 5 is injected is boron difluoride, injection
Dosage is 2E15~5E15/cm2, Implantation Energy is 40~60KeV.In other embodiments, the base contact area 5 is miscellaneous
Matter can also be boron, indium, gallium plasma.
Attached drawing 8 is please referred to, step S06 is executed: forming dielectric layer 6, the dielectric layer 6 includes being formed in the base area leaked out cruelly
The first part on 3 surfaces and the second part for being formed in 4 surface of part emitter region；It is also to be noted that in order to protect
Demonstrate,prove the extraction of subsequent electrode, the base contact area 5 is not completely covered the first part, in order to realize base contact area 5 with
The good contact of base stage, it is preferred that in the present embodiment, the dielectric layer 6 does not cover the base contact area 5.Further
, in certain embodiments of the present invention, forming the dielectric layer 6 can specifically include: in the base area 3 and the transmitting
The surface in area 4 grows silicon dioxide layer；By photoetching and etching technics, base stage contact hole and hair are formed in the silicon dioxide layer
Emitter contact hole.Specifically, grow the silicon dioxide layer can for high-temperature oxidation, growth temperature 800~1000 DEG C it
Between, growth thickness is between 1800~2200A；In other embodiments, the material of the dielectric layer 6 can also be oxidation
Aluminium, silicon oxynitride, one of or arbitrarily a variety of combination such as nitrogen oxide, the method for forming the dielectric layer 6 can also pass through
Depositing technics is formed, such as CVD method, for example, by CVD method in the base area 3 being exposed and
4 surface deposition silicon nitride layer of emitter region forms base stage contact then again by photoetching and etching technics on the silicon nitride layer
Hole and emitter contact hole, and then form the dielectric layer 6 for offering base stage contact hole and emitter contact hole.
Attached drawing 9 is please referred to, step S07 is executed: being respectively formed front metal layer and metal layer on back；Specifically, difference shape
It is specifically included at front metal layer and metal layer on back: metal sputtering is carried out to the emitter region 4 and 5 surface of base contact area,
Then emitter 7 and base stage are formed by photoetching and etching, wherein the emitter 7 is electrically connected with the emitter region 4, described
Base stage is electrically connected with the base contact area 5；The substrate 1 is carried out grinding processing is thinned far from the side of the epitaxial layer 2,
Then re-evaporation metal, and then collector 9 is formed, the collector 9 is electrically connected with the substrate 1.More specifically, the transmitting
Pole 7 and the base stage pass through the emitter contact hole and base stage contact hole and the emitter region 4 and base on the dielectric layer 6 respectively
Area contact zone 5 connects；In the present embodiment, the base stage can may be bilateral extraction for unilateral extraction, with specific reference to
After etching the emitter region 4,3 region of the base area that is exposed is determined.Further, the base stage and transmitting are being formed
After pole 7, the method also includes carrying out pad pasting protection to front side of silicon wafer, it should be noted that the front side of silicon wafer refers to
Far from the face where the epitaxial layer 2, the base stage and the emitter 7 are front electricity for the base stage and the emitter 7
Pole, and the substrate 1 is silicon chip back side far from the face where the epitaxial layer 2, the collector 9 is rear electrode.It should
It is appreciated that, the present invention makes the triode final thickness be only by carrying out reduction processing to the substrate 1 for being located at the back side
Between 100~150 μm, the resistance of collector 9 further reduced, not only meet powerful requirement, while it can also be with work
Make in high frequency environment.
Attached drawing 2 is please referred to, the embodiment of the present invention provides a kind of triode, and the triode includes: the first conduction type
Substrate 1, in the epitaxial layer 2 of 1 surface growth regulation of substrate, one conduction type；Be formed in 2 surface of epitaxial layer second is led
The base area 3 of electric type；It is formed in the emitter region 4 of first conduction type on 3 surface of base area, the edge of the base area 3 is not described
Emitter region 4 is completely covered；It is formed in the base of the second conduction type in 3 surface region of base area not covered by the emitter region 4
Area contact zone 5；Dielectric layer 6, the dielectric layer 6 include first for being formed in 3 surface of base area not covered by the emitter region 4
The second part for dividing and being formed in 4 part of the surface of emitter region；Front metal layer and metal layer on back.
It is appreciated that the present invention can be in the triode operation by the above method, electric current longitudinally flows from the bottom up
It is dynamic, it is several to which current capacity is greatly improved since transmitting junction area is very big, that is, it is provided with powerful characteristic, together
When triode area do not significantly increase, therefore do not need additionally to increase radiator yet.While provided in this embodiment three
The method and process of pole pipe is simple, at low cost.
Further, carrier of the substrate 1 as the device, primarily serves the effect of support.Under normal circumstances, institute
The material for stating substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., and in the present embodiment, the substrate 1 is
Silicon substrate, silicon are most common, cheap and stable performance semiconductor material.In certain embodiments of the present invention, the lining
Bottom 1 is N-type, and 1 resistivity of substrate is 0.001~0.005 Ω * cm, with a thickness of 250~350 μm, in the present embodiment,
The Doped ions of the substrate 1 are specially phosphonium ion, and certainly, in other embodiments, the Doped ions of the substrate 1 may be used also
For other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, collection of the substrate 1 as triode proposed by the present invention
Electrode contact zone.The pressure resistance of the thickness and concentration and device of the epitaxial layer 2 is closely related, in some embodiments of the present invention
In, 2 resistivity of epitaxial layer is 45~60 Ω * cm, and thickness is between 15~18 μm.Preferably, the epitaxial layer 2 passes through
The relatively simple homoepitaxy of technique is formed, i.e., the material of the described epitaxial layer 2 is identical as the material of the substrate 1, when substrate 1
When material is silicon, the material of the epitaxial layer 2 is also silicon.The epitaxial layer 2 can be formed in the lining using epitaxial growth method
The upper surface at bottom 1.The doping type of the epitaxial layer 2 is identical as the doping type of the substrate 1, in the present embodiment, institute
Stating substrate 1 is n-type doping, and the epitaxial layer 2 is n-type doping, in other embodiments, if the substrate 1 is p-type doping,
The epitaxial layer 2 is p-type doping.In the present embodiment, the Doped ions of the epitaxial layer 2 are specially phosphonium ion, at other
In embodiment, the Doped ions of the epitaxial layer 2 can be also other pentavalent ions such as arsenic or antimony.More specifically, the extension
Growth method can be vapor phase epitaxial growth, liquid phase epitaxial process, vacuum evaporation growth method, high-frequency sputtering growth method, molecule
Beam epitaxy growth method etc., preferably chemical vapor deposition method (or vapor phase epitaxial growth), chemical vapor deposition method are
It is a kind of to react and deposit into the technique of solid thin layer or film on solid matrix surface with vapor reaction raw material, be a kind of comparison at
The epitaxial growth method of ripe transistor, this method spray silicon and doped chemical on the substrate 1, uniformity, repeatability
It is good, and step coverage is excellent.The perfection of silicon materials can be improved in chemical vapor deposition method simultaneously, improves the integrated of device
Degree, reaches raising minority carrier life time, reduces the leakage current of storage element.It is to be appreciated that the epitaxial layer 2 is as of the invention
Collecting zone is made by using epitaxy technique in collecting zone, and integral thickness is highly uniform, than the current collection of conventionally employed buried structure
Area is easier to control.
Further, the base area 3 is formed in the surface of the epitaxial layer 2, in the present embodiment, the base area 3
Doped ions are boron ion, doping concentration 1.5E13-2.5E13/cm3.When first conduction type is N-type, the hair
The Doped ions for penetrating area 4 are that phosphonium ion certainly in other embodiments can also be by other pentavalent ion generations such as arsenic or antimony
It replaces.In order to guarantee the current capacity of triode of the invention, preferably, doping 6E15~8E15/cm of the emitter region 43。
The base contact area 5 is formed by doping process, and the doping process includes thermal diffusion method and ion implantation,
Thermal diffusion is earliest using being also simplest doping process, it utilizes the diffusion motion of atom at high temperature, makes foreign atom
It is spread from dense impurity source into silicon and forms certain distribution.Thermal diffusion method usually carries out in two steps: pre- to form sediment
Long-pending and main diffusion.Pre-deposited is to be diffused at high temperature using impurity sources such as boron, phosphorus to the doping window on silicon wafer,
Layer but the impurity layer with higher concentration are formed at window.Main diffusion is that surface impurity layer is formed by using pre-deposited
Impurity source is done, the process at high temperature spreading this layer of impurity into silicon body, the time usually promoted is longer.And ion implanting is
The foreign atom or molecule adulterated using high-energy particle bombardment, is allowed to ionize, further accelerates certain energy, it is made to be emitted directly toward silicon
Inside piece, then makes impurity activation by annealing, achieve the purpose that doping.Ion implanting can guarantee the consistency of junction depth, repeat
Property, so that it is guaranteed that the consistency of device parameters, and concentration distribution can be made steep by ion implanting.In implementation of the invention
In example, the base contact area 5 is formed by ion implantation technology, in the present embodiment, what the base contact area 5 was injected
Impurity is boron difluoride, and implantation dosage is 2E15~5E15/cm2, Implantation Energy is 40~60KeV.In other embodiments,
The impurity in the base contact area 5 can also be boron, indium, gallium plasma.
Further, the dielectric layer 6 includes being formed in the first part on 3 surface of base area leaked out cruelly and being formed in institute
State the second part on 4 surface of part emitter region；It is also to be noted that the extraction in order to guarantee subsequent electrode, described first
Divide and the base contact area 5 is not completely covered, in order to realize that base contact area 5 is contacted with the good of base stage, it is preferred that in this reality
It applies in mode, the dielectric layer 6 does not cover the base contact area 5.Further, in certain embodiments of the present invention,
Forming the dielectric layer 6 can specifically include: grow silicon dioxide layer in the base area 3 and the surface of the emitter region 4；Pass through
Photoetching and etching technics form base stage contact hole and emitter contact hole in the silicon dioxide layer.Specifically, growth described two
Silicon oxide layer can be high-temperature oxidation, and growth temperature is between 800~1000 DEG C, and growth thickness is between 1800~2200A；
In other embodiments, the material of the dielectric layer 6 can also be aluminium oxide, silicon oxynitride, nitrogen oxide etc. it is one of or
Any a variety of combination, the method for forming the dielectric layer 6 can also be formed by depositing technics, such as CVD method,
For example, then being led to again by CVD method in 4 surface deposition silicon nitride layer of the base area being exposed and emitter region
Photoetching and etching technics are crossed, forms base stage contact hole and emitter contact hole on the silicon nitride layer, and then formed and offered
The dielectric layer 6 of base stage contact hole and emitter contact hole.
Further, the front metal layer includes emitter 7 and base stage 8, wherein the emitter 7 and the transmitting
Area 4 is electrically connected, and the base stage 8 is electrically connected with the base contact area 5；The metal layer on back includes collector 9, the current collection
Pole 9 is electrically connected with the substrate 1, and the base stage 8 can may be bilateral extraction for unilateral extraction, with specific reference to described in etching
After emitter region 4,3 region area of the base area that is exposed is determined.
Further, although preferred embodiments of the present invention have been described, but those skilled in the art once learn
Basic creative concept, then additional changes and modifications may be made to these embodiments.So appended claims are intended to solve
It is interpreted as including preferred embodiment and all change and modification for falling into the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of production method of triode, which is characterized in that the described method includes:
The substrate of the first conduction type is provided, in the epitaxial layer of one conduction type of substrate surface growth regulation；
The injection of the second conductive type ion is carried out in the epi-layer surface, forms the base area；
The injection of the first conductive type ion is carried out in the base region surface, forms emitter region；
The emitter region is etched, to leak out the edge of base area cruelly；
Form the base contact area of the second conduction type in the base region surface region leaked out cruelly, the base contact area with it is described
Emitter region has interval in the horizontal direction；
Dielectric layer is formed, the dielectric layer includes being formed in the first part of the base region surface leaked out cruelly and being formed in the portion
Divide the second part on emitter region surface；
It is respectively formed front metal layer and metal layer on back.
2. the production method of triode as described in claim 1, which is characterized in that described to carry out the in the epi-layer surface
The injection of two conductive type ions forms the base area and specifically includes:
The injection of boron ion, the implantation dosage 1.5E13-2.5E13/cm of the boron ion are carried out to the epi-layer surface2, note
Entering energy is 100~120KeV；
The semiconductor structure of formation is sent into boiler tube and carries out High temperature diffusion, and then forms the base area.
3. the production method of triode as claimed in claim 2, which is characterized in that the temperature of the High temperature diffusion 1125~
Between 1175 DEG C, the process duration of High temperature diffusion is 270~300 minutes.
4. the production method of triode as described in claim 1, which is characterized in that be respectively formed front metal layer and back-side gold
Belong to layer to specifically include:
Metal sputtering is carried out to the emitter region and base contact area surface, emitter and base are then formed by photoetching and etching
Pole, wherein the emitter is electrically connected with the emitter region, and the base stage is electrically connected with the base contact area；
The substrate is carried out grinding processing is thinned far from the side of the epitaxial layer, then re-evaporation metal, and then forms collection
Electrode, the collector and the substrate electrical connection.
5. the production method of triode as described in claim 1, which is characterized in that form the dielectric layer and specifically include:
Silicon dioxide layer is grown in the base area and the surface of the emitter region；
By photoetching and etching technics, base stage contact hole and emitter contact hole are formed in the silicon dioxide layer.
6. a kind of triode, which is characterized in that the triode includes:
The substrate of first conduction type, in the epitaxial layer of one conduction type of substrate surface growth regulation；
It is formed in the base area of the second conduction type of the epi-layer surface；
It is formed in the emitter region of the first conduction type of base region surface, the edge of the base area is not covered by the emitter region completely
Lid；
It is formed in the base contact area of the first conduction type in the base region surface region not covered by the emitter region；
Dielectric layer, the dielectric layer include first part and the formation for being formed in the base region surface not covered by the emitter region
Second part in the emitter region part of the surface；
Front metal layer and metal layer on back.
7. the production method of triode as claimed in claim 6, which is characterized in that the front metal layer include emitter and
Base stage, wherein the emitter is electrically connected with the emitter region, and the base stage is electrically connected with the base contact area；The back
Face metal layer includes collector, the collector and the substrate electrical connection.
8. the production method of triode as claimed in claim 6, which is characterized in that the resistivity of the substrate be 0.001~
0.005 Ω * cm, with a thickness of 250~350 μm.
9. the production method of triode as claimed in claim 6, which is characterized in that the resistivity of the epitaxial layer is 45~60
Ω * cm, with a thickness of 15~18 μm.
10. the production method of triode as claimed in claim 6, which is characterized in that the material of the dielectric layer is titanium dioxide
Silicon, thickness is between 1800~2200A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811517969.0A CN109768085A (en) | 2018-12-12 | 2018-12-12 | A kind of triode and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811517969.0A CN109768085A (en) | 2018-12-12 | 2018-12-12 | A kind of triode and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN109768085A true CN109768085A (en) | 2019-05-17 |
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ID=66450611
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811517969.0A Withdrawn CN109768085A (en) | 2018-12-12 | 2018-12-12 | A kind of triode and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109768085A (en) |
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2018
- 2018-12-12 CN CN201811517969.0A patent/CN109768085A/en not_active Withdrawn
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Application publication date: 20190517 |