CN110085669A - A kind of triode and preparation method thereof - Google Patents
A kind of triode and preparation method thereof Download PDFInfo
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- CN110085669A CN110085669A CN201910220298.XA CN201910220298A CN110085669A CN 110085669 A CN110085669 A CN 110085669A CN 201910220298 A CN201910220298 A CN 201910220298A CN 110085669 A CN110085669 A CN 110085669A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The present invention relates to a kind of triodes and preparation method thereof, which comprises the substrate of the first conduction type is provided, in the epitaxial layer of one conduction type of substrate surface growth regulation；The injection region of the first conduction type is formed in the fringe region of the epitaxial layer and forms the base area of the second conduction type in the epitaxial layer intermediate region；The first isolation channel and the second isolation channel are formed in the base area region, second isolation channel interval is formed in the side of first isolation channel and abuts with the injection region；The emitter region of the first conduction type is formed far from the base area region surface of second isolation channel side in first isolation channel；The base contact area of the second conduction type is formed between first isolation channel and second isolation channel；Form dielectric layer, contact hole, emitter, base stage and collector.The triode is at low cost, high pressure resistant.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically a kind of production method of triode.
Background technique
Triode is that a kind of semiconductor devices of control electric current can be weak current because it is with Current amplifier effect
Signal zooms into biggish current signal, is the core element of electronic circuit.Triode is made on a block semiconductor silicon wafer
Bulk semiconductor is divided into three parts by the PN junction of two close proximities, two PN junctions, and middle section is base area, and two side portions are hairs
Penetrate area and collecting zone, usual emitter region doping concentration highest, followed by base area, adulterating most light is collecting zone.Each region
Electrode leads to client is referred to as emitter, collector and base area.It is divided into PNP triode and two kinds of NPN triode by doping type,
The Current amplifier ability of triode is indicated with amplification factor (symbol " β "), is equal to collector current and base stage electricity
The ratio of stream, this is the most important parameter of triode.
Traditional triode in order to guarantee that each interpolar obtains higher breakdown reverse voltage, usually increase between each pole away from
From, cause device area huge, and influence triode emission effciency and transfer efficiency, thereby reduce the times magnification of triode
Number.
Summary of the invention
The embodiment of the invention provides a kind of production methods of triode, and device can be improved under the premise of not increasing area
The power of part.
In a first aspect, the embodiment of the invention provides a kind of production methods of triode, which comprises provide first
The substrate of conduction type, in the epitaxial layer of one conduction type of substrate surface growth regulation；In the fringe region of the epitaxial layer
It forms the injection region of the first conduction type and forms the base area of the second conduction type in the epitaxial layer intermediate region；Described
The first isolation channel is formed in the region of base area and the second isolation channel, second isolation channel interval are formed in first isolation channel
Side and adjacent with the injection region；In base area region surface shape of first isolation channel far from second isolation channel side
At the emitter region of the first conduction type；The second conduction type is formed between first isolation channel and second isolation channel
Base contact area；Form dielectric layer, contact hole, emitter, base stage and collector.
Second aspect, the embodiment of the present invention provide a kind of triode, and the triode includes: the lining of the first conduction type
Bottom, in the epitaxial layer of one conduction type of substrate surface growth regulation；Be formed in the fringe region of the epitaxial layer first is led
The injection region of electric type and be formed in the epitaxial layer intermediate region the second conduction type base area；It is formed in the base area
Interior the first isolation channel and the second isolation channel, wherein second isolation channel interval be formed in the side of first isolation channel and
It is adjacent with the injection region；It is formed in the of base area region surface of first isolation channel far from second isolation channel side
The emitter region of one conduction type；It is formed in the base of the second conduction type between first isolation channel and second isolation channel
Area contact zone；Dielectric layer, contact hole, emitter, base stage and collector.
First isolation channel and the isolation of the second isolation channel, thoroughly avoid cross between each pole of triode provided by the invention
To the generation of breakdown, when emitter junction and collector junction are in reverse-biased, with the increase of voltage, depletion region can only longitudinally to
Lower extension, therefore depletion region can extend very wide, and high breakdown voltage is obtained with this.Simultaneously because using deep trench isolation, device
No need to increase spacing for the exit of each pole in the surface of part, therefore the surface area of device does not increase, the collection of this device just improved
Cheng Du is conducive to batch production and the reduction of cost.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
It constitutes a part of attached drawing of the invention to be used to provide further understanding of the present invention, schematic implementation of the invention
Example and its specification are used to explain the present invention, and do not constitute the improper restriction to not allowing you to invent.
Fig. 1 is the flow diagram of the method for the production triode that the embodiment of the present invention proposes；
Fig. 2 to Fig. 9 is the schematic diagram of the section structure of the method for the production triode that the embodiment of the present invention proposes；
Description of symbols: 1, substrate；2, epitaxial layer；3, injection region；4, base area；5, the first isolation channel；6, the second isolation
Slot；7, emitter region；8, base contact area；9, collector dielectric layer；10, emitter；11, base stage；12, collector；13, it is passivated
Layer；14, conductive glue；15, metal framework.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Referring to Fig. 1, Fig. 1 is the flow diagram of the method for the production triode that the embodiment of the present invention proposes, the present invention
A kind of production method of triode is provided, comprising:
Step S01: the substrate of the first conduction type is provided, in the extension of one conduction type of substrate surface growth regulation
Layer；
Step S02: the injection region of the first conduction type is formed in the fringe region of the epitaxial layer and in the extension
Layer intermediate region forms the base area of the second conduction type；
Step S03: the first isolation channel and the second isolation channel, second isolation channel interval are formed in the base area region
It is formed in the side of first isolation channel and is abutted with the injection region；
Step S04: first is formed far from the base area region surface of second isolation channel side in first isolation channel
The emitter region of conduction type；
Step S05: the base area that the second conduction type is formed between first isolation channel and second isolation channel connects
Touch area；
Step S06: dielectric layer, contact hole, emitter, base stage and collector are formed.
It is appreciated that the present invention makes first isolation channel and the second isolation channel between each pole of triode by the above method
Isolation, thoroughly avoids the generation laterally punctured, when emitter junction and collector junction are in reverse-biased, with the increase of voltage,
Its depletion region can only longitudinally extend downwards, therefore depletion region can extend very wide, and high breakdown voltage is obtained with this.While by
In using deep trench isolation, no need to increase spacing for the exit of each pole in the surface of device, therefore the surface area of device does not increase, this
With regard to the integrated level of the device of raising, be conducive to batch production and the reduction of cost.
With reference to the accompanying drawings, the method for the above-mentioned formation transistor is elaborated.
For convenience of subsequent description, special to illustrate herein: technical solution of the present invention is related to designing and manufacturing for semiconductor devices,
Semiconductor refers to that a kind of electric conductivity can be controlled, conductive extensions can from insulator to the material changed between conductor, common half
Conductor material has silicon, germanium, GaAs etc., and silicon be in various semiconductor materials it is most powerful, be most widely used one
Kind.Semiconductor is divided into intrinsic semiconductor, P-type semiconductor and N-type semiconductor, and free from foreign meter and without lattice defect semiconductor is known as
Intrinsic semiconductor mixes triad (such as boron, indium, gallium) in pure silicon crystal, is allowed to replace silicon atom in lattice
Seat just forms P-type semiconductor, mixes pentad (such as phosphorus, arsenic) in pure silicon crystal, is allowed to replace silicon in lattice
The position of atom is formed N-type semiconductor, and P-type semiconductor is different with the conduction type of N-type semiconductor, in reality of the invention
It applies in example, the first conduction type is N-type, and the second conduction type is p-type, in an embodiment of the present invention, if without especially saying
Bright, the preferred Doped ions of every kind of conduction type are all that can be changed to the ion with same conductivity type.
Attached drawing 2 is please referred to, step S01 is executed: the substrate 1 of the first conduction type is provided, in the 1 surface growth regulation of substrate
The epitaxial layer 2 of one conduction type；Specifically, carrier of the substrate 1 as the device, primarily serves the effect of support.One
As in the case of, the material of the substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., in the present embodiment,
The substrate 1 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material.In some embodiment party of the invention
In formula, the substrate 1 is N-type heavy doping substrate, and between 0.001~0.01 Ω * cm, thickness exists the resistivity of the substrate 1
Between 220~280 μm, in the present embodiment, the Doped ions of the substrate 1 are specially phosphonium ion, certainly, in other implementations
In mode, the Doped ions of the substrate 1 can be also other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, described
Collector contact area of the substrate 1 as triode proposed by the present invention.The thickness of the epitaxial layer 2 and the pressure resistance of concentration and device
It is closely related, in some embodiments of the invention, 2 resistivity of epitaxial layer between 25~50 Ω * cm, thickness 15~
Between 18 μm.Preferably, the epitaxial layer 2 is formed by the relatively simple homoepitaxy of technique, i.e., the material of the described epitaxial layer 2
Identical as the material of the substrate 1, when the material of substrate 1 is silicon, the material of the epitaxial layer 2 is also silicon.The epitaxial layer 2
The upper surface of the substrate 1 can be formed in using epitaxial growth method.The doping type of the epitaxial layer 2 and the substrate 1
Doping type is identical, and in the present embodiment, the substrate 1 is n-type doping, and the epitaxial layer 2 is n-type doping, in other realities
It applies in mode, if the substrate 1 is p-type doping, the epitaxial layer 2 is p-type doping.In the present embodiment, the epitaxial layer 2
Doped ions be specially phosphonium ion, in other embodiments, the Doped ions of the epitaxial layer 2 can also for arsenic or antimony etc. its
His pentavalent ion.More specifically, the epitaxial growth method can steam for vapor phase epitaxial growth, liquid phase epitaxial process, vacuum
Generation regular way, high-frequency sputtering growth method, molecular beam epitaxial growth method etc., preferably chemical vapor deposition method (or outside gas phase
Epitaxial growth), chemical vapor deposition method is a kind of to be reacted with vapor reaction raw material on solid matrix surface and deposit into solid
The technique of thin layer or film, is a kind of epitaxial growth method of the transistor of comparative maturity, and this method sprays silicon and doped chemical
On the substrate 1, uniformity is reproducible, and step coverage is excellent.Chemical vapor deposition method can be improved simultaneously
The perfection of silicon materials improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.It needs to manage
Collecting zone is made as collecting zone of the invention, by using epitaxy technique in solution, the epitaxial layer 2, and integral thickness is non-
Often uniformly, the collecting zone than conventionally employed buried structure is easier to control.It should be noted triode provided by the invention
Due to collecting zone resistivity it is higher, very high voltage can be undertaken, while its thickness does not increase, therefore when triode operation
Its conducting resistance will not significantly increase, therefore further improve collector current, obtain more preferably working characteristics.
Attached drawing 3 and attached drawing 4 are please referred to, step S02 is executed: forming the first conductive-type in the fringe region of the epitaxial layer 2
The injection region 3 of type and 2 intermediate region of epitaxial layer formed the second conduction type base area 4；On the side of the epitaxial layer 2
Edge region forms the injection region 3 of the first conduction type and forms the base of the second conduction type in 2 intermediate region of epitaxial layer
Area 4 may include: to form the first conduction type on the 2 fringe region surface of epitaxial layer by photoetching, ion implantation technology
Injection region 3；2 surface region of epitaxial layer in 3 inside of injection region forms the base area 4 of the second conduction type；Pass through heat
Diffusion technique promotes the injection region 3 and the base area 4, and the quantity of the injection region 3 can be one or more.
In the present embodiment, the injection element of the injection region 3 is P elements, and implantation dosage is 4E12~6E12/cm2Between, note
Enter energy between 120~150KeV.In the present embodiment, the injection element of the base area 4 is boron, and implantation dosage is in 6E12
~8E12/cm2Between, Implantation Energy is between 100~120KeV.In the present embodiment, the diffusion temperature of the thermal diffusion
Between 1100~1250 DEG C, thermal process continues 200~350 minutes, so that the junction depth of the base area 4 and the injection region 3 reaches
To 8~10 μm, the purpose for carrying out thermal diffusion process is to form certain Impurity Distribution, and device is made to have reasonable surface concentration
And junction depth, and this is also the main foundation of determining process conditions, the important process control parameter of diffusion has: temperature, time are gentle
Body flow etc..It is to be appreciated that the base area 4 is injected using whole face, diffuseed to form, thickness is also highly uniform, therefore, this
The transistor parameter stability that invention provides is far superior to conventionally produced triode, and it is raw to be particularly suitable for high-volume
It produces.
Attached drawing 5 is please referred to, step S03 is executed: forming the first isolation channel 5 and the second isolation channel in 4 region of base area
6, second isolation channel 6 is spaced the side for being formed in first isolation channel 5 and abuts with the injection region 3；Specifically,
The first isolation channel 5 and the second isolation channel 6 formed in the base area 4 may include: by photoetching and dry etch process, in institute
It states 4 surface etch of base area and goes out first groove and second groove, the second groove interval is formed in the outside of the first groove
And it is adjacent with the injection region 3；The filled media material in the first groove and second groove, so be respectively formed first every
From slot 5 and the second isolation channel 6.Specifically, the dielectric material is silica, after filled media material, in order to form one
A complete surface can be removed the silica of excess surface using the method for chemical mechanical grinding, chemical machinery later
The method of grinding is the conventional techniques of those skilled in the art, is no longer repeated one by one again.In other embodiments, institute
Giving an account of material can also be aluminium oxide, silicon oxynitride, one of or arbitrarily a variety of combination such as nitrogen oxide.More specifically,
The dry etching performs etching the base area 4 using the combination gas of chlorine, boron chloride, and then can be formed steep
Silicon groove shape.It is understood that the quantity of first isolation channel 5 and second isolation channel 6 can be for 1 or more
It is a.
Attached drawing 6 is please referred to, step S04 is executed: forming first in 4 region surface of base area that first isolation channel 5 surrounds
The emitter region 7 of conduction type；Further, the emitter region 7 is formed by ion implanting, forms the transmitting in ion implanting
Before area 7, need to realize that the photoetching offset plate figure for the emitter region 7 that definition needs to form, the above process are referred to as photoetching, then with institute
Photoetching offset plate figure is stated as exposure mask, the emitter region 7, in the present embodiment, the transmitting are formed by ion implantation technology
7 implanted dopant of area is arsenic element, and implantation dosage is in 1E16~1.5E16/cm2Between, Implantation Energy is between 80~100KeV.
It please refers to attached drawing 7, executes step S05: forming the between first isolation channel 5 and second isolation channel 6
The base contact area 8 of two conduction types, the base contact area 8 is for realizing good between subsequent base stage and the base area 4
Good contact, guarantees the reliability of device；The base contact area 8 is formed by doping process, and the doping process includes thermal expansion
Arching pushing and ion implantation, thermal diffusion are earliest using being also simplest doping process, it utilizes the expansion of atom at high temperature
It loads in bulk dynamic, spreads foreign atom into silicon from dense impurity source and form certain distribution.Thermal diffusion method usually divides
Two steps carry out: pre-deposited and main diffusion.Pre-deposited is at high temperature using impurity sources such as boron, phosphorus to mixing on silicon wafer
Miscellaneous window is diffused, and layer but the impurity layer with higher concentration are formed at window.Main diffusion is to utilize pre-deposited
Be formed by surface impurity layer and do impurity source, the process at high temperature spreading this layer of impurity into silicon body, usually promote when
Between it is longer.And ion implanting is allowed to ionize, further accelerate certain using the foreign atom or molecule of high-energy particle bombardment doping
Energy is emitted directly toward it inside silicon wafer, then makes impurity activation by annealing, achievees the purpose that doping.Ion implanting can protect
Consistency, the repeatability of demonstrate,proving junction depth, so that it is guaranteed that the consistency of device parameters, and ion implanting can do concentration distribution
It is very steep.In an embodiment of the present invention, the base contact area 8 is formed by ion implantation technology, in the present embodiment, institute
The impurity for stating the injection of base contact area 8 is boron difluoride, and implantation dosage is 2E15~5E15/cm2, Implantation Energy be 40~
60KeV.In other embodiments, the impurity in the base contact area 8 can also be boron, indium, gallium plasma.
Please refer to attached drawing 8, execute step S06: formed dielectric layer 9, contact hole (not shown), emitter 10, base stage 11 and
Collector 12.Further, in certain embodiments of the present invention, the material silica of the dielectric layer 9, aluminium oxide,
Silicon oxynitride, one of or arbitrarily a variety of combination such as nitrogen oxide, preferably, the material of the dielectric layer 9 is titanium dioxide
Silicon, thickness are preferably 6000A.The dielectric layer 9 is formed in 2 upper surface of epitaxial layer, is covered in the injection region 3, base area
The upper surface of the upper surface and the first isolation channel 5 and the second isolation channel 6 of contact zone 8 and emitter region 7.Further, institute is grown
State dielectric layer 9 can for high-temperature oxidation, growth temperature between 800~1000 DEG C, growth thickness 1800~2200A it
Between.In other embodiments, the dielectric layer 9 can also be formed by depositing technics, such as CVD method.Then
Again by photoetching and etching technics, contact hole is formed on the dielectric layer 9, the contact hole includes base stage contact hole and transmitting
Pole contact hole.Further, it is formed by semicon-ductor structure surface splash-proofing sputtering metal in above-mentioned steps, then passes through photoetching and etching
Form emitter 10 and base stage 11, wherein the emitter 10 is electrically connected by the emitter contact hole and the emitter region 7
It connects, the base stage 11 is electrically connected by base stage contact hole with the base contact area 8；Further, separate to the substrate 1
The side of the epitaxial layer 2 carries out that grinding processing is thinned, then re-evaporation metal, and then forms collector 12, the collector
12 are electrically connected with the substrate 1.It is appreciated that the various the present invention by be located at the back side the substrate 1 carry out reduction processing,
Making the triode final thickness is only that further reduced the resistance of collector 12 between 100~150 μm, is not only met big
The requirement of power, while it can also work in high frequency environment.
Attached drawing 9 is please referred to, further, after forming base stage 11 and emitter 10, the method also includes: to above-mentioned
Step is formed by semicon-ductor structure surface and is passivated the deposit of layer 13, then by lithography and etching, by emitter 10 and base
The extraction location of pole 11 is opened.The material of the passivation layer 13 is the phosphorosilicate glass containing 3%, can be very good protection outside water
The adverse effects such as vapour, scuffing, contamination improve the reliability of device.
Please continue to refer to attached drawing 9, further, after forming collector 12, the method also includes: to the half of formation
Conductor structure carries out scribing, to expose the side of the semiconductor structure；In the extremely described collection in the side of the semiconductor structure
Electrode 12 coats conductive glue 14 far from the surface of 1 side of substrate；By the conductive glue 14 by collector 12 and gold
Belong to frame 15 to connect.It is understood that the purpose for carrying out scribing to the semiconductor structure of formation is single one by one in order to be formed
Chip.Also it is understood that, (i.e. collector 12 is far from described from the lower end surface of the semiconductor structure for the conductive glue 14
The surface of substrate 1) overflow is to semiconductor structure side, preferably, the conductive glue 14 includes silver powder 90%~95%, it can
To obtain fabulous electric conductivity.Preferably, 14 dosage of conductive glue will guarantee glue from bottom overflow to chip side
Face, covers the side of the injection region 3 in whole or in part, and overflow degree is preferably the 70~85% of entire chip thickness.It can
To understand, the collector 12 of triode of the present invention is not only drawn by back metal, but also the side (injection region 3) of collector 12
It is drawn by conductive glue connection, so that the ability that collector 12 collects electronics greatly improves, therefore 12 electric current of collector is improved,
So the amplification factor of triode also increases accordingly, the amplification factor than conventional high-tension triode improves 80%.
Referring to attached drawing 9, the embodiment of the present invention provides a kind of triode, and the triode includes: the first conductive-type
The substrate 1 of type, in the epitaxial layer 2 of 1 surface growth regulation of substrate, one conduction type；It is formed in the marginal zone of the epitaxial layer 2
The injection region 3 of first conduction type in domain and be formed in 2 intermediate region of epitaxial layer the second conduction type base area 4；
The first isolation channel 5 and the second isolation channel 6 being formed in the base area 4, wherein second isolation channel 6 interval be formed in it is described
The side of first isolation channel 5 and adjacent with the injection region 3；First isolation channel 5 is formed in far from second isolation channel 6
The emitter region 7 of first conduction type of 4 region surface of base area of side；Be formed in first isolation channel 5 with described second every
Base contact area 8 from the second conduction type between slot 6；Dielectric layer 9, contact hole, emitter 10, base stage 11 and collector
12。
It is appreciated that first isolation channel 5 and the isolation of the second isolation channel 6 between each pole of triode provided by the invention,
The generation laterally punctured thoroughly is avoided, when emitter junction and collector junction are in reverse-biased, with the increase of voltage, is exhausted
Area can only longitudinally extend downwards, therefore depletion region can extend very wide, and high breakdown voltage is obtained with this.Simultaneously because using
Deep trench isolation, no need to increase spacing for the exit of each pole in the surface of device, therefore the surface area of device does not increase, this is just improved
Device integrated level, be conducive to batch production and cost reduction.
Further, carrier of the substrate 1 as the device, primarily serves the effect of support.Under normal circumstances, institute
The material for stating substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., and in the present embodiment, the substrate 1 is
Silicon substrate, silicon are most common, cheap and stable performance semiconductor material.In certain embodiments of the present invention, the lining
Bottom 1 be N-type heavy doping substrate, the resistivity of the substrate 1 between 0.001~0.01 Ω * cm, thickness 220~280 μm it
Between, in the present embodiment, the Doped ions of the substrate 1 are specially phosphonium ion, certainly, in other embodiments, described
The Doped ions of substrate 1 can be also other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, the substrate 1 is as this
Invent the collector contact area of the triode proposed.The pressure resistance of the thickness and concentration and device of the epitaxial layer 2 is closely related,
In some embodiments of the present invention, 2 resistivity of epitaxial layer is between 25~50 Ω * cm, and thickness is between 15~18 μm.It is excellent
Choosing, the epitaxial layer 2 is formed by the relatively simple homoepitaxy of technique, i.e., the material and the substrate 1 of the described epitaxial layer 2
Material it is identical, when the material of substrate 1 be silicon when, the material of the epitaxial layer 2 is also silicon.The epitaxial layer 2 can be using outer
Epitaxial growth is formed in the upper surface of the substrate 1.The doping type phase of the doping type of the epitaxial layer 2 and the substrate 1
Together, in the present embodiment, the substrate 1 is n-type doping, and the epitaxial layer 2 is n-type doping, in other embodiments, if
The substrate 1 is p-type doping, and the epitaxial layer 2 is p-type doping.In the present embodiment, the Doped ions of the epitaxial layer 2
Specially phosphonium ion, in other embodiments, the Doped ions of the epitaxial layer 2 can also for other pentavalents such as arsenic or antimony from
Son.More specifically, the epitaxial growth method can for vapor phase epitaxial growth, liquid phase epitaxial process, be evaporated in vacuo growth method,
High-frequency sputtering growth method, molecular beam epitaxial growth method etc., preferably chemical vapor deposition method (or vapor phase epitaxial growth),
Chemical vapor deposition method is a kind of to react and deposit into solid thin layer or film on solid matrix surface with vapor reaction raw material
Technique, be a kind of epitaxial growth method of the transistor of comparative maturity, this method sprays silicon and doped chemical in the substrate 1
On, uniformity is reproducible, and step coverage is excellent.The complete of silicon materials can be improved in chemical vapor deposition method simultaneously
Beauty improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.It is to be appreciated that described
Collecting zone is made as collecting zone of the invention, by using epitaxy technique in epitaxial layer 2, and integral thickness is highly uniform, than passing
System is easier to control using the collecting zone of buried structure.It should also be noted that, triode provided by the invention due to current collection
Area's resistivity is higher, can undertake very high voltage, while its thickness does not increase, therefore its conducting resistance when triode operation
It will not significantly increase, therefore further improve 12 electric current of collector, obtain more preferably working characteristics.
Further, the process for forming the injection region 3 of the first conduction type and the base area 4 of the second conduction type can be with
Are as follows: the injection region 3 of the first conduction type is formed on the 2 fringe region surface of epitaxial layer by photoetching, ion implantation technology；?
2 surface region of epitaxial layer of 3 inside of injection region forms the base area 4 of the second conduction type；Pass through thermal diffusion process pair
The injection region 3 and the base area 4 are promoted, and the quantity of the injection region 3 can be one or more.In this embodiment party
In formula, the injection element of the injection region 3 is P elements, and implantation dosage is 4E12~6E12/cm2Between, Implantation Energy is 120
Between~150KeV.In the present embodiment, the injection element of the base area 4 is boron, and implantation dosage is in 6E12~8E12/cm2
Between, Implantation Energy is between 100~120KeV.In the present embodiment, the diffusion temperature of the thermal diffusion 1100~
Between 1250 DEG C, thermal process continues 200~350 minutes, so that the junction depth of the base area 4 and the injection region 3 reaches 8~10 μ
M, the purpose for carrying out thermal diffusion process be to form certain Impurity Distribution, and device is made to have reasonable surface concentration and junction depth,
And this is also the main foundation of determining process conditions, the important process control parameter of diffusion has: temperature, time and gas flow
Deng.It is to be appreciated that the base area 4 is injected using whole face, diffuseed to form, thickness is also highly uniform, and therefore, the present invention mentions
The transistor parameter stability of confession is far superior to conventionally produced triode, is particularly suitable for producing in enormous quantities.
Further, the first isolation channel 5 and the second isolation channel 6 formed in the base area 4 may include: to pass through photoetching
And dry etch process, go out first groove and second groove in 4 surface etch of base area, the second groove interval is formed in
The outside of the first groove and adjacent with the injection region 3；The filled media material in the first groove and second groove,
And then it is respectively formed the first isolation channel 5 and the second isolation channel 6.Specifically, the dielectric material is silica, in filled media
After material, in order to form a complete surface, the method for chemical mechanical grinding can be used the dioxy of excess surface later
SiClx removal, the method for chemical mechanical grinding is the conventional techniques of those skilled in the art, is no longer repeated one by one again.?
In other embodiments, the dielectric material can also be that aluminium oxide, silicon oxynitride, nitrogen oxide etc. are one of or any a variety of
Combination.More specifically, the dry etching performs etching the base area 4 using the combination gas of chlorine, boron chloride, into
And steep silicon groove shape can be formed.It is understood that the quantity of first isolation channel 5 and second isolation channel 6
It can be for 1 or multiple.
Further, further, the emitter region 7 is formed by ion implanting, forms the transmitting in ion implanting
Before area 7, need to realize that the photoetching offset plate figure for the emitter region 7 that definition needs to form, the above process are referred to as photoetching, then with institute
Photoetching offset plate figure is stated as exposure mask, the emitter region 7, in the present embodiment, the transmitting are formed by ion implantation technology
7 implanted dopant of area is arsenic element, and implantation dosage is in 1E16~1.5E16/cm2Between, Implantation Energy is between 80~100KeV.
Further, the base contact area 8 is for realizing well connecing between subsequent base stage 11 and the base area 4
Touching, guarantees the reliability of device；The base contact area 8 is formed by doping process, and the doping process includes thermal diffusion method
And ion implantation, thermal diffusion are earliest using being also simplest doping process, it is transported using the diffusion of atom at high temperature
It is dynamic, it spreads foreign atom into silicon from dense impurity source and forms certain distribution.Thermal diffusion method is usually divided to two
Step carries out: pre-deposited and main diffusion.Pre-deposited is at high temperature using impurity sources such as boron, phosphorus to the doping window on silicon wafer
Mouth is diffused, and layer but the impurity layer with higher concentration are formed at window.Main diffusion is to utilize pre-deposited institute shape
At surface impurity layer do impurity source, the process at high temperature spreading this layer of impurity into silicon body, the time usually promoted compared with
It is long.And ion implanting is allowed to ionize, further accelerate to one surely using the foreign atom or molecule of high-energy particle bombardment doping
Amount, is emitted directly toward it inside silicon wafer, then makes impurity activation by annealing, achievees the purpose that doping.Ion implanting can guarantee
Consistency, the repeatability of junction depth, so that it is guaranteed that the consistency of device parameters, and concentration distribution can be made by ion implanting
Suddenly.In an embodiment of the present invention, the base contact area 8 is formed by ion implantation technology, in the present embodiment, described
The impurity that base contact area 8 is injected is boron difluoride, and implantation dosage is 2E15~5E15/cm2, Implantation Energy is 40~60KeV.
In other embodiments, the impurity in the base contact area 8 can also be boron, indium, gallium plasma.
Further, further, in certain embodiments of the present invention, the material silica of the dielectric layer 9,
Aluminium oxide, silicon oxynitride, one of or arbitrarily a variety of combination such as nitrogen oxide, preferably, the material of the dielectric layer 9 is
Silica, thickness are preferably 6000A.The dielectric layer 9 is formed in 2 upper surface of epitaxial layer, is covered in the injection region
3, the upper surface of the upper surface and the first isolation channel 5 and the second isolation channel 6 of base contact area 8 and emitter region 7.Further,
Grow the dielectric layer 9 can for high-temperature oxidation, growth temperature between 800~1000 DEG C, growth thickness 1800~
Between 2200A.In other embodiments, the dielectric layer 9 can also be formed by depositing technics, such as CVD method
Deng.Then contact hole is formed on the dielectric layer 9 by photoetching and etching technics again, the contact hole includes base stage contact
Hole and emitter contact hole.Further, it is formed by semicon-ductor structure surface splash-proofing sputtering metal in above-mentioned steps, then passes through light
It carves and etching forms emitter 10 and base stage 11, wherein the emitter 10 passes through the emitter contact hole and the transmitting
Area 7 is electrically connected, and the base stage 11 is electrically connected by base contact hole with the base contact area 8；Further, then to the lining
Bottom 1 carries out that grinding processing is thinned far from the side of the epitaxial layer 2, then re-evaporation metal, and then forms collector 12, described
Collector 12 is electrically connected with the substrate 1.It is appreciated that the various the present invention is by subtracting the substrate 1 for being located at the back side
Thin processing, making the triode final thickness is only that further reduced the resistance of collector 12, not only between 100~150 μm
Meet powerful requirement, while it can also work in high frequency environment.
Further, although preferred embodiments of the present invention have been described, but those skilled in the art once learn
Basic creative concept, then additional changes and modifications may be made to these embodiments.So appended claims are intended to solve
It is interpreted as including preferred embodiment and all change and modification for falling into the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of production method of triode, which is characterized in that the described method includes:
The substrate of the first conduction type is provided, in the epitaxial layer of one conduction type of substrate surface growth regulation；
The injection region of the first conduction type is formed in the fringe region of the epitaxial layer and in epitaxial layer intermediate region shape
At the base area of the second conduction type；
The first isolation channel and the second isolation channel are formed in the base area region, second isolation channel interval is formed in described
The side of one isolation channel and adjacent with the injection region；
The hair of the first conduction type is formed far from the base area region surface of second isolation channel side in first isolation channel
Penetrate area；
The base contact area of the second conduction type is formed between first isolation channel and second isolation channel；
Form dielectric layer, contact hole, emitter, base stage and collector.
2. the production method of triode as described in claim 1, which is characterized in that formed in the fringe region of the epitaxial layer
The injection region of first conduction type and the epitaxial layer intermediate region formed the second conduction type base area specifically include:
The injection of cricoid first conduction type is formed in the epilayer edges region surface by photoetching, ion implantation technology
Area；
Epi-layer surface region on the inside of the injection region forms the base area of the second conduction type；
The injection region and the base area are promoted by thermal diffusion process.
3. the production method of triode as claimed in claim 2, which is characterized in that form the first isolation channel in the base area
And second isolation channel specifically include:
By photoetching and dry etch process, first groove and second groove, second ditch are etched in the base region surface
Slot interval is formed in the side of the first groove and abuts with the injection region；
The filled media material in the first groove and second groove, and then it is respectively formed the first isolation channel and the second isolation
Slot.
4. the production method of triode as described in claim 1, which is characterized in that formed dielectric layer, contact hole, emitter,
Base stage and collector specifically include:
Dielectric layer is formed in the epi-layer surface；
Form contact hole on the dielectric layer by photoetching and etching technics, the contact hole include emitter contact hole and
Base stage contact hole；
In the dielectric layer surface splash-proofing sputtering metal, emitter and base stage are formed by photoetching and etching technics, the emitter is logical
It crosses the emitter contact hole to be electrically connected with the emitter region, the base stage passes through base stage contact hole and base contact regions electricity
Connection；
The substrate is carried out grinding processing, then re-evaporation metal is thinned far from the side of the epitaxial layer, so formed with
The collector of the substrate electrical connection.
5. the production method of triode as described in claim 1, which is characterized in that the method also includes:
Scribing is carried out to the semiconductor structure of formation, to expose the side of the semiconductor structure；
In the side of the semiconductor structure, the extremely described collector coats conductive glue far from the surface of the one side of substrate；
Collector is connect with metal framework by the conductive glue.
6. a kind of triode, which is characterized in that the triode includes:
The substrate of first conduction type, in the epitaxial layer of one conduction type of substrate surface growth regulation；
It is formed in the injection region of the first conduction type of the fringe region of the epitaxial layer and is formed among the epitaxial layer
The base area of second conduction type in region；
The first isolation channel and the second isolation channel being formed in the base area, wherein second isolation channel interval be formed in it is described
The side of first isolation channel and adjacent with the injection region；
It is formed in the first conduction type of base area region surface of first isolation channel far from second isolation channel side
Emitter region；
It is formed in the base contact area of the second conduction type between first isolation channel and second isolation channel；
Dielectric layer, contact hole, emitter, base stage and collector.
7. triode as claimed in claim 6, which is characterized in that the resistivity of the substrate 0.001~0.01 Ω * cm it
Between, thickness is between 220~280 μm.
8. triode as claimed in claim 6, which is characterized in that filling in first isolation channel and second isolation channel
There is dielectric material, the dielectric material is silica.
9. triode as claimed in claim 6, which is characterized in that the width of second isolation channel of the first isolation channel is 1.5
Between~2 μm, depth is deep 60%~75% in the base area.
10. triode as claimed in claim 6, which is characterized in that the dielectric layer with a thickness of 6000A.
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| CN111969052A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Bipolar junction transistor with multiple grooves |
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| CN111969052A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Bipolar junction transistor with multiple grooves |
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