CN109765412A - A method of the accurate positioning trigger position based on programmable circuit - Google Patents
A method of the accurate positioning trigger position based on programmable circuit Download PDFInfo
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Abstract
The method for the accurate positioning trigger position based on programmable circuit that the invention discloses a kind of, comprising: the when base gear and Time delay of detection data collection analysis quasi-instrument；Judge whether user changes time base variable gear or Time delay, if so, carrying out software parameter setting, and on-site programmable gate array FPGA is sent to by bus communication, restarts acquisition Interpolation Process；Processor obtains sampled data and according to combination of channels situation, and real-time sampling data is combined into array；When data collection and analysis quasi-instrument is in interpolation gear, real-time interpolation is carried out, then carries out trigger point repositioning, adjusts interpolation point, the waveform generated is enabled to carry out stablizing display as reference point using triggering level.The pure hardware realization interpolation of the disclosure and triggering are accurately positioned, and short time consumption is small.The scheme division of labor is clear, gives full play to the strong feature of software computing capability in conjunction with the requirement of real-time of oscillograph according to the execution speed degree of software and hardware, calculates the key parameter of hardware interpolation needs.
Description
Technical field
This disclosure relates to signal processing technology field, more particularly to the accurate positioning trigger position based on programmable circuit
Method.
Background technique
In the data collection and analysis quasi-instrument such as oscillograph, reduces waveform sampling rate and removed multidata process referred to as letter
Number extraction, improve waveform sampling rate and increase the processes of data and be known as the interpolation of signal.The data point that interpolation representation is acquired in ADC
Between calculated value is inserted into according to specific algorithm, achieve the purpose that improve sample rate clearly to analyze signal detail.
There are three types of common interpolation methods: linear interpolation keeps interpolation and Sine Interpolation.
As shown in fig. 6, Sine Interpolation is also " sin (x)/x " interpolation, it is most common interpolation method.This is based on any
Waveform is all the combination that can resolve into sine wave infinitely.By way of sinusoidal interpolation, it can compare accurately and smoothly
Restore true waveform signal.Sampling point is connected using curve, versatility is stronger.It utilizes Mathematical treatment, in practical sample spacings
In calculate result.This method is bent signal waveform, is allowed to generate the common waveform more more real than pure square wave and pulse.
In when extracting gear in oscillograph, since acquisition data are enough, realize that triggering positioning is relatively simple.It inserts
Quite different under value mode, interpolation can generate new data later, need to carry out again the data after interpolation according to triggering level
Positioning.Interpolation is carried out to undersampled signal frequently with Sine Interpolation in oscillograph, when Interpolation Process uses software approach, software is read
Take acquired data, interpolation carried out to the data after acquisition by turn, in the process of interpolation to pre-trigger length is met after
Data carry out triggering level positioning, all data are shown to screen centered on triggering level anchor point after the completion of interpolation
On.It when software interpolation, carries out by turn, interpolation takes a long time, and when especially oscillograph multichannel is opened simultaneously, delay effect is more
Obviously, the waveform capture rate that can seriously reduce oscillograph, omits certain key signals.
In conclusion the main problem that the application is solved is: software carries out interpolation and is accurately positioned trigger position time-consuming
It is larger, it causes the waveform capture rate of oscillograph lower, is easy to omit crucial accidental signal.
Summary of the invention
In order to solve the deficiencies in the prior art, embodiment of the disclosure provides the accurate positioning based on programmable circuit
The method of trigger position, in terms of with the consistency in structure, be easy to software and hardware coordinated control and cross-platform
Transplanting, can reinforce the reliability of product while improving oscilloscope waveform capturing rate, shorten the lead time of product.
To achieve the goals above, the application uses following technical scheme:
The method of accurate positioning trigger position based on programmable circuit, comprising:
The when base gear and Time delay of detection data collection analysis quasi-instrument；
Judge whether user changes time base variable gear or Time delay, if so, carrying out software parameter setting, and passes through bus
Communication is sent to on-site programmable gate array FPGA, restarts acquisition Interpolation Process；
FPGA obtains sampled data and according to combination of channels situation, and real-time sampling data is combined into array；
When data collection and analysis quasi-instrument is in interpolation gear, real-time interpolation is carried out, it is again fixed then to carry out trigger point
Position adjusts interpolation point memory, and the waveform generated is enabled to carry out stablizing display as reference point using triggering level.
As the further technical solution of the application, the on-site programmable gate array FPGA is adopted when acquiring data
Collect sufficient amount of data, to meet the needs an of storage depth and the needs of required interpolation point number.
As the further technical solution of the application, the on-site programmable gate array FPGA is according to data collection and analysis
Interpolation gear locating for quasi-instrument reads adopting in BRAM real-time storage area according to interpolation multiple stepping-in amount in Sine Interpolation method
Collect data, the DSP operation unit relied in on-site programmable gate array FPGA and the ROM progress interpolation for storing interpolation coefficient, and
Data after interpolation are stored into FIFO.
Data volume point as the further technical solution of the application, when triggering level repositions after interpolation, after interpolation
Cloth needs to relocate the data after interpolation between front and back real-time sampling point, finds in interpolation point closest to triggering
Position where the point of level, and the reference position shown for waveform is put with this.
As the further technical solution of the application, specifically after interpolation before triggering level repositioning, it is thus necessary to determine that
Parameter include:
Pre_length, pre-trigger stage sample array length, refer to meet storage depth requirement, oscillograph pre-trigger rank
Section needs the array quantity acquired；
Pre_offset, pre-trigger sample array offset, refer to that, to meet storage depth requirement, the pre-trigger stage first is adopted
The offset of sample array；
Post_length, it is rear to trigger stage sampling array length, refer to meet storage depth requirement, is triggered after oscillograph
Stage needs the array quantity acquired；
Post_offset, rear triggering sampling array offset, refers to meet storage depth requirement, it is rear trigger the stage last
The offset of a sampling array；
Insert_tirg_num_begin, the process that is accurately positioned open corresponding interpolation point number, and the parameter is for instructing
FPGA finds accurate trigger position enable signal, i.e., starts to carry out accurate positioning process after interpolation point counting reaches the value；
Insert_assist_num, be accurately positioned process auxiliary abandon point a number, due to when base gear and triggering when it is extended
The randomness set, to generate certain number of interpolation point, the interpolation non-whole situation of counting that will cause needs sometimes occurs, for
Such case, this programme are calculated by software and cause the points of more interpolation due to the influence of this non-integer, and be arranged parameter to
FPGA triggering repositioning module.The parameter and Trigged_num_of_inserted (can be met triggering item as needed by FPGA
Positional shift where the interpolation point of part between two real-time sampling points) it is added together, (Insert_ is abandoned before forming fluorescence
Assist_num+Trigged_num_of_inserted) number point, to guarantee waveform stabilization in trigger position；
Insert_tirg_num_end, accurate positioning process terminate corresponding interpolation point number, and the parameter is for instructing
FPGA terminates level comparison procedure after interpolation counter reaches the numerical value, it is ensured that the trigger point of searching is located at two sampled point of front and back
Between；
Trig_level_insert is accurately positioned dedicated relatively threshold value, the numerical value of interpolation point and the parameter is compared
Compared with finding and crossing the point of the parameter for the first time is the accurate trigger position to be found.When rising edge, FPGA is by Trig_
Level_insert is set as the sluggish high level Trig_high_level of triggering；When failing edge triggers, by Trig_level_
Insert is set as the sluggish low level Trig_low_level of triggering.
The embodiment of the present application discloses the system of the accurate positioning trigger position based on programmable circuit, comprising:
Acquisition state controls machine, and base gear and Time delay when according to locating for data collection and analysis quasi-instrument, acquisition is enough
The data of quantity to meet the needs an of storage depth and the needs of required interpolation point number, and store into FPGA BRAM
Real-time storage area；
Interpolation control module, according to interpolation gear locating for data collection and analysis quasi-instrument, in the method for Sine Interpolation, according to
Interpolation multiple stepping-in amount reads the acquisition data in BRAM real-time storage area, and the DSP operation unit and storage relied in FPGA is inserted
The ROM of value coefficient carries out interpolation, and the data after interpolation are stored into FIFO；
Triggering level repositions module after interpolation, and the data distribution after interpolation is between front and back real-time sampling point, to interpolation
Data afterwards are relocated, and are found closest to the position where the point of triggering level in interpolation point, and using this point as waveform
The reference position of display.
As the further technical solution of the application, triggering level repositions module after realizing interpolation after the interpolation
When triggering level repositions, the step of use are as follows:
According to interpolation gear, interpolation multiple and software parameter are set；
FPGA carries out interpolation arithmetic according to interpolation multiple, real-time reception sampled data, exports interpolation point, gives interpolation point ratio
Compared with device, which counts the number of interpolation point, when the number be in design parameter Insert_tirg_num_begin and
When between Insert_tirg_num_end, enable signal is provided, gives interpolation level comparator；
Interpolation point level comparator in FPGA in real time compares interpolation point and the Trig_level_insert of setting
Compared with finding triggering interpolation point.Such as when rising edge triggering, under the premise of enable signal is effective, if the value of previous interpolation point
Less than Trig_level_insert, and when the value of current interpolation point is greater than or equal to Trig_level_insert, that is, think to look for
Triggering interpolation point is arrived.At this point, recording the interpolation number of this two sampled point of interpolation point distance, it is denoted as Trigged_num_of_
inserted；
FPGA control logic abandons extra interpolation point, monitors interpolation point quantity in real time, after reaching screen display needs, opens
The arrangement of beginning interpolation storing data, abandons extra interpolation point, enables trigger point corresponding with trigger position on screen；
The interpolation point quantity for needing to abandon is Insert_assist_num+Trigged_num_of_inserted, practical
It reads to carry out by the way of control using FIFO when execution, the accurate triggering positioning after completing an interpolation at this time；
The superposition of fluorescence frequency starts to fold remaining interpolation point reading progress frequency after abandoning extra interpolation point
Add, further generates display waveform.
A kind of data collection and analysis quasi-instrument is realized using the system of the accurate positioning trigger position based on programmable circuit
To being accurately positioned trigger position after output signal interpolation.
Compared with prior art, the beneficial effect of the disclosure is:
Disclosure one kind is based on programmable logic device and realizes to acquisition data progress hardware interpolation and complete accurate triggering
Positioning.The present invention repositions the realization of this technology for interpolation and after triggering, and gives full play to the computing capability of software and may be programmed
The parallel execution of logical device and assembly line continuous operation feature.Interpolation and repositioning framework of the invention is wanted according to real-time
It asks, the not high operation of requirement of real-time is all completed by software, for requiring the part of quick execution all to be completed by hardware.
Triggering level localization method provided by the invention, in terms of with the consistency in structure, be easy to software and hardware association
Regulation system and cross-platform transplanting, can reinforce the reliability of product while improving oscilloscope waveform capturing rate, shorten product
Lead time.
The pure hardware realization interpolation of the disclosure and triggering are accurately positioned, and short time consumption is small.The scheme division of labor is clear, according to software and hardware
Execution speed degree give full play to the strong feature of software computing capability in conjunction with the requirement of real-time of oscillograph, calculate hardware
The key parameter that interpolation needs.Interpolation Process then uses that interpolation and triggering level are executed based on programmable logic hardware is accurately fixed
Position process, effectively promotes oscilloscope waveform capturing rate.
Disclosure scenario-frame is rigorous, clear process, is easy to cross-platform transplanting.This set of interpolation search and touching designed by the present invention
Generate electricity flat accurate positioning process, contains efficient structure composition, clearly executes process, and experiment proves that is truly feasible
's.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.
Fig. 1 is that the interpolation structure of embodiment of the present disclosure is illustrated；
Fig. 2 is that the single channel of embodiment of the present disclosure triggers positional parameter design；
Fig. 3 is the four-way combination triggering positional parameter design of embodiment of the present disclosure；
Fig. 4 be embodiment of the present disclosure triggering after reposition scheme；
Fig. 5 is the interpolation and positioning flow of embodiment of the present disclosure；
Fig. 6 is the Sine Interpolation schematic diagram of embodiment of the present disclosure；
Schematic diagram is repositioned after triggering when Fig. 7 is the rising edge triggering of embodiment of the present disclosure.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
This programme is strong according to software computing capability, and hardware executes the fast feature of speed, and incorporating parametric design, structure are set
Meter, accurate triggering when for interpolation gear position expansion, effectively promote interpolation locating speed and oscilloscope waveform capturing rate.This
The functional block diagram such as Fig. 1 signal provided is invented, it is big that interpolation and repositioning process mainly execute two by software calculating parameter and hardware
Part forms.
The technical solution part of the application needs to carry out parameter designing in software aspects, for convenience of explanation the skill of the application
Art scheme, Fig. 2 give and acquire being associated with for array and design parameter under single channel, and Fig. 3 gives four-way acquisition data combination
When acquisition array signal is associated with design parameter.
It include parameter 1. design parameter relates generally to pre-trigger stage, corresponding length of rear triggering stage and array offset
Pre_length,Pre_offset,Post_length,Post_offset.These parameters are mainly used for instructing FPGA programmable
Circuit acquires the data of full storage depth, such as 600 points of one acquisition.Wherein, Pre_length, Post_length can
The coarse adjustment of pre-trigger length and rear triggering length is carried out, the parameter is every to increase by 1, then the corresponding points for increasing an array length,
It is 4 points when single channel, is 16 points when four-way combines.And Pre_offset, Post_offset can be acquired the thin of points
It adjusts, the acquisition points acquisition that can satisfy random length requires.The flexible setting of this acquisition points be after interpolation and interpolation again
A premise guarantee has been done in positioning.
2. carrying out the combination of channel data in oscillograph often to improve sample rate, acquisition array when four-way combines is such as
Fig. 3 illustrates, and includes 16 data points under each sampling clock.In this case parameter setting, with step 1. in design join
Number compatibility, programmable circuit realize the control of acquisition points according to composite marking.It should be pointed out that this compatibility is simultaneously
Allow for the consistency in subsequent structural design.
3. triggering level repositions parameter designing after interpolation, triggering level repositioning module will be described in detail after interpolation.
In a kind of typical examples of implementation of the application, the system of the accurate positioning trigger position based on programmable circuit, side
Case is constituted, as shown in Figure 1, scheme interpolation and repositioning control machine, BRAM real-time data memory area, interpolation control comprising acquisition state
Triggering level repositioning module composition after molding block, interpolated data memory, interpolation.
Acquisition state controls machine: base gear and Time delay when according to locating for oscillograph acquire sufficient amount of data, with
Meet the needs an of storage depth and the needs of required interpolation point number.
Interpolation control module: the interpolation gear according to locating for oscillograph, in " sin (x)/x " method, according to interpolation multiple stepping
Amount reads the acquisition data in BRAM real-time storage area, relies on DSP operation unit (execute plus, multiplication) and ROM in FPGA
(storage interpolation coefficient) carries out interpolation, and the data after interpolation are stored into interpolated data memory FIFO.
Triggering level repositions module after interpolation: the data volume after interpolation is distributed between the real-time sampling point of front and back.At this time
It needs to relocate the data after interpolation, find closest to the position where the point of triggering level in interpolation point, and with
This point is the reference position that waveform is shown, is just avoided that the shaking of screen display waveform, reaches pinpoint purpose.
Scheme is repositioned after the present invention triggering of citing description below: as shown in Figure 7, it is assumed that storage depth 600, pre-trigger
Length is 300 points, and the rear length that triggers is 300 points, the non-combined mode in channel, 40 times of interpolation gears, rising edge triggering, triggering level
It is 520.So under the example, sampled data need to be combined into the array that 4 points are one group, the essence after interpolation to be realized by FPGA
Really triggering, must determine following parameter according to predetermined formula by software first.In formula, " Numpre" indicate that pre-trigger points, this example are
300 points；"Numpost" points are triggered after expression, this example is 300 points；" β " indicates interpolation multiple, this example is 40 times of interpolation；
" Width " indicates array extent, this example is the non-combined mode in channel, which is 4；" ┌ ┐ " expression rounds up, " └ ┘ " table
Show downward rounding；" % " indicates remainder operation, and " 16 " refer to complete interpolation arithmetic and need to prepare 16 points in advance.
Insert_assist_num=Insert_tirg_num_begin-Numpre (6)
Insert_tirg_num_end=Insert_tirg_num_begin+ β (7)
Pre_length is to sample array length in the pre-trigger stage, is referred to meet storage depth requirement, oscillograph pre-trigger
Stage needs the array quantity acquired.In conjunction with exemplary scene and calculation formula (1), calculated value 7.
Pre_offset is that pre-trigger samples array offset, is referred to meet storage depth requirement, the pre-trigger stage first
Sample the offset of array.In conjunction with exemplary scene and calculation formula (2), calculated value 1.
The triggering stage samples array length after Post_length is, refers to meet storage depth requirement, triggers after oscillograph
Stage needs the array quantity acquired.In conjunction with exemplary scene and calculation formula (3), calculated value 7.
Post_offset be after triggering sampling array offset, refer to meet storage depth requirement, it is rear trigger the stage last
The offset of a sampling array.In conjunction with exemplary scene and calculation formula (4), calculated value 1.
Insert_tirg_num_begin is that accurate positioning process opens corresponding interpolation point number, and the parameter is for referring to
It leads FPGA and finds accurate trigger position enable signal, i.e., start be accurately positioned after interpolation point counting reaches the value
Journey.In conjunction with exemplary scene and calculation formula (5), calculated value 320.
Insert_assist_num be accurate positioning process auxiliary abandon point a number, due to when base gear and triggering time delay
The randomness of setting, to generate certain number of interpolation point, the interpolation non-whole situation of counting that will cause needs sometimes occurs.Needle
To such case, this programme is calculated by software and causes the points of more interpolation due to the influence of this non-integer, and be arranged parameter to
FPGA triggering repositioning module.The parameter and Trigged_num_of_inserted (can be met triggering item as needed by FPGA
Positional shift where the interpolation point of part between two real-time sampling points) it is added together, (Insert_ is abandoned before forming fluorescence
Assist_num+Trigged_num_of_inserted) number point, to guarantee waveform stabilization in trigger position.In conjunction with
Exemplary scene and calculation formula (6), calculated value 20.
Insert_tirg_num_end is that accurate positioning process terminates corresponding interpolation point number, and the parameter is for instructing
FPGA terminates level comparison procedure after interpolation counter reaches the numerical value, it is ensured that the trigger point of searching is located at two sampled point of front and back
Between.In conjunction with exemplary scene and calculation formula (7), calculated value 360.
Trig_level_insert is to be accurately positioned dedicated relatively threshold value, and the numerical value of interpolation point and the parameter are compared
Compared with finding and crossing the point of the parameter for the first time is the accurate trigger position to be found.Example is rising edge triggering, according to calculating
Formula (8), setting Trig_level_insert are sluggish high level Trig_high_level i.e. 520 of triggering.
The correct setting of the above parameter is the premise and guarantee repositioned after successfully being triggered.It is fixed in conjunction with the above parameter
Justice, Fig. 4 give the scheme repositioned after triggering.
Interpolation multiple, Pre_length, Pre_offset, Post_length, Post_ is arranged according to interpolation gear in software
Offset, Insert_tirg_num_begin, Insert_assist_num, Insert_tirg_num_end and Trig_
The parameters such as level_insert.
For interpolating module in FPGA according to interpolation multiple, real-time reception sampled data carries out interpolation arithmetic, exports interpolation point,
Give interpolation point comparator.The module counts the number of interpolation point, when the number is in design parameter Insert_tirg_num_
When between begin and Insert_tirg_num_end, enable signal is provided, gives interpolation level comparator.
Interpolation point level comparator in FPGA in real time compares interpolation point and the Trig_level_insert of setting
Compared with.By taking rising edge as an example, under the premise of enable signal is effective, when the value of previous interpolation point is less than Trig_level_
Insert, and the value of current interpolation point be greater than or equal to Trig_level_insert when, that is, think to have found triggering interpolation point.
At this point, recording the interpolation number of this two sampled point of interpolation point distance, it is denoted as Trigged_num_of_inserted.
FPGA control logic abandons extra interpolation point, and interpolating module monitors interpolation point quantity in real time, reaches a screen and show
After needing, starts the arrangement of interpolation storing data, be primarily referred to as abandoning extra interpolation point here, enable trigger point and screen
Trigger position is corresponding on curtain.The interpolation point quantity for needing to abandon is Insert_assist_num+Trigged_num_of_
Inserted reads to carry out by the way of control when reality executes using FIFO.The accurate triggering after an interpolation is completed at this time
Positioning is repositioned with the triggering level that any interpolation multiple may be implemented in this method.
The superposition of fluorescence frequency starts to read remaining interpolation point into frequency to be superimposed after abandoning extra interpolation point
Module further generates display waveform.
Disclosed herein as well is the method for the accurate positioning trigger position based on programmable circuit, protocol procedures, such as Fig. 5 institute
Show.
Whether software real-time detection user changes time base variable or delay, immediately by corresponding parameter according to upper after finding to change
It states rule to be calculated, and FPGA is sent to by bus communication, restart acquisition Interpolation Process.It is assumed that data are past from right side
Left side flows into, and hardware cache acquisition module is according to combination of channels situation, according to above-mentioned acquisition array design scheme, by real-time sampling
Data group synthesizes array.When oscillograph is in interpolation gear, real-time interpolation is carried out by hardware interpolating module, subsequently enters triggering
Module is found in point repositioning, adjusts the memory of interpolation point, enables the waveform generated with triggering level for reference to click-through
Row stablizes display, repositions with the triggering level that any interpolation multiple may be implemented in this method.
The triggering that the key point of the application is parameter designing strategy in software design, designs on the basis of design parameter
Structure and the control of corresponding algorithm are repositioned afterwards and execute process.Wherein, parameter designing refer mainly to acquisition array definition and
The parameter definition of module is repositioned after triggering.In addition, this programme parameter designing is with uniformity in Multichannel combination, after triggering
Repositioning module, which can be compatible with, needs the non-whole situation of sampling number, has stronger flexibility.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (10)
1. the method for the accurate positioning trigger position based on programmable circuit, characterized in that include:
The when base gear and Time delay of detection data collection analysis quasi-instrument；
Judge whether user changes time base variable gear or Time delay, if so, carrying out software parameter setting, and passes through bus communication
It is sent to on-site programmable gate array FPGA, restarts acquisition Interpolation Process；
Processor obtains sampled data and according to combination of channels situation, and real-time sampling data is combined into array；
When data collection and analysis quasi-instrument is in interpolation gear, real-time interpolation is carried out, then carries out trigger point repositioning, is adjusted
Whole interpolation point enables the waveform generated to carry out stablizing display as reference point using triggering level.
2. the method for the accurate positioning trigger position based on programmable circuit as described in claim 1, characterized in that described existing
Field programmable gate array FPGA acquires sufficient amount of data when acquiring data, with meet a storage depth needs and
The needs of required interpolation point number.
3. the method for the accurate positioning trigger position based on programmable circuit as described in claim 1, characterized in that described existing
Field programmable gate array FPGA interpolation gear according to locating for data collection and analysis quasi-instrument, in Sine Interpolation method, according to interpolation
Multiple stepping-in amount reads the acquisition data in BRAM real-time storage area, relies on the DSP operation in on-site programmable gate array FPGA
Unit and the ROM for storing interpolation coefficient carry out interpolation, and the data after interpolation are stored into FIFO.
4. the method for the accurate positioning trigger position based on programmable circuit as described in claim 1, characterized in that after interpolation
When triggering level repositions, the data volume after interpolation is distributed between the real-time sampling point of front and back, need to the data after interpolation into
Row relocates, and finds closest to the position where the point of triggering level in interpolation point, and put the reference shown for waveform with this
Position.
5. the method for the accurate positioning trigger position based on programmable circuit as claimed in claim 4, characterized in that specifically exist
After interpolation triggering level repositioning before, it is thus necessary to determine that parameter include:
Pre_length samples array length for the pre-trigger stage, refers to meet storage depth requirement, oscillograph pre-trigger stage
The array quantity for needing to acquire；
Pre_offset samples array offset for pre-trigger, refers to meet storage depth requirement, the pre-trigger stage first sampling
The offset of array；
Post_length, stage of triggering after being sample array length, refer to meet storage depth requirement, trigger rank after oscillograph
Section needs the array quantity acquired；
Post_offset, triggering sampling array offset, refers to meet storage depth requirement after being, it is rear trigger the stage the last one
Sample the offset of array；
Insert_tirg_num_begin opens corresponding interpolation point number to be accurately positioned process, and the parameter is for instructing
FPGA finds accurate trigger position enable signal, i.e., starts to carry out accurate positioning process after interpolation point counting reaches the value；
Insert_assist_num abandons point number to be accurately positioned process auxiliary, calculates since the influence of this non-integer is made
At the points of more interpolation, and parameter is set and triggers repositioning module to FPGA.FPGA can as needed by the parameter and
Trigged_num_of_inserted is the positional shift between two real-time sampling points where meeting the interpolation point of trigger condition
It is added together, (Insert_assist_num+Trigged_num_of_inserted) number point is abandoned before forming fluorescence,
To guarantee waveform stabilization in trigger position；
Insert_tirg_num_end terminates corresponding interpolation point number for accurate positioning process, and the parameter is for instructing FPGA
After interpolation counter reaches the numerical value terminate level comparison procedure, it is ensured that the trigger point of searching be located at two sampled point of front and back it
Between；
Trig_level_insert is accurately positioned dedicated relatively threshold value, the numerical value of interpolation point and the parameter is compared, looked for
It is the accurate trigger position to be found to the point for crossing the parameter for the first time, when rising edge, FPGA is by Trig_level_
Insert is set as the sluggish high level Trig_high_level of triggering, and when failing edge triggers, Trig_level_insert is set
It is set to the sluggish low level Trig_low_level of triggering.
6. the method for the accurate positioning trigger position based on programmable circuit as claimed in claim 5, characterized in that after triggering
The specific steps of repositioning are as follows:
According to interpolation gear, interpolation multiple and software parameter are set；
FPGA carries out interpolation arithmetic according to interpolation multiple, real-time reception sampled data, exports interpolation point, gives interpolation point and compare
Device, which counts the number of interpolation point, when the number is in design parameter Insert_tirg_num_begin and Insert_
When between tirg_num_end, enable signal is provided, gives interpolation level comparator；
Interpolation point is compared by the interpolation point level comparator in FPGA with the Trig_level_insert of setting in real time, is looked for
Trigged_num_of_ is denoted as to triggering interpolation point at this point, recording the interpolation number of this two sampled point of interpolation point distance
inserted；
FPGA control logic abandons extra interpolation point, monitors interpolation point quantity in real time, after reaching screen display needs, starts to insert
It is worth the arrangement of storing data, abandons extra interpolation point, enable trigger point corresponding with trigger position on screen；
The interpolation point quantity for needing to abandon is Insert_assist_num+Trigged_num_of_inserted, practical to execute
The mode that Shi Caiyong FIFO reads control carries out, the accurate triggering positioning after completing an interpolation at this time；
The superposition of fluorescence frequency starts to read remaining interpolation point to carry out frequency superposition after abandoning extra interpolation point, into
One step generates display waveform.
7. the method for the accurate positioning trigger position based on programmable circuit as claimed in claim 6, characterized in that on for example
Rise along when, it is and current if the value of previous interpolation point is less than Trig_level_insert under the premise of enable signal is effective
When the value of interpolation point is greater than or equal to Trig_level_insert, that is, think to have found triggering interpolation point.
8. the system of the accurate positioning trigger position based on programmable circuit, characterized in that include:
Acquisition state controls machine, and base gear and Time delay when according to locating for data collection and analysis quasi-instrument acquire sufficient amount
Data, to meet the needs of storage depth and the needs of required interpolation point number, and it is real-time to store into FPGA BRAM
Memory block；
Interpolation control module, according to interpolation gear locating for data collection and analysis quasi-instrument, in the method for Sine Interpolation, according to interpolation
Multiple stepping-in amount reads the acquisition data in BRAM real-time storage area, relies on the DSP operation unit in FPGA and storage interpolation system
Several ROM carries out interpolation, and the data after interpolation are stored into FIFO；
Triggering level repositions module after interpolation, and the data volume after interpolation is distributed between the real-time sampling point of front and back, after interpolation
Data relocated, find closest to the position where the point of triggering level in interpolation point, and with this put for waveform it is aobvious
The reference position shown.
9. the system of the accurate positioning trigger position based on programmable circuit as claimed in claim 8, characterized in that described to insert
The step of triggering level repositions module when triggering level after realizing interpolation repositions after value, use are as follows:
According to interpolation gear, interpolation multiple and software parameter are set；
FPGA carries out interpolation arithmetic according to interpolation multiple, real-time reception sampled data, exports interpolation point, gives interpolation point and compare
Device, which counts the number of interpolation point, when the number is in design parameter Insert_tirg_num_begin and Insert_
When between tirg_num_end, enable signal is provided, gives interpolation level comparator；
Interpolation point is compared by the interpolation point level comparator in FPGA with the Trig_level_insert of setting in real time, is looked for
Trigged_num_of_ is denoted as to triggering interpolation point at this point, recording the interpolation number of this two sampled point of interpolation point distance
inserted；
FPGA control logic abandons extra interpolation point, monitors interpolation point quantity in real time, after reaching screen display needs, starts to insert
It is worth the arrangement of storing data, abandons extra interpolation point, enable trigger point corresponding with trigger position on screen；
The interpolation point quantity for needing to abandon is Insert_assist_num+Trigged_num_of_inserted, practical to execute
The mode that Shi Caiyong FIFO reads control carries out, the accurate triggering positioning after completing an interpolation at this time；
The superposition of fluorescence frequency starts to read remaining interpolation point to carry out frequency superposition after abandoning extra interpolation point, into
One step generates display waveform.
10. a kind of data collection and analysis quasi-instrument, using claim 8-9 it is any it is described based on programmable circuit it is accurate calmly
The system of position trigger position is realized to being accurately positioned trigger position after output signal interpolation.
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