CN109765412B - Method for accurately positioning trigger position based on programmable circuit - Google Patents
Method for accurately positioning trigger position based on programmable circuit Download PDFInfo
- Publication number
- CN109765412B CN109765412B CN201811621541.0A CN201811621541A CN109765412B CN 109765412 B CN109765412 B CN 109765412B CN 201811621541 A CN201811621541 A CN 201811621541A CN 109765412 B CN109765412 B CN 109765412B
- Authority
- CN
- China
- Prior art keywords
- interpolation
- trigger
- points
- point
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a method for accurately positioning a trigger position based on a programmable circuit, which comprises the following steps: detecting a time base gear and trigger delay of a data acquisition and analysis instrument; judging whether a user changes a time base gear or triggers time delay, if so, setting software parameters, sending the software parameters to a Field Programmable Gate Array (FPGA) through bus communication, and restarting an acquisition interpolation process; the processor obtains sampling data and combines the real-time sampling data into an array according to the channel combination condition; when the data acquisition and analysis instrument is in an interpolation gear, real-time interpolation is carried out, then the trigger point is relocated, and the interpolation point is adjusted, so that the generated waveform can be stably displayed by taking the trigger level as a reference point. The method realizes interpolation and triggering accurate positioning by pure hardware, and consumes less time. The scheme is clear in labor division, and key parameters required by hardware interpolation are calculated by fully utilizing the characteristic of strong software computing capability according to the execution speed of software and hardware and combining the real-time requirement of an oscilloscope.
Description
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to a method for accurately positioning a trigger position based on a programmable circuit.
Background
In data acquisition and analysis instruments such as oscilloscopes, the process of reducing the waveform sampling rate and removing excessive data is called signal extraction, and the process of increasing the waveform sampling rate and increasing the data is called signal interpolation. Interpolation means that a calculated value is interpolated between data points collected by the ADC according to a particular algorithm, with the goal of increasing the sampling rate to more clearly analyze the signal details. There are three common interpolation methods: linear interpolation, hold interpolation, and sinusoidal interpolation.
As shown in FIG. 6, sine interpolation is also called "sin (x)/x" interpolation, which is the most commonly used interpolation method. This is based on the combination that any waveform can be decomposed into sine waves an infinite number of times. By means of sine interpolation, the real waveform signal can be restored accurately and smoothly. And the sample points are connected by using the curve, so that the universality is stronger. It uses mathematical treatment to calculate the result in the actual sampling point interval. This method bends the waveform of the signal to produce a more realistic normal waveform than a pure square wave and a pulse.
When the oscilloscope is in the gear extraction position, the trigger positioning is simple to realize due to the fact that the collected data are enough. In the interpolation mode, otherwise, new data is generated after interpolation, and the interpolated data needs to be repositioned according to the trigger level. The oscilloscope usually adopts sine interpolation to interpolate under-sampled signals, when a software method is adopted in the interpolation process, software reads acquired data, interpolates the acquired data bit by bit, triggers level positioning on the data meeting the pre-triggering length in the interpolation process, and displays all data on a screen by taking the trigger level positioning point as a center after the interpolation is finished. During software interpolation, the interpolation is carried out bit by bit, the time consumption of the interpolation is long, especially when multiple channels of the oscilloscope are simultaneously started, the delay effect is more obvious, the waveform capture rate of the oscilloscope is seriously reduced, and certain key signals are omitted.
In summary, the main problems solved by the present application are: the software has the disadvantages of high time consumption for interpolation and accurate positioning of the trigger position, low waveform capture rate of the oscilloscope and easy omission of key accidental signals.
Disclosure of Invention
In order to solve the defects of the prior art, the implementation example of the disclosure provides a method for accurately positioning a trigger position based on a programmable circuit, has structural consistency in the aspects of parameter setting and the like, is easy for software and hardware coordination control and cross-platform transplantation, can enhance the reliability of a product while improving the waveform capture rate of an oscilloscope, and shortens the development cycle of the product.
In order to achieve the purpose, the following technical scheme is adopted in the application:
the method for accurately positioning the trigger position based on the programmable circuit comprises the following steps:
detecting a time base gear and trigger delay of a data acquisition and analysis instrument;
judging whether a user changes a time base gear or triggers time delay, if so, setting software parameters, sending the software parameters to a Field Programmable Gate Array (FPGA) through bus communication, and restarting an acquisition interpolation process;
the FPGA acquires sampling data and combines the real-time sampling data into an array according to the channel combination condition;
when the data acquisition and analysis instrument is in an interpolation gear, real-time interpolation is carried out, then the trigger point is relocated, and the interpolation point memory is adjusted, so that the generated waveform can be stably displayed by taking the trigger level as a reference point.
As a further technical solution of the present application, when the field programmable gate array FPGA collects data, a sufficient amount of data is collected to satisfy a requirement of a storage depth and a requirement of a required number of interpolation points.
As a further technical scheme of the application, the field programmable gate array FPGA reads the acquired data in the BRAM real-time storage area according to the interpolation gear of the data acquisition analysis instrument by a sine interpolation method and according to the interpolation multiple stepping quantity, interpolates by depending on a DSP operation unit in the field programmable gate array FPGA and a ROM for storing interpolation coefficients, and stores the interpolated data into the FIFO.
As a further technical solution of the present application, when the trigger level is repositioned after interpolation, the interpolated data amount is distributed between the front and rear real-time sampling points, and the interpolated data needs to be repositioned, and the position of the point closest to the trigger level in the interpolation points is found, and the point is used as the reference position for waveform display.
As a further technical solution of the present application, specifically before triggering level relocation after interpolation, parameters to be determined include:
pre _ length, sampling array length in the Pre-trigger stage, which means the number of arrays to be acquired in the Pre-trigger stage of the oscilloscope in order to meet the requirement of storage depth;
pre _ offset, Pre-trigger sample array offset, which refers to the offset of the first sample array in the Pre-trigger stage to meet the requirement of storage depth;
post _ length, the length of the sampling array in the Post-trigger stage, which refers to the number of arrays to be collected in the Post-trigger stage of the oscilloscope in order to meet the requirement of storage depth;
post _ offset, Post-trigger sampling array offset, which refers to the offset of the last sampling array in the Post-trigger stage to meet the requirement of storage depth;
the number of corresponding interpolation points is started in the accurate positioning process, the parameter is used for guiding the FPGA to search for an accurate triggering position enabling signal, namely the accurate positioning process is started when the number of the interpolation points reaches the value;
insert _ assist _ num, the number of discarded points is assisted in the accurate positioning process, and due to the randomness of time base gears and trigger time delay setting, the situation that the number of required interpolation points is not integral sometimes occurs for generating a certain number of interpolation points. The FPGA adds the parameter and trigger _ num _ of _ activated (position offset between two real-time sampling points where interpolation points meeting trigger conditions are located) according to needs, and discards the number of points of Insert _ assist _ num + trigger _ num _ of _ activated before fluorescence is formed, so that the waveform is ensured to be stabilized at the trigger position;
insert _ tirg _ num _ end, the number of interpolation points corresponding to the end of the accurate positioning process, wherein the parameter is used for guiding the FPGA to end the level comparison process after the interpolation counter reaches the value, and the searched trigger point is ensured to be positioned between the front sampling point and the rear sampling point;
and the Trig _ level _ insert accurately positions a special comparison threshold, compares the numerical value of the interpolation point with the parameter, and finds out the point which firstly passes the parameter, namely the accurate trigger position to be searched. When rising edge occurs, the FPGA sets the Trig _ level _ insert as a high-level Trig _ high _ level triggering hysteresis; and when a falling edge triggers, setting the Trig _ level _ insert as a low-level Trig _ low _ level triggering the hysteresis.
The embodiment of the application discloses a system for accurately positioning a trigger position based on a programmable circuit, which comprises:
the acquisition state control machine acquires enough data according to the time base gear and the trigger delay of the data acquisition and analysis instrument to meet the requirement of one storage depth and the requirement of the number of required interpolation points and stores the data into a BRAM real-time storage area in the FPGA;
the interpolation control module reads the acquired data in the BRAM real-time storage area according to the interpolation gear of the data acquisition and analysis instrument by a sine interpolation method and the interpolation multiple step quantity, interpolates by depending on a DSP operation unit in the FPGA and a ROM for storing interpolation coefficients, and stores the interpolated data into FIFO;
and triggering a level relocation module after interpolation, distributing the interpolated data between front and back real-time sampling points, relocating the interpolated data, finding the position of the point closest to the trigger level in the interpolated points, and taking the point as the reference position of waveform display.
As a further technical solution of the present application, when the post-interpolation trigger level relocation module implements post-interpolation trigger level relocation, the following steps are adopted:
setting interpolation multiples and software parameters according to the interpolation gears;
the FPGA receives sampling data in real time according to interpolation multiples to perform interpolation operation, outputs interpolation points and sends the interpolation points to an interpolation point comparator, the module counts the number of the interpolation points, and when the number is between design parameters Insert _ tirg _ num _ begin and Insert _ tirg _ num _ end, an enabling signal is given and sent to the interpolation point level comparator;
and an interpolation point level comparator in the FPGA compares the interpolation point with the set Trig _ level _ insert in real time to find out a trigger interpolation point. For example, when triggering a rising edge, on the premise that the enable signal is valid, if the value of the previous interpolation point is less than the Trig _ level _ insert and the value of the current interpolation point is greater than or equal to the Trig _ level _ insert, the trigger interpolation point is considered to be found. At this time, recording the interpolation number of the interpolation point from the two sampling points, and recording as trigger _ num _ of _ inserted;
the FPGA control logic discards redundant interpolation points, monitors the number of the interpolation points in real time, starts to sort the interpolation storage data after reaching the requirement of one-screen display, and discards the redundant interpolation points so that the trigger points can correspond to the trigger positions on the screen;
the number of interpolation points needing to be discarded is Insert _ assist _ num + trigger _ num _ of _ engaged, the actual execution is carried out in a FIFO read control mode, and at the moment, accurate trigger positioning after one-time interpolation is finished;
and (4) overlapping the fluorescence frequency, namely, discarding redundant interpolation points, starting to read the rest interpolation points for overlapping the frequency, and further generating a display waveform.
A data acquisition and analysis instrument adopts a system for accurately positioning a trigger position based on a programmable circuit to realize accurate positioning of the trigger position after interpolation of an output signal.
Compared with the prior art, the beneficial effect of this disclosure is:
the invention discloses a programmable logic device-based method for realizing hardware interpolation of acquired data and completing accurate trigger positioning. The invention is realized by aiming at the technology of interpolation and triggering relocation, and fully exerts the computing capability of software and the characteristics of parallel execution and continuous operation of a production line of a programmable logic device. The interpolation and relocation framework of the invention completely completes the operation with low real-time requirement by software according to the real-time requirement, and completely completes the part which requires rapid execution by hardware. The trigger level positioning method provided by the invention has structural consistency in the aspects of parameter setting and the like, is easy for software and hardware coordination control and cross-platform transplantation, can enhance the reliability of products while improving the waveform capture rate of the oscilloscope, and shortens the development period of the products.
The method realizes interpolation and triggering accurate positioning by pure hardware, and consumes less time. The scheme is clear in labor division, and key parameters required by hardware interpolation are calculated by fully utilizing the characteristic of strong software computing capability according to the execution speed of software and hardware and combining the real-time requirement of an oscilloscope. The interpolation process adopts programmable logic hardware as a main body to execute the interpolation and trigger level accurate positioning process, thereby effectively improving the waveform capture rate of the oscilloscope.
The scheme disclosed by the invention has the advantages of rigorous structure, clear flow and easiness in cross-platform transplantation. The set of interpolation and trigger level accurate positioning process designed by the invention comprises efficient structure composition and clear execution flow, and is indeed feasible through experimental verification.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application.
FIG. 1 is a schematic illustration of an interpolation structure in an embodiment of the disclosure;
FIG. 2 is a single channel triggered positioning parameter design of an embodiment of the present disclosure;
FIG. 3 is a four-channel combined triggered positioning parameter design according to an embodiment of the present disclosure;
FIG. 4 is a triggered relocation scheme of an embodiment of the present disclosure;
FIG. 5 is a flow chart of interpolation and positioning according to an embodiment of the present disclosure;
FIG. 6 is a schematic illustration of sine interpolation according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of triggered relocation upon rising edge triggering according to an embodiment of the disclosure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
According to the scheme, the characteristics of strong software computing capability and high hardware execution speed are combined with parameter design and structural design, and the interpolation positioning speed and the oscilloscope waveform capture rate are effectively improved aiming at accurate triggering positioning expansion in the interpolation gear. The schematic block diagram of the invention is shown in fig. 1, and the interpolation and relocation process mainly comprises two parts of software calculation parameters and hardware execution.
In the technical scheme of the application, parameter design is required in the aspect of software, for convenience of explanation of the technical scheme of the application, fig. 2 shows association between an acquisition array and design parameters under a single channel, and fig. 3 shows association between the acquisition array and the design parameters when four channels are combined for data acquisition.
The design parameters mainly relate to the lengths and array offsets corresponding to the Pre-trigger stage and the Post-trigger stage, and include parameters Pre _ length, Pre _ offset, Post _ length, and Post _ offset. The parameters are mainly used for guiding the FPGA programmable circuit to collect data with complete storage depth, such as collecting 600 points at a time. The Pre _ length and Post _ length can be used for coarse adjustment of the Pre-trigger length and the Post-trigger length, the number of points of an array length is correspondingly increased every time the parameter is increased by 1, the number of points is 4 points in a single channel, and the number of points is 16 points in a four-channel combination. The Pre _ offset and the Post _ offset can finely adjust the collection points, and can meet the collection requirement of the collection points with any length. The flexible setting of the collection points is an interpolation and a precondition guarantee is made for the relocation after the interpolation.
Secondly, channel data are often combined in the oscilloscope to improve the sampling rate, an acquisition array in the four-channel combination is shown in fig. 3, and each sampling clock comprises 16 data points. The parameter setting under the condition is compatible with the design parameters in the step I, and the programmable circuit realizes the control of the collection point number according to the combined mark. It should be noted that this compatibility also allows for consistency in the design of subsequent structures.
And thirdly, designing the relocation parameters of the trigger level after interpolation, and explaining the relocation module of the trigger level after interpolation in detail.
In a typical implementation example of the present application, a system for accurately positioning a trigger position based on a programmable circuit is configured as shown in fig. 1, where an interpolation and relocation module in the scheme includes an acquisition state controller, a BRAM real-time data storage area, an interpolation control module, an interpolation data storage, and a post-interpolation trigger level relocation module.
The acquisition state control machine: and acquiring enough data according to the time base gear and the trigger delay of the oscilloscope so as to meet the requirement of one storage depth and the requirement of the number of required interpolation points.
An interpolation control module: reading the acquired data in the BRAM real-time storage area according to the interpolation gear of the oscilloscope by a 'sin (x)/x' method according to the interpolation multiple stepping quantity, interpolating by relying on a DSP (digital signal processor) operation unit (executing addition and multiplication operation) and a ROM (storing interpolation coefficients) in the FPGA, and storing the interpolated data into an interpolation data memory FIFO.
Triggering a level relocation module after interpolation: the data volume after interpolation is distributed between front and back real-time sampling points. At this time, the interpolated data needs to be repositioned, the position of the point closest to the trigger level in the interpolated points is found, and the point is used as the reference position for waveform display, so that the shaking of the waveform displayed on the screen can be avoided, and the purpose of accurate positioning is achieved.
The following example describes the triggered relocation scheme of the present invention: as shown in fig. 7, it is assumed that the storage depth is 600, the pre-trigger length is 300 points, the post-trigger length is 300 points, the channel is in the non-combination mode, the interpolation step is 40 times, the rising edge triggers, and the trigger level is 520. In this example, the FPGA needs to combine the sampled data into an array with 4 points as a group, and to realize accurate triggering after interpolation, the FPGA needs to first performThe following parameters are determined by the software according to a predetermined formula. In the formula, "Numpre"represents the number of pre-trigger points, which is 300 points in this example; "Numpost"represents the number of post-trigger points, which is 300 points in this example; "β" represents the interpolation factor, which in this case is a 40-fold interpolation; "Width" represents the array Width, which is 4 for this example for the channel uncombined mode;
which means that the rounding is made up,
represents rounding down; "%" indicates the remainder operation, and "16" means that 16 points are prepared in advance to complete the interpolation operation.
Insert_assist_num＝Insert_tirg_num_begin-Numpre (6)
Insert_tirg_num_end＝Insert_tirg_num_begin+β (7)
Pre _ length is the length of the sampling array in the Pre-trigger stage, which means the number of the arrays to be acquired in the Pre-trigger stage of the oscilloscope in order to meet the requirement of storage depth. Combining the example scenario and calculation equation (1), the calculation value is 7.
Pre _ offset is the Pre-trigger sample array offset, which refers to the offset of the first sample array in the Pre-trigger phase to meet the memory depth requirement. Combining the example scenario and calculation equation (2), the calculation value is 1.
The Post _ length is the length of the sampling array in the Post-trigger stage, and refers to the number of arrays required to be collected in the Post-trigger stage of the oscilloscope in order to meet the requirement of storage depth. Combining the example scenario and calculation equation (3), the calculation value is 7.
The Post _ offset is the offset of the Post-trigger sampling array, which is the offset of the last sampling array in the Post-trigger stage to meet the requirement of the storage depth. Combining the example scenario and calculation equation (4), the calculation value is 1.
Insert _ tirg _ num _ begin is the number of interpolation points corresponding to the accurate positioning process, and the parameter is used for guiding the FPGA to search for an accurate trigger position enabling signal, namely, the accurate positioning process is started after the interpolation point count reaches the value. In connection with the example scenario and calculation equation (5), the calculation value is 320.
Insert _ assist _ num is the number of auxiliary discarding points in the accurate positioning process, and the required number of interpolation points is non-integral sometimes caused by the randomness of time base gears and trigger time delay setting to generate a certain number of interpolation points. Aiming at the situation, the scheme is that the number of points of multi-interpolation caused by the influence of the non-integer is calculated by software, and parameters are set for the FPGA to trigger the relocation module. The FPGA will add the parameter and trigger _ num _ of _ activated (the position offset between two real-time sampling points where the interpolation point satisfying the trigger condition is located) together according to the requirement, and discard the number of points of Insert _ assist _ num + trigger _ num _ of _ activated before forming the fluorescence, thereby ensuring the waveform to be stable at the trigger position. Combining the example scenario and calculation equation (6), the calculation value is 20.
Insert _ tirg _ num _ end is the number of interpolation points corresponding to the end of the accurate positioning process, and the parameter is used for guiding the FPGA to end the level comparison process after the interpolation counter reaches the value, so that the searched trigger point is ensured to be positioned between the front sampling point and the rear sampling point. Combining the example scenario and calculation equation (7), the calculation value is 360.
The Trig _ level _ insert is a special comparison threshold value for accurate positioning, the numerical value of an interpolation point is compared with the parameter, and the point which passes the parameter for the first time is found to be the accurate trigger position to be searched. An example is rising edge triggering, according to the calculation formula (8), the Trig _ level _ insert is set to be the high level Trig _ high _ level of the trigger hysteresis, i.e. 520.
The correct setting of the above parameters is a precondition and guarantee for successful triggering of relocation. In conjunction with the above parameter definitions, figure 4 presents a scheme for triggering relocation.
The software sets parameters such as interpolation multiple, Pre _ length, Pre _ offset, Post _ length, Post _ offset, Insert _ tirg _ num _ begin, Insert _ assist _ num, Insert _ tirg _ num _ end and Trig _ level _ Insert according to interpolation gear.
And an interpolation module in the FPGA receives the sampling data in real time according to the interpolation multiple to perform interpolation operation, outputs an interpolation point and sends the interpolation point to an interpolation point comparator. The module counts the number of interpolation points, giving an enable signal to the interpolation point level comparator when the number is between the design parameters Insert _ tirg _ num _ begin and Insert _ tirg _ num _ end.
And an interpolation point level comparator in the FPGA compares the interpolation point with the set Trig _ level _ insert in real time. Taking the rising edge as an example, on the premise that the enable signal is valid, the value of the current interpolation point is smaller than the Trig _ level _ insert, and when the value of the current interpolation point is greater than or equal to the Trig _ level _ insert, the trigger interpolation point is considered to be found. At this time, the interpolation number between the interpolation point and the two sampling points is recorded as trigger _ num _ of _ inserted.
The FPGA control logic discards redundant interpolation points, the interpolation module monitors the number of the interpolation points in real time, and after the requirement of one-screen display is met, the sorting of interpolation storage data is started, wherein the redundant interpolation points are mainly discarded, so that the trigger points can correspond to the trigger positions on the screen. The number of interpolation points to be discarded is Insert _ assist _ num + trigger _ num _ of _ engaged, and the actual execution is performed by using a FIFO read control mode. At the moment, accurate trigger positioning after one-time interpolation is finished, and the method can be used for realizing trigger level relocation of any interpolation multiple.
And (4) performing fluorescence frequency superposition, namely discarding redundant interpolation points, starting to read the rest interpolation points into a frequency superposition module, and further generating a display waveform.
The application also discloses a method for accurately positioning the trigger position based on the programmable circuit, and a scheme flow is shown in fig. 5.
And detecting whether the time base or the time delay is changed by the user in real time through software, calculating corresponding parameters according to the rule immediately after the change is found, transmitting the parameters to the FPGA through bus communication, and restarting an acquisition interpolation process. Assuming that data flows from the right side to the left side, the hardware cache acquisition module combines the real-time sampling data into an array according to the channel combination condition and the acquisition array design scheme. When the oscilloscope is in an interpolation gear, the hardware interpolation module performs real-time interpolation, then the hardware interpolation module enters the trigger point relocation searching module, and the memory of the interpolation point is adjusted, so that the generated waveform can be stably displayed by taking the trigger level as a reference point.
The key points of the method are a parameter design strategy in software design, a trigger repositioning structure designed on the basis of design parameters and a corresponding algorithm control and execution flow. The parameter design mainly refers to the definition of an acquisition array and the parameter definition of a triggering relocation module. In addition, the parameter design of the scheme has consistency in multi-channel combination, the trigger relocation module can be compatible with the non-integral condition of the number of the required sampling points, and the flexibility is strong.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. The method for accurately positioning the trigger position based on the programmable circuit is characterized by comprising the following steps:
detecting a time base gear and trigger delay of a data acquisition and analysis instrument;
judging whether a user changes a time base gear or triggers time delay, if so, setting software parameters, sending the software parameters to a Field Programmable Gate Array (FPGA) through bus communication, and restarting an acquisition interpolation process;
the processor obtains sampling data and combines the real-time sampling data into an array according to the channel combination condition;
when the data acquisition and analysis instrument is in an interpolation gear, performing real-time interpolation, then performing trigger point relocation, and adjusting the interpolation point, so that the generated waveform can be stably displayed by taking a trigger level as a reference point;
calculating key parameters required by hardware interpolation by using software, and realizing interpolation and triggering accurate positioning by using pure hardware;
the FPGA reads the acquired data in the BRAM real-time storage area according to the interpolation gear of the data acquisition and analysis instrument by a sine interpolation method and the interpolation multiple step quantity, interpolates by relying on a DSP operation unit in the FPGA and a ROM for storing interpolation coefficients, and stores the interpolated data into the FIFO.
2. The method for accurately positioning the trigger position based on the programmable circuit as claimed in claim 1, wherein the field programmable gate array FPGA acquires a sufficient amount of data to meet the requirement of one storage depth and the required number of interpolation points when acquiring the data.
3. The method as claimed in claim 1, wherein when the trigger level is repositioned after interpolation, the interpolated data amount is distributed between the front and rear real-time sampling points, and the interpolated data needs to be repositioned to find the position of the point closest to the trigger level among the interpolated points, and the point is used as the reference position for waveform display.
4. A method for accurately locating trigger positions based on programmable circuits as defined in claim 3 wherein the parameters to be determined, particularly prior to post-interpolation trigger level relocation, include:
pre _ length, which is the length of the sampling array in the Pre-trigger stage and refers to the number of arrays to be acquired in the Pre-trigger stage of the oscilloscope so as to meet the requirement of storage depth;
pre _ offset, which is the offset of the Pre-trigger sampling array, and refers to the offset of the first sampling array in the Pre-trigger stage, which meets the requirement of storage depth;
the Post _ length is the length of a sampling array in the Post-trigger stage, and refers to the number of arrays required to be collected in the Post-trigger stage of the oscilloscope to meet the requirement of storage depth;
the Post _ offset is offset of a Post-trigger sampling array, namely offset of the last sampling array in the Post-trigger stage, which meets the requirement of storage depth;
insert _ tirg _ num _ begin, starting the number of corresponding interpolation points for the accurate positioning process, wherein the parameters are used for guiding the FPGA to search for accurate triggering position enabling signals, namely, the accurate positioning process is started after the counting of the interpolation points reaches the value;
insert _ assist _ num, which is the number of auxiliary discarded points in the accurate positioning process, calculates the number of points with multiple interpolation caused by the influence of the non-integer, and sets parameters for the FPGA to trigger the relocation module; the FPGA adds the parameter and trigger _ num _ of _ triggered position offset between two real-time sampling points where interpolation points meeting trigger conditions are located according to the requirement, and discards the number of points of Insert _ assist _ num + triggered _ num _ of _ triggered before fluorescence is formed, so that the waveform is ensured to be stable at the trigger position;
insert _ tirg _ num _ end, which is the number of interpolation points corresponding to the end of the accurate positioning process, the parameter is used for guiding the FPGA to end the level comparison process after the interpolation counter reaches the value, and the searched trigger point is ensured to be positioned between the front sampling point and the rear sampling point;
the method comprises the steps of Trig _ level _ insert, accurately positioning a special comparison threshold, comparing the numerical value of an interpolation point with a parameter, finding out a point which crosses the parameter for the first time, namely, an accurate trigger position to be searched, setting the Trig _ level _ insert to trigger a high-level Trig _ high _ level of hysteresis by the FPGA when a rising edge exists, and setting the Trig _ level _ insert to trigger a low-level Trig _ low _ level of the hysteresis when a falling edge exists.
5. The method for accurately locating a trigger position based on a programmable circuit as claimed in claim 4, wherein the step of triggering relocation is as follows:
setting interpolation multiples and software parameters according to the interpolation gears;
the FPGA receives sampling data in real time according to interpolation multiples to perform interpolation operation, outputs interpolation points and sends the interpolation points to an interpolation point comparator, the module counts the number of the interpolation points, and when the number is between design parameters Insert _ tirg _ num _ begin and Insert _ tirg _ num _ end, an enabling signal is given and sent to the interpolation point level comparator;
an interpolation point level comparator in the FPGA compares an interpolation point with a set Trig _ level _ insert in real time, finds a trigger interpolation point, records the interpolation number of the interpolation point from two sampling points at the moment, and records the interpolation number as Trigged _ num _ of _ insert;
the FPGA control logic discards redundant interpolation points, monitors the number of the interpolation points in real time, starts to sort the interpolation storage data after reaching the requirement of one-screen display, and discards the redundant interpolation points so that the trigger points can correspond to the trigger positions on the screen; the number of interpolation points needing to be discarded is Insert _ assist _ num + trigger _ num _ of _ engaged, the actual execution is carried out in a FIFO read control mode, and at the moment, accurate trigger positioning after one-time interpolation is finished;
and (4) overlapping the fluorescence frequency, namely, discarding redundant interpolation points, starting to read the rest interpolation points for overlapping the frequency, and further generating a display waveform.
6. The method as claimed in claim 5, wherein on a rising edge, if the value of a previous interpolation point is less than the Trig _ level _ insert and the value of the current interpolation point is greater than or equal to the Trig _ level _ insert, the trigger interpolation point is considered to be found on the premise that the enable signal is asserted.
7. A system for accurately positioning a trigger position based on a programmable circuit, comprising:
the acquisition state control machine acquires enough data according to the time base gear and the trigger delay of the data acquisition and analysis instrument to meet the requirement of one storage depth and the requirement of the number of required interpolation points and stores the data into a BRAM real-time storage area in the FPGA;
the interpolation control module reads the acquired data in the BRAM real-time storage area according to the interpolation gear of the data acquisition and analysis instrument by a sine interpolation method and the interpolation multiple step quantity, interpolates by depending on a DSP operation unit in the FPGA and a ROM for storing interpolation coefficients, and stores the interpolated data into FIFO;
triggering a level relocation module after interpolation, distributing the data volume after interpolation between front and back real-time sampling points, relocating the interpolated data, finding the position of a point closest to the triggering level in the interpolation points, and taking the point as a reference position for waveform display;
and calculating key parameters required by hardware interpolation by using software, and realizing interpolation and triggering accurate positioning by using pure hardware.
8. The programmable circuit based accurate positioning trigger position system of claim 7 wherein said post-interpolation trigger level relocation module, in effecting post-interpolation trigger level relocation, employs the steps of:
setting interpolation multiples and software parameters according to the interpolation gears;
the FPGA receives sampling data in real time according to interpolation multiples to perform interpolation operation, outputs interpolation points and sends the interpolation points to an interpolation point comparator, the module counts the number of the interpolation points, and when the number is between design parameters Insert _ tirg _ num _ begin and Insert _ tirg _ num _ end, an enabling signal is given and sent to the interpolation point level comparator;
the number of corresponding interpolation points is started for the accurate positioning process, the parameter is used for guiding the FPGA to search an accurate trigger position enabling signal, namely the accurate positioning process is started after the count of the interpolation points reaches the value; insert _ tirg _ num _ end, which is the number of interpolation points corresponding to the end of the accurate positioning process, the parameter is used for guiding the FPGA to end the level comparison process after the interpolation counter reaches the value, and the searched trigger point is ensured to be positioned between the front sampling point and the rear sampling point;
an interpolation point level comparator in the FPGA compares an interpolation point with a set Trig _ level _ insert in real time, finds a trigger interpolation point, records the interpolation number of the interpolation point from two sampling points at the moment, and records the interpolation number as Trigged _ num _ of _ insert;
the Trig _ level _ insert is a special comparison threshold for accurate positioning, compares the numerical value of an interpolation point with the parameter, and finds out a point which firstly passes the parameter, namely an accurate trigger position to be searched;
the FPGA control logic discards redundant interpolation points, monitors the number of the interpolation points in real time, starts to sort the interpolation storage data after reaching the requirement of one-screen display, and discards the redundant interpolation points so that the trigger points can correspond to the trigger positions on the screen; the number of interpolation points needing to be discarded is Insert _ assist _ num + trigger _ num _ of _ engaged, the actual execution is carried out in a FIFO read control mode, and at the moment, accurate trigger positioning after one-time interpolation is finished;
the number of points discarded in an auxiliary mode in the accurate positioning process is calculated, the number of points with multiple interpolation caused by the influence of the non-integer is calculated, and parameters are set for an FPGA (field programmable gate array) to trigger a relocation module; the FPGA adds the parameter and trigger _ num _ of _ triggered position offset between two real-time sampling points where interpolation points meeting trigger conditions are located according to the requirement, and discards the number of points of Insert _ assist _ num + triggered _ num _ of _ triggered before fluorescence is formed, so that the waveform is ensured to be stable at the trigger position;
and (4) overlapping the fluorescence frequency, namely, discarding redundant interpolation points, starting to read the rest interpolation points for overlapping the frequency, and further generating a display waveform.
9. A data acquisition and analysis instrument, which adopts the system for accurately positioning the trigger position based on the programmable circuit according to any one of claims 7 to 8 to realize accurate positioning of the trigger position after the interpolation of the output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811621541.0A CN109765412B (en) | 2018-12-28 | 2018-12-28 | Method for accurately positioning trigger position based on programmable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811621541.0A CN109765412B (en) | 2018-12-28 | 2018-12-28 | Method for accurately positioning trigger position based on programmable circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109765412A CN109765412A (en) | 2019-05-17 |
| CN109765412B true CN109765412B (en) | 2021-06-01 |
Family
ID=66450442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811621541.0A Active CN109765412B (en) | 2018-12-28 | 2018-12-28 | Method for accurately positioning trigger position based on programmable circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109765412B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112051442B (en) * | 2020-08-05 | 2023-08-25 | 中电科思仪科技股份有限公司 | Method for improving time parameter measurement speed in microwave peak power measurement |
| CN114509589A (en) * | 2020-11-17 | 2022-05-17 | 北京普源精电科技有限公司 | Oscilloscope trigger system, oscilloscope trigger method, oscilloscope and storage medium |
| CN113125826B (en) * | 2021-04-19 | 2022-02-01 | 电子科技大学 | Transient power operation and triggering method of oscillography power analyzer |
| CN113447692B (en) * | 2021-08-31 | 2021-11-26 | 深圳市鼎阳科技股份有限公司 | Oscilloscope with data recording function and waveform display method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103018512A (en) * | 2011-09-23 | 2013-04-03 | 北京普源精电科技有限公司 | Oscilloscope with external triggering function |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753677B1 (en) * | 2003-02-28 | 2004-06-22 | Agilent Technologies, Inc. | Trigger jitter reduction for an internally triggered real time digital oscilloscope |
| DE102005035473A1 (en) * | 2005-07-28 | 2007-02-01 | Rohde & Schwarz Gmbh & Co. Kg | Method and system for digital triggering for oscilloscopes |
| CN102788892B (en) * | 2011-05-18 | 2016-09-07 | 北京普源精电科技有限公司 | A kind of digital oscilloscope for accurately triggering |
| CN104407190B (en) * | 2014-11-26 | 2017-02-01 | 电子科技大学 | Fully-digital random sampling method |
| CN104535815B (en) * | 2014-12-16 | 2017-08-25 | 北京航天测控技术有限公司 | A kind of digital two-stage combination trigger signal extracting method |
| CN106226573B (en) * | 2016-08-16 | 2019-02-26 | 中国电子科技集团公司第四十一研究所 | A kind of digital signal processing method for digital fluorescence oscilloscope |
-
2018
- 2018-12-28 CN CN201811621541.0A patent/CN109765412B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103018512A (en) * | 2011-09-23 | 2013-04-03 | 北京普源精电科技有限公司 | Oscilloscope with external triggering function |
Non-Patent Citations (1)
| Title |
|---|
| 一种多窗口示波器采集系统的设计与实现;王励等;《电子测量技术》;20180731;第41卷(第14期);134-137 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109765412A (en) | 2019-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109765412B (en) | Method for accurately positioning trigger position based on programmable circuit | |
| CN100529766C (en) | Equivalent sampling device | |
| JP4723030B2 (en) | Improved digital trigger circuit | |
| CN103368676B (en) | A kind of strange land based on cyclic pulse signal synchronous data sampling method and system | |
| CN104254761B (en) | Sensor time synchronization | |
| CN101706521B (en) | Digital storage oscilloscope with function of time base fine tuning | |
| CN106154299A (en) | A kind of GPS/SINS integrated navigation system method for synchronizing time | |
| CN102565673B (en) | Highly-reliable pulse counting test system based on FPGA (Field Programmable Gate Array) | |
| CN106772185B (en) | Signal interval or period detection method and device for oscilloscope | |
| CN110836992B (en) | Oscillography power meter acquisition system based on FPGA | |
| CN104375006B (en) | A kind of Fast synchronization phase amount correction method | |
| CN105044420A (en) | Waveform searching method of digital oscilloscope | |
| CN104297543A (en) | Hybrid oscilloscope with channel synchronization function | |
| CN106645780A (en) | Rotating speed detection method and system base on DSP | |
| CN101556325A (en) | Method for quickly verifying electric energy error | |
| CN104076178B (en) | A kind of oscillograph with improvement Trigger Function | |
| Hu | Design and verification of FIR filter based on Matlab and DSP | |
| CN107678333B (en) | Step length time correction method and device based on equivalent time sequence sampling | |
| CN108776264A (en) | The fft analysis device of digital oscilloscope | |
| CN109948223A (en) | A kind of impulse amplitude acquisition methods based on Lagrange's interpolation | |
| JP2003242130A (en) | Synchronization method of collected data and data processing system | |
| CN110061735B (en) | Decimal frequency dividing circuit and interface clock frequency dividing circuit using same | |
| CN110799807B (en) | Orthogonal encoder signal filtering method, device and system | |
| Kuojun et al. | A novel decimation method in parallel based acquisition system | |
| CN113126530B (en) | Method for calculating sampling rate of timer filter and control device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Applicant after: CLP kesiyi Technology Co.,Ltd. Address before: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Applicant before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |