CN113125826A - Transient power operation and triggering method of oscillography power analyzer - Google Patents

Transient power operation and triggering method of oscillography power analyzer Download PDF

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CN113125826A
CN113125826A CN202110417774.4A CN202110417774A CN113125826A CN 113125826 A CN113125826 A CN 113125826A CN 202110417774 A CN202110417774 A CN 202110417774A CN 113125826 A CN113125826 A CN 113125826A
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power
trigger
data
module
fifo
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CN113125826B (en
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耿航
许波
陈凯
陈子灵
白利兵
钟乔
赵佳
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/06—Arrangements for measuring electric power or power factor by measuring current and voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/133—Arrangements for measuring electric power or power factor by using digital technique
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage

Abstract

The invention discloses a transient power operation and triggering method of an oscillography power analyzer, a user sets a triggering mode to be power triggering through an upper computer, a triggering module firstly adopts a default power triggering threshold value to generate a power triggering signal under the condition, the upper computer displays a cursor in a display screen while displaying wave k (p) shape data, the initial position of the cursor corresponds to a quantized value of the default power triggering threshold value, the user can select whether an auxiliary reference source is needed to generate the power triggering signal together by adjusting the power triggering threshold value set by the cursor, and the phase difference between the triggering point and the displayed waveform is adjusted by adjusting a programming full signal to enable the triggering point and the displayed waveform to be synchronous. The invention can complete the realization of the power triggering, the visual setting of the triggering threshold value and the triggering delay correction, solve the problem of the positive and negative overturning and jumping of the voltage and the current when the voltage and the current signals are sine signals without harmonic waves and realize the triggering delay correction.

Description

Transient power operation and triggering method of oscillography power analyzer
Technical Field
The invention belongs to the technical field of oscillography power analyzers, and particularly relates to a transient power operation and triggering method of an oscillography power analyzer.
Background
Because the power of the signal to be detected can be analyzed in the oscillography power analyzer, conditions are provided for realizing power triggering. The existing oscillography power analyzer generally comprises an acquisition board card, a main FPGA board card and an upper computer, wherein the acquisition board card transmits data to the main FPGA board card after acquiring the data, the main FPGA board card divides the data into two paths, one path of data is stored in an FIFO (first in first out) used for oscillography mode display, and the other path of data is transmitted to a trigger module to generate a trigger signal. The trigger module can divide modules according to a trigger mode, the trigger module is determined when a power value is adopted for triggering, the trigger module firstly selects a trigger source, if the selected power value of a certain channel is used as the trigger source, the acquired data of the channel is sent to the trigger module, the voltage and the current of the channel generate a power calculation value through a multiplier, then the value is compared with a power comparison threshold through a comparator to generate a comparison square wave signal, finally, the square wave signal generates a power trigger signal, the power trigger signal is used for controlling the data writing of the FIFO, and the data stored in the FIFO is ensured to be the signal which a user wants to capture.
When the oscillometric power analyzer is applied in an electric power system, the signal to be measured is generally a periodic signal, but may be rich in a certain number of harmonics. Setting the voltage expression of the signal to be measured as
Figure BDA0003026605030000011
The current to be measured is represented by
Figure BDA0003026605030000012
Wherein N, M denotes the order of the harmonic voltage and the harmonic current, respectively, An、BmThe amplitudes of the harmonic voltage and the harmonic current are respectively shown, N is 0,1, …, N, M is 0,1, …, M. When the signal to be measured is a harmonic signal, the synthesized power signal is the sum of the product of any two harmonic waves. Any two-term harmonic product can be replaced by the sum of a frequency multiplication signal and a difference frequency signal according to a trigonometric function formula, and the power signal p can be represented by the following formula:
Figure BDA0003026605030000021
here, the case of a single harmonic signal including a second harmonic, a third harmonic, an odd harmonic (5 th order at the highest), and an even harmonic (4 th order at the highest) is further enumerated by way of enumeration:
Figure BDA0003026605030000022
Figure BDA0003026605030000023
Figure BDA0003026605030000024
Figure BDA0003026605030000025
Figure BDA0003026605030000026
as can be seen from the above formula, for a voltage and current signal with an arbitrary waveform, the corresponding power signal expression is extremely complex, and it is difficult to perform accurate power trigger threshold setting.
In addition, the formula
Figure BDA0003026605030000031
It can be known that the lower the harmonic frequency of the voltage and current is, the simpler the waveform is, and when the signal to be measured is a single harmonic signal, the voltage signal is reduced to u-a1sinwt, the current signal is reduced to i ═ B1sinwt, the power value is then:
Figure BDA0003026605030000032
from the above equation, it can be seen that when the voltage and current are single harmonic signals, the frequency of the power signal becomes a superposition of a dc bias and a sine wave of twice the frequency of the voltage and current. FIG. 1 is a voltage, current and power waveform contrast image of a single harmonic signal. As shown in fig. 1, in this case, the voltage, current, power, and power are displayed together on the display screen with both the voltage and current at the two trigger points of power being on the rising edge at a time and on the falling edge at a time. Therefore, the voltage and current waveforms captured in the power triggering manner may be captured at the rising edge and also may be captured at the falling edge, and positive and negative flip jumps may occur between several waveforms, which is not favorable for observing the power values corresponding to the voltage and current waveforms, and this is also a problem to be solved.
In addition, in an actual circuit, due to the fact that path delay exists in internal wiring of the FPGA and the long time required by floating-point number multiplication operation is long, a certain time deviation exists between the time of generating the trigger signal and the real trigger time, and as a result of the deviation, the position of the trigger point displayed on the display interface is delayed, and the delay can be different according to different system architectures and even different individuals.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a transient power operation and triggering method of an oscillography power analyzer, realizes the visual adjustment functions of power triggering and triggering threshold in the oscillography power analyzer, can enable a user to freely set the threshold of the power triggering threshold, solves the problem of positive and negative overturning and jumping of voltage and current when the voltage and current signals are sine signals without harmonic waves, and realizes triggering delay correction.
In order to achieve the above object, the transient power operation and triggering method of the oscillometric power analyzer of the present invention comprises the following steps:
s1: a splicing module, a POWER operation module, an oscillography mode storage module ACQ _ FIFO, a POWER value storage module POWER _ FIFO and a trigger module are configured in a main FPGA board card of the oscillography POWER analyzer, wherein the splicing module is used for receiving voltage data and current data and sending the voltage data and the current data into the oscillography mode storage module ACQ _ FIFO for storage after splicing; the POWER operation module is used for receiving the voltage data and the current data, and respectively sending the POWER data obtained by operation to the trigger module and the POWER value storage module POWER _ FIFO; the trigger module is used for receiving the voltage data, the current data and the power data, selecting corresponding data according to a trigger source and an edge trigger type set by a user to generate a trigger signal, and sending the trigger signal to the oscillography mode storage module ACQ _ FIFO for carrying out trigger control on the storage of the voltage data and the current data; the oscillography mode storage module ACQ _ FIFO is used for storing voltage data and current data for an upper computer to read and display; the POWER value storage module POWER _ FIFO is used for storing POWER data for an upper computer to read and display;
s2: setting a voltage amplitude level and a current amplitude level by a user through an upper computer, wherein the amplitude level determines the voltage and current measuring range of the display screen, the measuring range of the voltage amplitude level is recorded as [ -U, U ], and the measuring range of the current amplitude level is recorded as [ -I, I ];
s3: the acquisition board card acquires a signal to be detected, and transmits acquired voltage data and current data to the main FPGA board card, the main FPGA board card divides the received voltage data and current data into three paths, one path is spliced by the splicing module and then stored in the oscillography mode storage module ACQ _ FIFO, the other path is transmitted to the trigger module, the other path is transmitted to the POWER operation module to be operated to obtain corresponding POWER data, and then the corresponding POWER data is transmitted to the trigger module and the POWER value storage module POWER _ FIFO;
s4: a user sets a trigger source and an edge trigger type of power triggering through an upper computer, and if the power value of a certain channel is selected as the trigger source, a trigger module adopts a power triggering mode; at the moment, the upper computer triggers the trigger source, the edge trigger type and the preset default power trigger threshold value
Figure BDA0003026605030000041
And sending the power trigger signal to a trigger module in the main FPGA board card, wherein the trigger module generates the power trigger signal by adopting the following method:
the trigger module triggers the power data received from the power operation module and the default power threshold value
Figure BDA0003026605030000042
Comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or two edges of the power comparison square wave level as power trigger signals according to the edge trigger type;
the main FPGA board card controls an oscillography module storage module ACQ _ FIFO to collect and store data according to a power trigger signal, an upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, corresponding power data are calculated and displayed in a quantification mode, and the specific method for quantifying the power data is as follows:
recording the resolution of an ADC module in the acquisition board card as 2K, and calculating a quantization result K (p) of any power value p calculated according to the voltage data and the current data according to the following calculation formula:
Figure BDA0003026605030000043
where Δ p represents a unit increment of power,
Figure BDA0003026605030000051
s5: the upper computer obtains the default power trigger threshold value by adopting the quantization method in the step S3
Figure BDA0003026605030000052
Quantized value of
Figure BDA0003026605030000053
Displaying a cursor on the display screen, wherein the initial position of the cursor corresponds to the quantized value
Figure BDA0003026605030000054
The user adjusts the power trigger threshold value through the upper computer, and the adjusted power trigger threshold value is recorded as
Figure BDA0003026605030000055
The current power trigger threshold value obtained by the quantization method in the step S3 is
Figure BDA0003026605030000056
Corresponding quantized value
Figure BDA0003026605030000057
The upper computer adjusts the vernier position to the quantized value
Figure BDA0003026605030000058
A corresponding position;
s6: a user selects whether an auxiliary reference source is needed to generate a power trigger signal together according to actual needs, if not, the auxiliary reference source work enabling signal is set to be invalid, if so, the auxiliary reference source work enabling signal is set to be valid, meanwhile, an auxiliary reference source selection signal is set and is used for selecting voltage data or current data to be adopted as an auxiliary reference source and setting a voltage threshold value or a current threshold value;
s7: when the trigger module receives an invalid auxiliary reference source work enabling signal, the following method is adopted to generate a power trigger signal:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure BDA0003026605030000059
Comparing to generate power comparison square waveSelecting a rising edge, a falling edge or a double edge of the power comparison square wave level as a power trigger signal according to the edge trigger type;
when the trigger module receives the effective auxiliary reference source work enabling signal, the power trigger signal is generated by adopting the following method:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure BDA00030266050300000510
Comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or two edges of the power comparison square wave level as an initial trigger signal according to the edge trigger type;
selecting voltage data or current data according to the auxiliary reference source selection signal, and comparing the voltage data or the current data with a voltage threshold value or a current threshold value to generate an auxiliary comparison square wave level;
performing phase comparison on the initial trigger signal and the auxiliary comparison square wave level to obtain a power trigger signal;
s8: recording the programming full depth set in the upper computer as prog _ full _ thresh, recording the delay caused by the calculation of POWER data by the POWER operation module as n clock cycles, and then respectively sending prog _ full _ thresh-n serving as the programming full depth to the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO by the upper computer, and when the data stored in the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO reach the programming full depth, pulling up the corresponding programming full signal to wait for the arrival of a POWER trigger signal;
s9: the main FPGA board card controls the oscillography module storage module ACQ _ FIFO to collect and store data according to the POWER trigger signal generated in the step S7, the upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, meanwhile, the upper computer reads corresponding POWER data from the POWER value storage module POWER _ FIFO, and then the read data are displayed quantitatively on the display screen.
The invention relates to a transient power operation and trigger method of an oscillography power analyzer, which comprises the steps that firstly, a user sets a trigger mode to be power trigger through an upper computer, under the condition, a trigger module firstly adopts a default power trigger threshold value to generate a power trigger signal, the upper computer displays a cursor in a display screen while displaying waveform data, the initial position of the cursor corresponds to a quantized value of the default power trigger threshold value, the user can select whether an auxiliary reference source is needed to generate the power trigger signal together or not by adjusting the power trigger threshold value set by the cursor, and the phase difference between the trigger point and a displayed waveform is adjusted by adjusting a programming full signal so that the trigger point and the displayed waveform are synchronous.
The invention can complete the realization of the power triggering and the visual setting of the triggering threshold value and solve the problem of the positive and negative overturning and jumping of the voltage and the current when the voltage and the current signals are sine signals without harmonic waves. And before the oscillography power analyzer is suitable, the trigger delay between the voltage current power signal and the trigger signal caused by circuit wiring and floating point operation can be manually corrected by adjusting the programming full depth, and because the delay is related to system architectures of different instruments and even different individuals, the trigger delay can be manually corrected, so that the oscillography power analyzer has good adaptability to different devices.
Drawings
FIG. 1 is a voltage, current and power waveform contrast image of a single harmonic signal;
FIG. 2 is a flow chart of an embodiment of a transient power calculation and triggering method of the oscillometric power analyzer of the present invention;
fig. 3 is a structural diagram of a main FPGA board card in the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
FIG. 2 is a flow chart of an embodiment of a transient power calculation and triggering method of the oscillometric power analyzer of the present invention. As shown in fig. 2, the transient power operation and triggering method of the oscillometric power analyzer of the present invention comprises the following steps:
s201: power trigger related module setting:
in the invention, in order to realize the power triggering function of the oscillography power analyzer, the main FPGA board card needs to be correspondingly improved. Fig. 3 is a structural diagram of a main FPGA board card in the present invention. As shown in fig. 3, in the present invention, a splicing module, a POWER operation module, an oscillography mode storage module ACQ _ FIFO, a POWER value storage module POWER _ FIFO, and a trigger module are configured in a main FPGA board card of an oscillography POWER analyzer, wherein the splicing module is configured to receive voltage data and current data, and send the voltage data and the current data to the oscillography mode storage module ACQ _ FIFO for storage after splicing; the POWER operation module is used for receiving the voltage data and the current data, and respectively sending the POWER data obtained by operation to the trigger module and the POWER value storage module POWER _ FIFO; the trigger module is used for receiving the voltage data, the current data and the power data, selecting corresponding data according to a trigger source and an edge trigger type set by a user to generate a trigger signal, and sending the trigger signal to the oscillography mode storage module ACQ _ FIFO for carrying out trigger control on the storage of the voltage data and the current data; the oscillography mode storage module ACQ _ FIFO is used for storing voltage data and current data for an upper computer to read and display; the POWER value storage module POWER _ FIFO is used for storing POWER data for an upper computer to read and display.
In this embodiment, in order to ensure the precision of the power data, when the power operation module calculates the power data, the voltage data vol _ data and the current data cur _ data collected by the collection board card are converted into floating point numbers under the IEEE standard, and then the floating point numbers are sent to a floating point number multiplier for operation, and finally the result is restored to be integer unsigned number output power calculated value power _ data.
The bit width of the ACQ _ FIFO of the oscillometric memory module in this embodiment is denoted as
Figure BDA0003026605030000071
Figure BDA0003026605030000072
Represents ADBit width of C, so [ -P, P [)]＝[-UI,UI]The sum of the bit widths of the voltage and the current is collected for two paths of ADCs, the high bit is the current, the low bit is the voltage, and the depth is D. And the bit width and the depth of the POWER _ FIFO are consistent with those of the ACQ _ FIFO.
S202: setting gear parameters:
a user sets a voltage amplitude gear and a current amplitude gear through an upper computer, the amplitude gear determines the measuring range of voltage and current of the display screen, the measuring range of the voltage amplitude gear is recorded as [ -U, U ], and the measuring range of the current amplitude gear is recorded as [ -I, I ].
S203: data acquisition:
the acquisition board card acquires a signal to be detected, voltage data and current data are transmitted to the main FPGA board card, the main FPGA board card divides the received data into three paths, one path is spliced by the splicing module and then stored into the oscillography mode storage module ACQ _ FIFO, the other path is transmitted into the trigger module, the other path is transmitted into the POWER operation module to be operated to obtain corresponding POWER data, and then the corresponding POWER data are transmitted to the trigger module and the POWER value storage module POWER _ FIFO.
S204: triggering display by a default power triggering threshold value:
a user sets a triggering source and an edge triggering type of triggering through an upper computer, and if the power value of a certain channel is selected as the triggering source, a triggering module adopts a power triggering mode. The voltage triggering and the current triggering are very common triggering methods and are not the key point of the present invention, and the two triggering methods are not described herein again.
When a power triggering mode is adopted, the upper computer triggers a triggering source, an edge triggering type and a preset default power triggering threshold value
Figure BDA0003026605030000084
The power triggering signal is sent to a triggering module in the main FPGA board card (usually 0W or set according to experience), and the triggering module generates the power triggering signal by adopting the following method:
the trigger module triggers the power data received from the power operation module and the default power threshold value
Figure BDA0003026605030000085
And comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or a double edge of the power comparison square wave level as a power trigger signal according to the edge trigger type.
The main FPGA board card controls an oscillography module storage module ACQ _ FIFO to collect and store data according to a power trigger signal, an upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, corresponding power data are calculated and displayed in a quantification mode, and the specific method for quantifying the power data is as follows:
calculating power range [ P, P ] according to the voltage amplitude level and the current amplitude level]＝[-UI,UI]. The resolution of an ADC module in the acquisition board card is recorded as 2K (2K is 2)NN represents the bit width of the ADC), the unit increment Δ u of the voltage and the unit increment Δ i of the current can be expressed by the following formulas, respectively:
Figure BDA0003026605030000081
Figure BDA0003026605030000082
the unit increment of power Δ p can thus be found:
Figure BDA0003026605030000083
this formula characterizes that for each increase of the true power value by Δ p, the corresponding ADC quantized power value increases by 1. Therefore, for any power value p calculated from the voltage data and the current data, the calculation formula of the quantization result k (p) is as follows:
Figure BDA0003026605030000091
where k (0) represents the quantization result for a true power value of 0. The formula is used for representing the mapping relation between the trigger threshold power value set on the interface and the quantization threshold value in the system.
In addition, in practical application, the unstable triggering condition caused by input signal glitch and other reasons often occurs, and the problem can be solved by adopting a hysteresis comparison mode when generating a power comparison square wave level, and the specific method is as follows: the power trigger threshold value is shifted upwards to obtain a higher power threshold, the power trigger threshold value is shifted downwards to obtain a lower power threshold, the offset can be set according to the actual situation, when the power data is larger than the higher power threshold, the power comparison square wave level is judged to be 1, when the power data is lower than the lower power threshold, the power comparison square wave level is judged to be 0, and when the power data is processed between the higher power threshold and the lower power threshold, the power comparison square wave level keeps the last moment output value.
When the oscillography power analyzer is a multichannel one, the voltage data and the voltage data read from the oscillography module storage module ACQ _ FIFO by the upper computer are spliced by the voltage and current data of the multiple channels, so the upper computer can be firstly split into the voltage and the current according to the channels, then the voltage and the current of the same channel are multiplied to obtain the power value at the moment, and then the power value corresponding to the waveform of the whole voltage and current is obtained and displayed on the screen together with the acquired voltage and current values.
S205: setting a power trigger threshold value:
the upper computer obtains the default power trigger threshold value by adopting the quantization method in the step S203
Figure BDA0003026605030000092
Quantized value of
Figure BDA0003026605030000093
Displaying a cursor on the display screen, wherein the initial position of the cursor corresponds to the quantized value
Figure BDA0003026605030000094
The user adjusts the power trigger threshold value through the upper computer, and the adjusted power trigger threshold value is recorded as
Figure BDA0003026605030000095
The current power trigger threshold value obtained by the quantization method in step S203 is
Figure BDA0003026605030000096
Corresponding quantized value
Figure BDA0003026605030000097
The upper computer adjusts the vernier position to the quantized value
Figure BDA0003026605030000098
And (4) corresponding to the position.
By adopting the method, the power triggering threshold value vernier can be displayed while the power waveform is displayed, and the relative position of the vernier of the power triggering threshold value and the actual power waveform can be used as a reference for setting the triggering threshold value by a user, so that the visualized adjustment of the power triggering threshold value is realized, and the actual requirement is better adapted.
S206: auxiliary reference source setting:
the method comprises the steps that a user selects whether an auxiliary reference source is needed to generate a power trigger signal together according to actual needs, if not, an auxiliary reference source work enabling signal is set to be invalid, if needed, the auxiliary reference source work enabling signal is set to be valid, meanwhile, an auxiliary reference source selection signal is set and used for selecting voltage data or current data to be adopted as an auxiliary reference source, and a voltage threshold value or a current threshold value is set.
S207: generating a trigger signal:
when the trigger module receives an invalid auxiliary reference source work enabling signal, the following method is adopted to generate a power trigger signal:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure BDA0003026605030000101
And comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or a double edge of the power comparison square wave level as a power trigger signal according to the edge trigger type.
When the trigger module receives the effective auxiliary reference source work enabling signal, the power trigger signal is generated by adopting the following method:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure BDA0003026605030000102
And comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or a double edge of the power comparison square wave level as an initial trigger signal according to the edge trigger type.
And selecting voltage data or current data according to the auxiliary reference source selection signal, and comparing the voltage data or the current data with a voltage threshold value or a current threshold value to generate an auxiliary comparison square wave level.
And performing phase comparison on the initial trigger signal and the auxiliary comparison square wave level to obtain a power trigger signal.
Similarly, when generating the auxiliary comparison square wave level, a hysteresis comparison method may also be adopted to avoid unstable triggering caused by glitches in the voltage data or the current data.
According to analysis in the background art, when the voltage and current signals are single harmonic signals, the obtained power signal frequency is twice of the voltage and current signal frequency, and when the voltage and current power is displayed on a screen at the same time, positive and negative overturning jumping of the voltage and current can continuously occur, so that observation of a user on waveforms is influenced. The significance of adding an auxiliary comparison square wave level is that a voltage or current comparison level is used as an auxiliary decision, when the voltage or current comparison level is high, the power trigger pulse is valid, otherwise, the power trigger pulse is invalid. Therefore, the power trigger can be ensured to be triggered only once in one voltage or current signal period, and positive and negative overturning jump is avoided.
S208: adjusting the trigger point and the display waveform phase:
in an actual circuit, because of the path delay of the internal wiring of the FPGA and the long time required for the floating-point number multiplication, a certain time deviation exists between the time of generating the trigger signal and the real trigger time, and as a result of the deviation, the position of the trigger point displayed on the display interface is delayed, and in order to avoid the situation, a delay correction function needs to be introduced.
In the read/write control of the FIFO, the program full signal prog _ full is often used as a decision flag to enter a wait for trigger state. In the invention, the programming full depth set in the upper computer is recorded as prog _ full _ thresh (usually half of the total depth of FIFO, namely D/2), the delay caused by the calculation of POWER data by the POWER operation module is recorded as n clock cycles, the upper computer respectively sends prog _ full _ thresh-n as the programming full depth to the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO, when the data stored in the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO reach the programming full depth, the corresponding programming full signal is pulled high, the situation is the same as the conventional situation, at the moment, the two FIFOs enter the state of writing edge polishing points and wait for the arrival of POWER trigger signals. By adopting the method, the function of advancing the trigger point by n clock cycles compared with the trigger point which is not corrected is realized.
According to the invention, through the above mode, the upper computer realizes the phase adjustment of the trigger time in a mode of changing the full depth of FIFO programming, and further artificially corrects the position deviation of the trigger point generated by path delay and power operation.
S209: triggering display:
the main FPGA board card controls the oscillography module storage module ACQ _ FIFO to collect and store data according to the POWER trigger signal generated in the step S207, the upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, meanwhile, the upper computer reads corresponding POWER data from the POWER value storage module POWER _ FIFO, and then the read data are displayed quantitatively on the display screen.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (2)

1. A transient power operation and triggering method of an oscillography power analyzer is characterized by comprising the following steps:
s1: a splicing module, a POWER operation module, an oscillography mode storage module ACQ _ FIFO, a POWER value storage module POWER _ FIFO and a trigger module are configured in a main FPGA board card of the oscillography POWER analyzer, wherein the splicing module is used for receiving voltage data and current data and sending the voltage data and the current data into the oscillography mode storage module ACQ _ FIFO for storage after splicing; the POWER operation module is used for receiving the voltage data and the current data, and respectively sending the POWER data obtained by operation to the trigger module and the POWER value storage module POWER _ FIFO; the trigger module is used for receiving the voltage data, the current data and the power data, selecting corresponding data according to a trigger source and an edge trigger type set by a user to generate a trigger signal, and sending the trigger signal to the oscillography mode storage module ACQ _ FIFO for carrying out trigger control on the storage of the voltage data and the current data; the oscillography mode storage module ACQ _ FIFO is used for storing voltage data and current data for an upper computer to read and display; the POWER value storage module POWER _ FIFO is used for storing POWER data for an upper computer to read and display;
s2: setting a voltage amplitude level and a current amplitude level by a user through an upper computer, wherein the amplitude level determines the voltage and current measuring range of the display screen, the measuring range of the voltage amplitude level is recorded as [ -U, U ], and the measuring range of the current amplitude level is recorded as [ -I, I ];
s3: the acquisition board card acquires a signal to be detected, and transmits acquired voltage data and current data to the main FPGA board card, the main FPGA board card divides the received voltage data and current data into three paths, one path is spliced by the splicing module and then stored in the oscillography mode storage module ACQ _ FIFO, the other path is transmitted to the trigger module, the other path is transmitted to the POWER operation module to be operated to obtain corresponding POWER data, and then the corresponding POWER data is transmitted to the trigger module and the POWER value storage module POWER _ FIFO;
s4: the user sets a trigger source and an edge trigger type of power trigger through the upper computer, and if the power value of a certain channel is selected as the trigger source, the trigger source triggersThe module adopts a power triggering mode; at the moment, the upper computer triggers the trigger source, the edge trigger type and the preset default power trigger threshold value
Figure FDA0003026605020000011
And sending the power trigger signal to a trigger module in the main FPGA board card, wherein the trigger module generates the power trigger signal by adopting the following method:
the trigger module triggers the power data received from the power operation module and the default power threshold value
Figure FDA0003026605020000012
Comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or two edges of the power comparison square wave level as power trigger signals according to the edge trigger type;
the main FPGA board card controls an oscillography module storage module ACQ _ FIFO to collect and store data according to a power trigger signal, an upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, corresponding power data are calculated and displayed in a quantification mode, and the specific method for quantifying the power data is as follows:
recording the resolution of an ADC module in the acquisition board card as 2K, and calculating a quantization result K (p) of any power value p calculated according to the voltage data and the current data according to the following calculation formula:
Figure FDA0003026605020000021
where Δ p represents a unit increment of power,
Figure FDA0003026605020000022
s5: the upper computer obtains the default power trigger threshold value by adopting the quantization method in the step S3
Figure FDA0003026605020000023
Quantized value of
Figure FDA0003026605020000024
Displaying a cursor on the display screen, wherein the initial position of the cursor corresponds to the quantized value
Figure FDA0003026605020000025
The user adjusts the power trigger threshold value through the upper computer, and the adjusted power trigger threshold value is recorded as
Figure FDA0003026605020000026
The current power trigger threshold value obtained by the quantization method in the step S3 is
Figure FDA0003026605020000027
Corresponding quantized value
Figure FDA0003026605020000028
The upper computer adjusts the vernier position to the quantized value
Figure FDA0003026605020000029
A corresponding position;
s6: a user selects whether an auxiliary reference source is needed to generate a power trigger signal together according to actual needs, if not, the auxiliary reference source work enabling signal is set to be invalid, if so, the auxiliary reference source work enabling signal is set to be valid, meanwhile, an auxiliary reference source selection signal is set and is used for selecting voltage data or current data to be adopted as an auxiliary reference source and setting a voltage threshold value or a current threshold value;
s7: when the trigger module receives an invalid auxiliary reference source work enabling signal, the following method is adopted to generate a power trigger signal:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure FDA00030266050200000211
Comparing to generate power comparison square wave level, triggering according to edgeSelecting the rising edge, the falling edge or the double edges of the power comparison square wave level as power trigger signals;
when the trigger module receives the effective auxiliary reference source work enabling signal, the power trigger signal is generated by adopting the following method:
the trigger module triggers the power data received from the power operation module and the power trigger threshold value
Figure FDA00030266050200000210
Comparing to generate a power comparison square wave level, and selecting a rising edge, a falling edge or two edges of the power comparison square wave level as an initial trigger signal according to the edge trigger type;
selecting voltage data or current data according to the auxiliary reference source selection signal, and comparing the voltage data or the current data with a voltage threshold value or a current threshold value to generate an auxiliary comparison square wave level;
performing phase comparison on the initial trigger signal and the auxiliary comparison square wave level to obtain a power trigger signal;
s8: recording the programming full depth set in the upper computer as prog _ full _ thresh, recording the delay caused by the calculation of POWER data by the POWER operation module as n clock cycles, and then respectively sending prog _ full _ thresh-n serving as the programming full depth to the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO by the upper computer, and when the data stored in the oscillography module storage module ACQ _ FIFO and the POWER value storage module POWER _ FIFO reach the programming full depth, pulling up the corresponding programming full signal to wait for the arrival of a POWER trigger signal;
s9: the main FPGA board card controls the oscillography module storage module ACQ _ FIFO to collect and store data according to the POWER trigger signal generated in the step S7, the upper computer reads voltage data and current data from the oscillography module storage module ACQ _ FIFO, meanwhile, the upper computer reads corresponding POWER data from the POWER value storage module POWER _ FIFO, and then the read data are displayed quantitatively on the display screen.
2. The transient power calculating and triggering method as claimed in claim 1, wherein the step S4 and the step S7 generate the power comparison square wave level and the auxiliary comparison square wave level by using a hysteresis comparison method.
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CN201508381U (en) * 2009-07-21 2010-06-16 北京普源精电科技有限公司 Digital oscilloscope with video triggering function
US20120041701A1 (en) * 2010-08-13 2012-02-16 Tektronix, Inc. Time-domain triggering in a test and measurement instrument
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