CN109755226A - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
- Publication number
- CN109755226A CN109755226A CN201810884731.5A CN201810884731A CN109755226A CN 109755226 A CN109755226 A CN 109755226A CN 201810884731 A CN201810884731 A CN 201810884731A CN 109755226 A CN109755226 A CN 109755226A
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- China
- Prior art keywords
- semiconductor package
- antenna element
- lower packaging
- substrate
- irradiation unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims description 70
- 239000010410 layer Substances 0.000 claims description 68
- 238000007789 sealing Methods 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 230000005855 radiation Effects 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 13
- 239000011247 coating layer Substances 0.000 claims description 6
- 239000010949 copper Substances 0.000 description 8
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 101100491335 Caenorhabditis elegans mat-2 gene Proteins 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002552 dosage form Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000003447 ipsilateral effect Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/44—Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna, e.g. means for giving an antenna an aesthetic aspect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/48—Earthing means; Earth screens; Counterpoises
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0006—Particular feeding systems
- H01Q21/0075—Stripline fed arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
- H01Q21/065—Patch antenna array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/045—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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Abstract
公开了一种半导体封装件及其制造方法。所述半导体封装件包括具有至少一个电子器件的下封装件以及设置在所述下封装件的上表面上的天线单元,其中,所述天线单元包括:接地部,设置在所述下封装件的上表面上;辐射部,设置为与所述接地部分开;以及支撑部,将所述辐射部和所述接地部分开,位于所述辐射部与所述接地部之间的至少一部分是空的空间。
Description
本申请要求于2017年11月2日提交到韩国知识产权局的第10-2017-0145398号韩国专利申请的优先权和权益,出于所有目的,该韩国专利申请的全部公开内容通过引用包含于此。
技术领域
本公开涉及一种半导体封装件及其制造方法。
背景技术
为了高速使用高质量和高容量数据,半导体封装件的频带已增加。例如,对于用于无线通信的半导体封装件,考虑使用27GHz或更高的毫米波段的技术。
在毫米波段中,频率的波长缩短为以毫米为单位,因此,使用传统半导体封装件结构可能使性能劣化。
发明内容
提供该发明内容来以简要的形式介绍将在下面在具体实施方式中进一步描述的构思的选择。该发明内容不意图确定所要求保护的主题的关键特征或必要特征,也不意图用作帮助确定所要求保护的主题的范围。
在一个总的方面,一种半导体封装件包括:下封装件,包括一个或更多个电子器件;以及天线单元,设置在所述下封装件的上表面上,其中,所述天线单元包括:接地部,设置在所述下封装件的上表面上;辐射部,包括设置为与所述接地部分开的一个或更多个辐射件;以及支撑部,将所述辐射部和所述接地部分开,其中,位于所述辐射部与所述接地部之间的至少一部分是空的空间。
所述支撑部可以包括:第一支撑部,支撑所述辐射部的馈电线;以及第二支撑部,支撑所述辐射部的所述辐射件。
所述下封装件可以包括基板和密封安装在所述基板上的所述电子器件的密封部,并且所述天线单元可以设置在所述密封部上。
连接部可以设置在所述密封部的侧表面上,并且将所述天线单元与所述基板电连接。
所述连接部可以包括:第一连接部,将所述接地部与所述基板上的接地垫连接;以及第二连接部,将所述辐射部与所述基板上的信号垫连接。
所述信号垫与所述接地垫可以暴露到所述密封部的外部。
所述半导体封装件还可以包括穿过所述密封部将所述天线单元和所述基板电连接的连接导体。
所述下封装件可以包括容纳所述电子器件的芯基板和设置在所述芯基板的相对的表面上的再布线层,并且所述接地部可以设置在所述芯基板的上表面上设置的所述再布线层上。
所述半导体封装件还可以包括穿过所述支撑部将所述辐射部和所述下封装件电连接的连接导体。
所述辐射部可以包括:金属层,设置在所述支撑部上;以及镀覆层,设置在所述金属层上。
所述半导体封装件还可以包括绝缘板,所述辐射部结合到所述绝缘板的下表面。
所述半导体封装件可以发送和接收超高频带中的无线电信号。
所述半导体封装件可以发送和接收毫米波段中的无线电信号。
在另一总的方面,一种半导体封装件包括:下封装件,可以包括设置在基板上的一个或更多个电子器件和密封所述电子器件的密封部;天线单元,设置在所述密封部的上表面上,其中,所述天线单元可以包括:接地部,设置在所述下封装件的上表面上;辐射部,设置为与所述接地部分开;以及连接部,设置在所述密封部的侧表面上,并且将所述天线单元和所述基板电连接。
在另一总的方面,一种制造半导体封装件的方法可以包括:制备下封装件;以及在所述下封装件的上表面上形成天线单元,其中,形成所述天线单元的步骤包括:在所述下封装件的上表面上形成接地部;以及在所述接地部上堆叠支撑部和辐射部,其中,位于所述辐射部与所述接地部之间的至少一部分是空的空间。
制造半导体封装件的方法可以包括:将所述天线单元和所述下封装件的所述基板电连接。
将所述天线单元和所述下封装件的所述基板电连接的步骤可以包括:部分地切割所述下封装件以暴露设置在所述下封装件中的垫;沿着所述下封装件的切割表面将所述天线单元和所述垫电连接;以及完全地切割所述下封装件。
将所述天线单元和所述下封装件的所述基板电连接的步骤可以包括:在所述下封装件中形成通孔以暴露设置在所述下封装件中的垫;以及用导电材料填充所述通孔以将所述垫和所述天线单元电连接。
其他特征和方面将通过以下具体实施方式、附图和权利要求而明显。
附图说明
图1是示意性示出根据实施例的半导体封装件的透视图;
图2是沿图1的线II-II′截取的截面图;
图3是沿图1的线III-III′截取的截面图;
图4是沿图2的线IV-IV′截取的截面图;
图5至图7是示意性示出制造图1中所示的半导体封装件的方法的示图;
图8是示意性示出根据实施例的半导体封装件的截面图;
图9是示意性示出根据实施例的半导体封装件的截面图;
图10是示意性示出制造图9中所示的半导体封装件的方法的示图;
图11是示意性示出根据实施例的半导体封装件的透视图;以及
图12是沿图11的线XII-XII′截取的截面图。
在所有的附图和具体实施方式中,相同的附图标号表示相同的元件。附图可以不是按比例的,出于清楚、说明和方便的目的,附图中元件的相对尺寸、比例和描绘可以被夸大。
具体实施方式
提供以下具体实施方式以帮助读者获得对这里所描述的方法、设备和/或系统的全面理解。然而,在理解本申请的公开内容后,这里所描述的方法、设备和/或系统的各种改变、变型及等同物将是明显的。例如,这里所描述的操作顺序仅仅是示例,其并不限于这里所阐述的顺序,而是除了必须以特定顺序发生的操作之外,在理解本申请的公开内容后可做出将是明显的改变。此外,为了提高清楚性和简洁性,可省略本领域已知的特征的描述。
这里所描述的特征可按照不同的形式实现,并且将不被解释为受限于这里所描述的示例。更确切地说,已经提供这里所描述的示例仅仅为示出在理解本申请的公开内容后将是明显的实现这里所描述的方法、设备和/或系统的许多可行方式中的一些方式。
在整个说明书中,当诸如层、区域或基板的元件被描述为“位于”另一元件“上”、“连接到”另一元件或者“结合到”另一元件时,该元件可以直接“位于”所述另一元件“上”、直接“连接到”所述另一元件或者直接“结合到”所述另一元件,或者可存在介于两者之间的一个或更多个其他元件。相比之下,当元件被描述为“直接位于”另一元件“上”、“直接连接到”另一元件或者“直接结合到”另一元件时,可能不存在介于两者之间的其他元件。
如这里所使用的,术语“和/或”包括相关所列项中的任何一个或者相关所列项中的任何两个或更多个的任何组合。
尽管可在这里使用诸如“第一”、“第二”和“第三”的术语来描述各种构件、组件、区域、层或部分,但是这些构件、组件、区域、层或部分不受这些术语限制。更确切地说,这些术语仅用于将一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分区分开。因而,在不脱离示例的教导的情况下,这里所描述的示例中所称的第一构件、组件、区域、层或部分还可以被称为第二构件、组件、区域、层或部分。
为了易于描述,这里可以使用诸如“在……上方”、“上部”、“在……下方”以及“下部”的空间相对术语,以描述如图所示的一个元件与另一元件的关系。这样的空间相对术语意图包含除了图中所描绘的方位以外装置在使用或操作中的不同方位。例如,如果图中的装置翻转,则描述为相对于另一元件位于“上方”或“上部”的元件随后将相对于所述另一元件位于“下方”或“下部”。因而,术语“在……上方”根据装置的空间方位包括上方和下方两种方位。装置也可以按照其他方式(例如,旋转90度或处于其他方位)定位,并且将对这里使用的空间相对术语做出相应解释。
这里使用的术语仅用于描述各种示例,并且不用于限制本公开。除非上下文另外清楚地指出,否则单数形式也意图包括复数形式。术语“包含”、“包括”和“具有”列举存在所陈述的特征、数量、操作、构件、元件和/或它们的组合,但是不排除存在或添加一个或更多个其他特征、数量、操作、构件、元件和/或它们的组合。
由于制造技术和/或公差,可发生附图中所示的形状的变型。因而,这里所描述的示例不限于附图中所示的特定形状,而是包括在制造期间所发生的形状的改变。
这里所描述的示例的特征可按照在理解本申请的公开内容后将是明显的各种方式进行组合。此外,尽管这里所描述的示例具有各种配置,但是在理解本申请的公开内容后将是明显的其他配置是可能的。
在实施例中,第一表面和第二表面指构件中的布置在相对方向、相反方向或不同方向上的两个表面。
图1是示意性示出根据实施例的半导体封装件的透视图,图2是沿图1的线II-II′截取的截面图。图3是沿图1的线III-III′截取的截面图,图4是沿图2的线IV-IV′截取的截面图。
参照图1至图4,根据实施例的半导体封装件100是利用毫米波段发送和接收无线电信号的半导体封装件。半导体封装件100包括下封装件90和天线单元80。下封装件90包括基板(或板)10、电子器件1和密封部50。
基板10可以使用本领域中已知的各种基板(例如,印刷电路板(PCB)、柔性基板、陶瓷基板、玻璃基板等)形成。
基板10可以是通过重复地堆叠多个绝缘层和多个布线层形成的多层基板。然而,通过在一个绝缘层的两侧上形成布线层而形成的双侧板也可以用在实施例中。
布线层将如下文中所描述的电子器件1和天线单元80电连接。可以使用诸如Cu、Ni、Al、Ag和Au的具有导电性的金属作为布线层。
在其上安装下文中描述的电子器件1的安装垫2a、信号垫2b和接地垫2c被设置在基板10的一个表面上。
所有的安装垫2a设置在如下文中所描述的密封部50之内。同时,信号垫2b和接地垫2c被设置为与基板10的侧表面相邻,或者暴露于基板10的侧表面。另外,信号垫2b和接地垫2c从基板10的一个表面暴露到如下文中所描述的密封部50的外部。
电子器件1安装在基板10的一个表面上,并且包括无源器件和有源器件中的至少一种。电子器件1可以被构造为一个或多个电子器件。
电子器件1电连接到如在下文中所描述的天线单元80,并且通过天线单元80执行无线通信。为此,电子器件1可以包括(但是不限于)多模拟组件(multiple analogcomponents)(MAC)或基带信号处理电路。
密封部50形成在基板10的一个表面上。因此,密封部50被布置为使安装在基板10的一个表面上的电子器件1嵌入。
密封部50填充电子器件1之间的空间以防止电子器件1之间发生电短路,并且覆盖电子器件1的外部以将电子器件1固定到基板10来安稳地保护电子器件1免受外部冲击影响。
密封部50使用绝缘材料形成。在实施例中,环氧模塑料(EMC)被用作密封部50的材料,但不限于此。
根据实施例的密封部50整体形成为六面体形状。然而,密封部50的形状不限于此,并且密封部50的形状可以被变型为各种形状,只要密封部50的上表面可以形成为平坦的即可。
在实施例中,密封部50的上表面形成为具有比基板10的一个表面小的面积。在半导体封装件的制造工艺期间,该结构使信号垫和连接垫暴露到外部,这可以通过对制造方法的描述而被清楚地理解。
连接端子24结合到基板10的另一表面。
当半导体封装件100被安装在电子装置中设置的主板(未示出)上时,连接端子24使半导体封装件100和主板物理连接且电连接。连接端子24可以使用诸如焊料的导电粘合剂形成,但不限于此。
天线单元80设置在下封装件90的上表面上。具体地,天线单元80设置在密封部50的上表面上,并且电连接到基板10和电子器件1。实施例的天线单元80可以辐射或接收毫米波段的RF信号。
天线单元80包括辐射部82、接地部81、支撑部83和连接部84。
辐射部82设置在半导体封装件100的顶部处,并且由下文中所描述的支撑部83支撑。
实施例的辐射部82被构造为阵列天线。因此,辐射部82包括多个辐射件82a和将辐射件82a电连接到基板10的馈电线82b。
辐射件82a形成为方形贴片,多个辐射件82a彼此分开规则的间隔。
然而,辐射件82a的构造不限于此。例如,辐射件82a可以具有诸如曲折形状或多边形形状的各种其他形状,只要其可在毫米波频带中执行无线通信即可。
馈电线82b将辐射件82a中的每个电连接到如下文中所描述的第二连接部84b。馈电线82b使用与辐射件82a的材料相同的材料形成,并且设置在其上设置有辐射件82a的同一平面上。
接地部81设置在密封部50的上表面上。辐射部82与接地部81分开预定距离,并设置在接地部81上方。
接地部81形成为具有比辐射部82的面积大的面积。因此,当辐射部82投影到接地部81上时,辐射部82的整体区域可以设置在接地部81内。然而,本公开不限于此。
支撑部83设置在辐射部82与接地部81之间。因此,辐射部82设置在支撑部83上,支撑部83用于支撑辐射部82。
支撑部83不完全地填充辐射部82与接地部81之间的空间,而仅占据了该空间的一部分来支撑辐射部82。因此,其中设置有空气的空的空间E设置在辐射部82与接地部81之间。
在实施例中,支撑部83可以被分为支撑馈电线82b的第一支撑部83a和支撑辐射件82a的第二支撑部83b。
第一支撑部83a沿着馈电线82b形成,并且不形成在辐射件82a下方。然而,本公开不限于此,而是可以被构造为部分地支撑辐射件82a。
在实施例中,第一支撑部83a被形成为连续的壁,但是其不限于此,第一支撑部83a可以不连续地形成。
第二支撑部83b设置在辐射件82a下方,以支撑辐射件82a。
第二支撑部83b以比辐射件82a的面积小的面积与辐射件82a接触以支撑辐射件82a。在实施例中,描述了一个第二支撑部83b支撑一个辐射件82a的情况。具体地,第二支撑部83b设置在辐射件82a的中央处,并且具有柱形形状以支撑辐射件82a。
然而,本公开的构造不限于此,而是可以被各种变型,使得多个第二支撑部83b被构造为支撑一个辐射件82a,并且支撑辐射件82a的边缘而不是辐射件82a的中央。
实施例的支撑部83不在形状和尺寸上限制,只要其将辐射件82a与接地部81分开并且支撑辐射件82a,使得辐射件82a的至少一部分直接面对支撑部83即可。
支撑部83使用诸如聚合物的绝缘材料形成,并且结合到接地部81的表面。然而,本公开不限于此,支撑部83可以直接结合到密封部50。在这种情况下,接地部81设置在密封部50的上表面的未设置支撑部83的区域中。
连接部84设置在密封部50的表面上,并且包括将接地部81和基板10电连接的第一连接部84a以及将辐射部82和基板10连接的第二连接部84b。
第一连接部84a设置在密封部50的侧表面上并且与从基板10的一个表面暴露到密封部50的外部的接地垫2c连接。第二连接部84b设置在密封部50的侧表面以及支撑部83的第一支撑部83a的侧表面上,并且连接到暴露到密封部50的外部的信号垫2b。
第一连接部84a和第二连接部84b可以一起设置在密封部50的四侧之中的同一侧上。然而,本公开不限于此,第一连接部84a和第二连接部84b可以布置在不同侧上。在实施例中,示出了其中连接部84仅设置在密封部50的四侧之中的一侧上的情况作为示例,但连接部84可以分别设置在多个侧上。
在如上所述构造的根据实施例的半导体封装件100中,天线单元80设置在密封部50的上表面上。因此,天线单元80与电子器件1之间的距离可以最小化,使信号功率的损耗最小化,并且减少反射率的劣化。
另外,为了使损耗最小化,根据实施例的天线单元80具有在辐射部82与接地部81之间存在空气层的空的空间E。当空气被用作介电层时,损耗因子是零。因此,因为使天线单元80的损耗减少或最小化,所以可以在诸如毫米波段的超高频带中提高天线的发送/接收效率。
在下文中,将参照图5至图7来描述制造图1中所示的半导体封装件的方法。出于描述的目的,图5至图7示出了沿图1的线II-II′截取的截面图。
根据制造根据实施例的半导体封装件的方法,下封装件90和天线单元80的部分被单独地制造,并且被结合。
参照制造天线单元80的方法,如图5中所示,在操作S01中首先在载体基板P上形成第一金属层20。这里,第一金属层20可以使用铜(Cu)形成。第一金属层20可以通过诸如粘合带的结合构件17的介质来设置在载体基板P上。
随后,在操作S02中,在第一金属层20上形成掩模层(未示出),并且去除第一金属层20的一部分以形成辐射部82。掩模层可以使用感光膜(干膜光致抗蚀剂(DFR))或光致抗蚀剂(PR,Photoresist)形成,但不限于此。
随后,在操作S03中将支撑层830堆叠在辐射部82上。支撑层830可以形成为覆盖整个辐射部82或者可以被部分地形成。
而后将支撑层830形成为支撑部83。因此,支撑层830可以使用诸如树脂或聚合物的绝缘材料形成,但是支撑层830的材料不限于此。
随后,在操作S04中去除支撑层830的一部分以形成支撑部83。在该工艺期间,将支撑部83分开地形成为支撑馈电线82b的第一支撑部83a和支撑辐射件82a的第二支撑部83b。
其后,在操作S05中制备下封装件90。在该阶段提供的下封装件90是这样的封装件:通过单个基板条上的封装区域制造多个封装件,而不是被切割为如图1中所示的单个封装件的形式。然而,本公开不限于此。
另外,在该阶段提供的下封装件90中,接地部81设置在密封部50上。因此,可以在制造下封装件90的工艺中与下封装件90一起形成接地部81。
例如,可以通过在密封部50的整个上表面上形成第二金属层并且其后去除第二金属层的一部分来形成接地部81。第二金属层可以使用铜(Cu)形成,但不限于此。
当下封装件90被制备时,在操作S06中将形成在载体基板P上的结构转移到下封装件90。这里,转移该结构使得支撑部83结合到接地部81的表面。
当完成转移时,去除载体基板P。因此,辐射部82被暴露到外部。在该阶段,还将粘合构件17与载体基板P一起去除。
其后,在操作S07中沿着切割线C部分地切割下封装件90。执行该操作以使形成在基板10上的信号垫2b和接地垫2c暴露。
因此,在信号垫2b和接地垫2c设置在基板的表面上的情况下,信号垫2b和接地垫2c可以通过仅切割密封部50而暴露到外部。然而,在信号垫2b和接地垫2设置在基板内的情况下,将基板10的一部分与密封部50一起切割以将信号垫2b和接地垫2c暴露到外部。
随后,在部分切割的表面上形成连接部84。可以通过以下操作形成连接部84:在辐射部82上设置掩模层M的操作S08;基于掩模层M在切割表面上形成第三金属层23的操作S09;以及去除掩模层M的操作S10。
这里,掩模层M还设置在切割表面上,使得第三金属层23仅形成在形成连接部84的部分中。可以通过溅射形成第三金属层23,但不限于此。
当去除掩模层M时,第三金属层23形成为将接地部81和接地垫2c连接的第一连接部84a(图4)以及将辐射部82和信号垫2b连接的第二连接部84b。
随后,在操作S11中将连接端子24安装在基板10上,并且在操作S12中沿切割线C完全地切割下封装件90,以形成图1中所示的半导体封装件。
同时,根据实施例的半导体封装件不限于上述实施例,随之还存在各种变型。
图8是示意性示出根据实施例的半导体封装件的截面图。
实施例的半导体封装件具有布置为穿透密封部50的连接导体86,而不具有上述连接部(图1的84)。
连接导体86的一端结合到基板10,连接导体86的另一端连接到辐射部82或接地部81。在图8中,仅示出了将辐射部82和基板10连接的连接导体86。在这种情况下,连接导体86还穿透支撑部83并且将辐射部82和基板10的信号垫2b连接。
虽然未示出,但还设置了将接地部81和基板10的接地垫(未示出)连接的连接导体。
连接导体86可以使用例如铜、金、银、铝或它们的合金的导电材料形成。连接导体86可以被构造为各种形式,只要其可将基板10和天线单元80电连接即可。
在上述操作S06之后,制造根据实施例的半导体封装件的方法可以包括形成穿透支撑部83和密封部50的通孔并用导电材料填充通孔以形成连接导体86的操作。
可以利用激光钻孔形成通孔,但不限于此。可以通过利用焊料或导电膏填充通孔或者通过镀覆来形成连接导体86。
图9是示意性示出根据实施例的半导体封装件的截面图。
参照图9,在根据实施例的半导体封装件中,再布线部15a和15b形成在容纳电子器件1的芯基板15的相对的表面上,天线单元80设置在两个再布线部15a和15b之中设置在上方的再布线部15a上。芯基板15包括密封部51。
因为根据实施例的天线单元80直接设置在形成有电路布线的再布线部15a上,所以接地部81直接连接到下封装件90的接地垫2c。
辐射部82通过穿透支撑部83的连接导体86a连接到下封装件90的信号垫2b。然而,不限于此,可以做出各种变型,类似于上述实施例,使得连接部(图1的84)沿着支撑部83的侧表面形成以将辐射部82和信号垫2b连接。
另外,在实施例中,辐射部82可以包括金属层821和以镀覆方式堆叠在金属层821上的镀覆层822。然而,不限于此,存在镀覆层822被省略且辐射部82仅形成为金属层821的各种变型示例。
在下文中,将参照图10描述制造图9中所示的半导体封装件的方法。
首先,在操作S001中在下封装件90的上表面上形成接地部81。可以通过光刻工艺来形成接地部81,但不限于此。
接着,在操作S002中在下封装件90的上表面上形成支撑部83。可以通过在接地部81上形成支撑层(未示出),然后使其图案化来形成支撑部83。
在该工艺期间,部分地去除支撑部83的内部以形成开口OP。开口OP形成为完全地穿透支撑部83,下封装件90的信号垫2b通过开口OP暴露到外部。开口OP被用作其中在辐射部82与接地部81之间存在有空的空间E以及设置有连接导体86a的空间。
随后,在操作S003中在支撑部83上形成金属层821。可以通过在支撑部83上堆叠金属构件,然后去除金属构件的一部分来形成金属层821。在该工艺期间,其中设置有信号垫2b的开口OP暴露到金属层821的外部。
金属构件可以形成为薄金属板。另外,金属构件可以被堆叠为完全地覆盖支撑部83。
可以通过光刻工艺将金属构件形成为金属层821,但不限于此。
随后,在操作S004中用导电材料填充其中设置有信号垫2b的开口OP以形成连接导体86a。可以通过镀覆工艺或丝网印刷工艺来执行该操作,但不限于此。
在该工艺期间,还将导电材料堆叠在金属层821的上表面上以形成镀覆层822。
同时,可以另外执行在开口OP的内部上和金属层821的上表面上形成种子层的操作,以改善连接导体86a或镀覆层822的结合稳定性。
在这种情况下,可以通过以下操作完成连接导体86a:在金属层821的表面上和开口OP的内部形成种子层的操作;在种子层上形成掩模层的操作;用导电材料填充开口OP的操作;以及去除掩模层和种子层的操作。
种子层可以使用诸如钛(Ti)、铝(Al)或铜(Cu)等的材料形成,但本公开不限于此。
图11是示意性示出根据实施例的半导体封装件的透视图,图12是沿图11的线XII-XII′截取的截面图。
参照图11和图12,实施例的天线单元80设置有在支撑部83上的绝缘板87。另外,辐射部82设置在绝缘板87的下表面上。这里,绝缘板87的下表面指面对接地部81的表面。
辐射部82的一部分可以插入到绝缘板87中。在这种情况下,辐射部82与绝缘板87之间的接触面积增加,其增加了辐射部82与绝缘板87之间的结合力。然而,本公开不限于此,绝缘板87的下表面可以形成为平坦的,并且辐射部82可以利用诸如粘合带的粘合构件附着到绝缘板87的下表面。
在实施例中,支撑部83支撑绝缘板87,而不支撑辐射部82。因此,设置辐射部82使得其全部(不是部分)直接面对接地部81,因为仅空的空间E位于辐射部82与接地部81之间,所以仅空气层设置在其中。
然而,本公开的构造不限于此,可以做出各种变型,类似于上述实施例,使得支撑部83部分地支撑辐射部82,或者使得支撑部83沿馈电线(未示出)布置以支撑馈电线82b和绝缘板87两者。
在实施例中,如图11中所示,接地部81和辐射部82通过连接部84连接到基板10。然而,本公开不限于此,可以做出各种变型,使得如图8或图9的实施例中接地部81和辐射部82通过连接导体86或者86a连接到基板10。
例如,上述实施例可以彼此结合。例如,图8中所示的天线单元可以通过图5至图7中所示的方法来制造,同样地,图1中所示的天线单元可以通过图10中所示的方法来制造。
如上所阐述,在根据实施例的半导体封装件中,天线单元设置在密封部的上表面上。因此,可以使天线单元与电子器件之间的距离最小化。另外,因为设置有空气层的空的空间设置在辐射部与接地部之间,所以天线单元中产生的损耗可以最小化,因此,可以在诸如毫米波段的超高频带中提高天线的发送和接收效率。
虽然本公开包括特定的示例,但是在理解了本申请的公开内容后将明显的是,在不脱离权利要求及其等同物的精神和范围的情况下,可在这些示例中做出形式和细节上的各种改变。这里描述的示例仅将被视为描述性的含义,并非出于限制的目的。在每个示例中的特征或方面的描述将被认为可适用于其他示例中的类似特征或方面。如果以不同的顺序执行所描述的技术,和/或如果以不同的方式组合所描述的系统、架构、装置或者电路中的组件,和/或用其他组件或者它们的等同物进行替换或者补充描述的系统、架构、装置或者电路中的组件,则可获得适当的结果。因此,本公开的范围不由具体实施方式限定,而是由权利要求及其等同物所限定,并且权利要求及其等同物范围内的所有改变将解释为被包括在本公开中。
Claims (18)
1.一种半导体封装件,所述半导体封装件包括:
下封装件,包括一个或更多个电子器件;以及
天线单元,设置在所述下封装件的上表面上,
其中,所述天线单元包括:接地部,设置在所述下封装件的上表面上;辐射部,包括设置为与所述接地部分开的一个或更多个辐射件;以及支撑部,将所述辐射部和所述接地部分开,
其中,位于所述辐射部与所述接地部之间的至少一部分是空的空间。
2.根据权利要求1所述的半导体封装件,其中,
所述支撑部包括:
第一支撑部,支撑所述辐射部的馈电线;以及
第二支撑部,支撑所述辐射部的所述辐射件。
3.根据权利要求1所述的半导体封装件,其中,
所述下封装件包括基板和密封安装在所述基板上的所述电子器件的密封部,并且
所述天线单元设置在所述密封部上。
4.根据权利要求3所述的半导体封装件,其中,所述天线单元还包括:
连接部,设置在所述密封部的侧表面上,并且将所述天线单元与所述基板电连接。
5.根据权利要求4所述的半导体封装件,其中,
所述连接部包括:
第一连接部,将所述接地部与所述基板上的接地垫连接;以及
第二连接部,将所述辐射部与所述基板上的信号垫连接。
6.根据权利要求5所述的半导体封装件,其中,
所述信号垫与所述接地垫暴露到所述密封部的外部。
7.根据权利要求3所述的半导体封装件,所述半导体封装件还包括:
连接导体,穿过所述密封部将所述天线单元和所述基板电连接。
8.根据权利要求1所述的半导体封装件,其中,
所述下封装件还包括容纳所述电子器件的芯基板和设置在所述芯基板的相对的表面上的再布线层,并且
所述接地部设置在所述芯基板的上表面上设置的所述再布线层上。
9.根据权利要求8所述的半导体封装件,所述半导体封装件还包括:
连接导体,穿过所述支撑部将所述辐射部和所述下封装件电连接。
10.根据权利要求1所述的半导体封装件,其中,
所述辐射部包括:
金属层,设置在所述支撑部上;以及
镀覆层,设置在所述金属层上。
11.根据权利要求1所述的半导体封装件,其中,所述天线单元还包括:
绝缘板,所述辐射部结合到所述绝缘板的下表面。
12.根据权利要求1所述的半导体封装件,其中,所述半导体封装件发送和接收超高频带中的无线电信号。
13.根据权利要求1所述的半导体封装件,其中,所述半导体封装件发送和接收毫米波段中的无线电信号。
14.一种半导体封装件,所述半导体封装件包括:
下封装件,包括设置在基板上的一个或更多个电子器件和密封所述电子器件的密封部;以及
天线单元,设置在所述密封部的上表面上,
其中,所述天线单元包括:接地部,设置在所述下封装件的上表面上;辐射部,设置为与所述接地部分开;以及连接部,设置在所述密封部的侧表面上,并且将所述天线单元和所述基板电连接。
15.一种制造半导体封装件的方法,所述方法包括:
制备下封装件;以及
在所述下封装件的上表面上形成天线单元,
其中,形成所述天线单元的步骤包括:在所述下封装件的上表面上形成接地部;以及在所述接地部上堆叠支撑部和辐射部,
其中,位于所述辐射部与所述接地部之间的至少一部分是空的空间。
16.根据权利要求15所述的方法,所述方法还包括:
将所述天线单元和所述下封装件的基板电连接。
17.根据权利要求16所述的方法,其中,
将所述天线单元和所述下封装件的所述基板电连接的步骤包括:
部分地切割所述下封装件以暴露设置在所述下封装件中的垫;
沿着所述下封装件的切割表面将所述天线单元和所述垫电连接;以及
完全地切割所述下封装件。
18.根据权利要求16所述的方法,其中,
将所述天线单元和所述下封装件的所述基板电连接的步骤包括:
在所述下封装件中形成通孔以暴露设置在所述下封装件中的垫;以及
用导电材料填充所述通孔以将所述垫和所述天线单元电连接。
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CN111540689A (zh) * | 2020-03-26 | 2020-08-14 | 甬矽电子(宁波)股份有限公司 | Ic射频天线结构、制作方法和半导体器件 |
CN112310041A (zh) * | 2019-07-29 | 2021-02-02 | 群创光电股份有限公司 | 电子装置及其制造方法 |
CN113782496A (zh) * | 2020-06-10 | 2021-12-10 | 讯芯电子科技(中山)有限公司 | 半导体封装装置和半导体封装装置制造方法 |
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KR20190018812A (ko) | 2017-08-16 | 2019-02-26 | 삼성전기주식회사 | 반도체 패키지와 이를 구비하는 전자 기기 |
US11139551B2 (en) * | 2018-09-18 | 2021-10-05 | Samsung Electro-Mechanics Co., Ltd. | Chip antenna module |
KR102482195B1 (ko) * | 2018-10-26 | 2022-12-27 | 삼성전기주식회사 | 칩 안테나 모듈 |
US11462460B2 (en) * | 2019-06-06 | 2022-10-04 | The Boeing Company | Electrical module assembly with embedded dies |
JP7540580B2 (ja) | 2021-03-05 | 2024-08-27 | 株式会社村田製作所 | アンテナ装置、及び、アンテナユニット |
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US10483618B2 (en) | 2019-11-19 |
US20190131689A1 (en) | 2019-05-02 |
CN109755226B (zh) | 2023-03-14 |
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