CN109728082B - 功率半导体器件及其制造方法 - Google Patents

功率半导体器件及其制造方法 Download PDF

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CN109728082B
CN109728082B CN201811259649.XA CN201811259649A CN109728082B CN 109728082 B CN109728082 B CN 109728082B CN 201811259649 A CN201811259649 A CN 201811259649A CN 109728082 B CN109728082 B CN 109728082B
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impurity
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epitaxial layer
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CN109728082A (zh
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李珠焕
禹赫
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Hyundai Mobis Co Ltd
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Abstract

本发明涉及功率半导体器件及其制造方法。该器件包括：外延层，其构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；场截止区，其位于外延层下方且以第二浓度掺杂有第一导电类型的杂质，该第一导电类型的杂质随后被激活；以及集电极区，其位于场截止区下方并且掺杂有第二导电类型的杂质。该场截止区通过重复交替地布置其中第一导电类型的杂质的激活相对较强的区域和其中第一导电类型的杂质的激活相对较弱的区域来形成。

Description

功率半导体器件及其制造方法
相关申请的交叉引证
本申请要求于2017年10月30日向韩国知识产权局提交的韩国专利申请号10-2017-0142732的优先权和权益，其全部内容通过引证并入本文。
技术领域
本发明涉及一种功率半导体器件及其制造方法，更具体地涉及一种绝缘栅双极型晶体管(IGBT)器件及其制造方法。
背景技术
通过金属氧化物半导体(MOS)技术和双极物理学的功能整合来开发绝缘栅双极型晶体管(IGBT)。其特征在于其低饱和电压和快速开关能力。其应用扩展到用晶闸管、双极型晶体管、MOSFET等不能实现的应用。其也是必需在广泛用于300V或更高的电压范围中的高效率、高速电力系统中使用的下一代功率半导体器件。由于二十世纪七十年代的功率MOSFET的发展，MOSFET已经被用作需要快速开关能力的领域中的开关器件，而双极型晶体管、晶闸管、GTO等已经用于其中在中压到高压下需要高的导电电流的领域。在二十世纪八十年代早期开发的IGBT在输出特性方面具有比双极型晶体管更好的电流能力，并且在输入特性方面具有类似于MOSFET的栅极驱动特性，并且因此，其能够以约100kHz的高速进行开关。因此，IGBT正在广泛的应用中使用，从工业到家庭用电子产品，因为其不仅用于代替MOSFET、双极型晶体管和晶闸管的器件，而且还用于创建新的应用系统。
相关的现有技术是韩国公布号20140057630(2014年5月13日公布，名称为“IGBTand manufacturing method thereof”)。
发明内容
本发明的目的是提供一种能够改善效率和稳健性两者的功率半导体器件及其制造方法。然而，这些问题是说明性的，因此本发明的范围不限于此。
提供了根据本发明的一方面的用于解决上述问题的功率半导体器件。该功率半导体器件包括外延层，该外延层构成有源单元(active cell)区的一部分并且以第一浓度掺杂有第一导电类型的杂质；场截止区，位于外延层下方且以第二浓度掺杂有第一导电类型的杂质，该杂质随后被激活；以及集电极区，其位于场截止区下方并且掺杂有第二导电类型的杂质，其中场截止区通过重复交替地布置其中第一导电类型的杂质的激活相对较强的区域和其中第一导电类型的杂质的激活相对较弱的区域而形成。
当功率半导体器件切换至导通时，穿过场截止区的其中激活相对较弱的区域的空穴电流大于穿过场截止区的其中激活相对较强的区域的空穴电流，并且当功率半导体器件切换至截止时，通过场截止区的其中激活相对较强的区域的电流大于通过场截止区的其中激活相对较弱的区域的电流。
在功率半导体器件中，场截止区中的第一导电类型的杂质的第二浓度可以高于外延层中的第一导电类型的杂质的第一浓度。
在功率半导体器件中，第一导电类型和第二导电类型可以有相反的导电类型并且可以各自是p型和n型中的一种。
提供了根据本发明的另一方面的用于解决上述问题的用于制造功率半导体器件的方法。该方法包括：在半导体晶片上形成外延层，该外延层构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；在外延层上形成栅极结构；去除半导体晶片的边缘之外的半导体晶片；通过用第一导电类型的杂质以第二浓度掺杂外延层的下部并通过使用第一激光退火处理激活杂质来形成场截止区；并且通过用第二导电类型的杂质掺杂外延层的在场截止区以下的下部的区域，并且通过使用第二激光退火处理激活杂质来形成集电极区，其中执行第一退火处理，使得其中第一导电类型的和第二浓度的杂质的激活相对较强的区域和其中第一导电类型的和第二浓度的杂质的激活相对较弱的区域重复交替布置。
提供了根据本发明的又一方面的用于解决上述问题的用于制造功率半导体器件的方法。该方法包括：在半导体晶片上形成外延层，该外延层构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；在外延层上形成栅极结构；去除半导体晶片的边缘之外的半导体晶片；通过用第二导电类型的杂质掺杂外延层的下部并使用第二激光退火处理激活杂质来形成集电极区；以及通过使用第一导电类型的杂质以第二浓度掺杂外延层的下部中的集电极区并通过使用第一激光退火处理激活杂质来形成场截止区，其中进行第一退火处理，使得其中第一导电类型和第二浓度的杂质的激活相对较强的区域和其中第一导电类型和第二浓度的杂质的激活相对较弱的区域重复交替布置。
在制造功率半导体器件的方法中，可以以如下方式进行第一激光退火处理：将激光能量和退火时间中的至少一种有区别地施加到其中第一导电类型的杂质的激活相对强的区域和其中第一导电类型的杂质的激活相对弱的区域，使得其中第一导电类型的杂质的激活相对较强的区域和其中第一导电类型的杂质的激活相对较弱的区域重复交替地布置在场截止区中。
在制造功率半导体器件的方法中，去除半导体晶片的边缘之外的半导体晶片可以包括使用Tyco法研磨处理去除的步骤。
根据如上所述的本发明的实施方式，可以实现功率半导体器件及其制造方法，其能够提高效率和稳健性两者。当然，本发明的范围不受这些影响的限制。
附图说明
图1示出了现有技术的常规功率半导体器件的一部分有源单元区。
图2示出了说明现有技术的取决于图1的区域A中的场截止区域的厚度的浓度分布、效率和稳健性的表格。
图3是示出现有技术的常规功率半导体器件中的效率和稳健性之间的关系的曲线图。
图4A和图4B示出了根据本发明的实施方式的功率半导体器件的效率和稳健性。
图5是根据本发明的实施方式的功率半导体器件中的有源单元区的截面图。
图6A至图6C以及图7A至图7D分别示出根据本发明的实施方式的制造功率半导体器件的处理的各部分。
图8A和图8B示出了由于根据离子注入处理和随后的退火处理的激活而引起的晶格变化。
图9示出了总结根据本发明的实施方式和比较例的功率半导体器件中的缓冲层结构、杂质浓度分布、效率和稳健性的表格。
<参考标记的说明>
10：外延层
70：作为缓冲层的场截止区
70：其中第一导电类型的杂质的激活相对较强的区域
70b：其中第一导电类型的杂质的激活相对较弱的区域
71：集电极区
具体实施方式
在下文中，将参考附图详细描述本发明的实施方式。然而，应当理解，本发明不限于下面描述的实施方式，而是可以以各种其他形式来体现。以下实施方式旨在给出对本公开的更完整的描述，并且为了将本公开的范围完全传达给本领域技术人员而提供。而且，为了便于说明，可以放大或缩小至少一些部件的尺寸。在所有附图中，相同的附图标记指代相同的元件。
在本说明书中，第一导电类型和第二导电类型可以是相反的导电类型，并且可以分别是n型和p型中的一种。例如，第一导电类型可以是n型，第二导电类型可以是p型，并且这些导电类型说明性地在附图中表示。然而，本发明的技术思想不限于此。例如，第一导电类型可以是p型，第二导电类型可以是n型。
图1示出了常规功率半导体器件的一部分有源单元区。图2示出了说明取决于图1的区域A1中的场截止区的厚度的浓度分布、效率和稳健性的表格，图3是示出常规功率半导体器件的效率和稳健性之间的关系的曲线图。
参照图1至图3，功率半导体器件包括：外延层10，其构成有源单元区(active cellregion)的一部分并且以第一浓度掺杂有第一导电类型的杂质；场截止区70，位于外延层10下方并且以第二浓度掺杂有第一导电类型的杂质，该杂质然后被激活；以及集电极区71，其位于场截止区70下方并且掺杂有第二导电类型的杂质。此处，场截止区70可以被理解为缓冲层。
如果场截止区70的厚度相对较小，那么在切换至导通期间来自空穴的向上电流相对较高，因此开关速度(效率)较好。然而，存在在切换至截止期间来自电子的向下OFF电流相对较低并且因此稳健性较差的问题。
同时，如果场截止区70的厚度相对较大，则在切换至截止期间来自电子的向下OFF电流相对较高，因此稳健性较好。然而，存在在切换至导通期间来自空穴的向上电流相对较低且因此开关速度(效率)较差的问题。
因此，功率半导体器件通常在效率和稳健性之间具有折衷。
图4A和图4B示出了根据本发明的实施方式的功率半导体器件中的效率和稳健性。
根据本发明的实施方式的功率半导体器件包括：外延层10，其构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；以及场截止区70，位于外延层10下方并且以第二浓度掺杂有第一导电类型的杂质，该杂质然后被激活。
通过重复交替地布置其中第一导电类型的杂质的激活相对较强的区域70a和其中第一导电类型的杂质的激活相对较弱的区域70b来形成场截止区70。例如，区域70a和70b可以交替布置，同时在平行于外延层10的上表面的方向上彼此连接。在其它方面，沿着功率半导体器件的深度方向(图中的垂直方向)，其中第一导电类型的杂质的激活相对较强的区域70a可以比其中第一导电类型的杂质的激活相对较弱的区域70b长。
参考图4A，当根据本发明的实施方式的功率半导体器件切换至导通时，穿过场截止区的其中激活相对较弱的区域70b的空穴电流大于穿过场截止区70的其中激活相对较强的区域70a的空穴电流，从而通过低激活区域确保效率增加。
参考图4B，当根据本发明的实施方式的功率半导体器件切换至截止时，穿过场截止区70的其中激活相对较强的区域70a的电子电流大于穿过其中激活相对较弱的区域70b的电子电流，因此OFF电流有效地流过高激活区域并且因此确保稳健性。
因此，根据本发明的实施方式的功率半导体器件具有可以利用场截止区70通过重复交替地布置其中第一导电类型的杂质的激活相对较强的区域70a和其中第一导电类型的杂质的激活相对弱的区域70b而形成来同时确保效率和稳健性的有利效果。
图5是根据本发明的实施方式的功率半导体器件中的有源单元区的截面图。
参考图5，根据本发明的实施方式的功率半导体器件100包括：外延层10，外延层10构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；场截止区70，位于外延层10下方并且以第二浓度掺杂有第一导电类型的杂质，该杂质然后被激活；以及集电极区71，其位于场截止区70下方并且掺杂有第二导电类型的杂质。场截止区70通过反复交替地布置其中第一导电类型的杂质的激活相对较强的区域和其中第一导电类型的杂质的激活相对较弱的区域而形成。
外延层10作为衬底可以被理解为包括外延生长在半导体晶片上的外延层。半导体晶片可以包括例如轻掺杂有第一导电类型的杂质的半导体晶片。半导体晶片中的n型杂质的掺杂浓度可以是例如约1013/cm3至约1016/cm3。考虑到n型杂质的掺杂浓度，包括外延生长的外延层的衬底10可以称为N衬底。然而，衬底10的材料和掺杂浓度不限于此，而是可以变化。有源单元区包括其中设置有多个有源单元并且在垂直方向上发生电流传导的区域。
场截止区70设置为外延层10的与上表面相对的下表面上的缓冲层。场截止区70可以是掺杂有第一导电类型的杂质的区域。例如，场截止区70中的n型杂质浓度可以是约1014/cm3到1018/cm3。考虑场截止区70中的n型杂质浓度，场截止区70可以被称为N0层。场截止区70中的n型杂质浓度可以高于包括外延生长的外延层的衬底10中的n型杂质浓度。集电区域71可以设置在场截止区70的下方。集电极区71可以是掺杂有第二导电类型的杂质的区域，例如p型杂质。同时，可在集电极区70下方进一步提供第二金属膜76。第二金属膜76可以设置为集电极。
此外，下面将描述构成根据本发明的实施方式的功率半导体器件100的说明性元件。然而，应当理解，这些说明性元件并不被提供来限制本发明的技术思想，而是被提供作为对理解功率半导体器件的配置的解释。
根据本发明的实施方式的功率半导体器件100包括：分别设置在第一沟槽20a和第二沟槽20b中的一对栅电极50a和50b，第一沟槽20a和第二沟槽20b在外延层10中彼此间隔开。此处，外延层10可以理解为包括外延生长在晶片上的外延层。
根据本发明的实施方式的功率半导体器件100包括具有第二导电类型的本体区域42和具有第一导电类型的一对源极区域44a和44b，本体区域42设置在第一沟槽20a和第二沟槽20b之间，源极区域44a和44b在主体区域42中彼此间隔开并且分别邻近第一沟槽20a和第二沟槽20b设置。
根据本发明的实施方式的功率半导体器件100包括：围绕第一沟槽20a的底表面和至少一个侧表面的具有第二导电类型的浮动区域(floating region)30a以及围绕第二沟槽20b的底表面和至少一个侧表面的具有第二导电类型的浮动区域30b。具有第二导电类型的一对浮动区域30a和30b可彼此间隔开。相对于作为衬底的外延层10的顶表面1s，到浮动区域30a和30b的底表面的深度大于到第一沟槽20a和第二沟槽20b的底表面的深度。也就是说，具有第二导电类型的浮动区域30a和30b的最大掺杂深度可以大于第一沟槽20a和第二沟槽20b的深度。
根据本发明的实施方式的功率半导体器件100包括具有第一导电类型的漂移区，其从具有第二导电类型的一对浮动区域30a和30b下方穿过在具有第二导电类型的该对浮动区域30a和30b之间的区域14延伸至第二导电类型的本体区域42。
同时，具有第二导电类型的本体区42的最大掺杂深度小于第一沟槽20a和第二沟槽20b的深度，并且具有第二导电类型的浮动区域30a和30b的最大掺杂深度可以大于第一沟槽20a和第二沟槽20b的深度。
电连接到栅电极50a和50b的导电图案64和电连接到源极区44a和44b和本体区42的导电图案68设置在衬底上。导电图案64和68用作电极或触点，并且可以与介于其间的绝缘图案62和66电绝缘。同时，集电极76可以设置在衬底下面。
在下文中，将描述根据本发明的实施方式的制造功率半导体器件的方法。
图6A至图6C以及图7A至图7D分别示出根据本发明的实施方式的制造功率半导体器件的处理的部分。图6A所示的功率半导体器件对应于施加激光退火处理之前的状态，并且图7A中所示的功率半导体器件对应于施加激光退火处理之后的状态。
图7B是示出沿图7A所示的功率半导体器件中的线A-A截取的截面中的掺杂浓度分布的曲线图，图7C是示出沿图7A中所示的功率半导体器件中的线B-B截取的截面中的掺杂浓度分布的曲线图，并且图7D是示出图7A中所示的功率半导体器件中的电场分布的曲线图。
根据本发明的一个方面，制造功率半导体器件的方法包括：在半导体晶片200上形成外延层，其构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；在外延层上形成栅极结构；去除半导体晶片的边缘250之外的半导体晶片200；通过用第一导电类型的杂质以第二浓度掺杂外延层的下部并使用第一激光退火处理激活杂质来形成场截止区；以及通过用第二导电类型的杂质掺杂外延层的在场截止区下方的下部的区域并且通过使用第二激光退火处理激活杂质来形成集电极区。同时，进行第一退火处理，使得其中第一导电类型和第二浓度的杂质的激活相对较强的区域和其中第一导电类型和第二浓度的杂质的激活相对较弱的区域重复交替布置。此处，在集电极区之前形成场截止区。
根据本发明的另一方面，制造功率半导体器件的方法包括：在半导体晶片200上形成外延层，外延层构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；在外延层上形成栅极结构；去除半导体晶片的边缘250之外的半导体晶片200；通过用第二导电类型的杂质掺杂外延层的下部并使用第二激光退火处理激活杂质来形成集电极区；以及通过用第一导电类型的杂质以第二浓度掺杂外延层的下部中的集电极区并且通过使用第一激光退火处理激活杂质来形成场截止区。同时，进行第一退火处理，使得其中第一导电类型和第二浓度的杂质的激活相对较强的区域和其中第一导电类型和第二浓度的杂质的激活相对较弱的区域重复交替布置。此处，集电极区在场截止区之前形成。
此处，半导体晶片200可以包括例如轻掺杂有第一导电类型的杂质的半导体晶片。半导体晶片中的n型杂质的掺杂浓度可以是例如约1013/cm3至约1016/cm3。考虑到n型杂质的掺杂浓度，包括外延生长的外延层的衬底可以称为N衬底。
半导体晶片200的厚度相对较厚，因此通过用杂质穿过半导体晶片200的后表面掺杂外延层的下表面然后激活杂质而形成场截止区和集电极区是低效的。因此，在形成场截止区和集电极区之前，需要减小半导体晶片200的后表面的至少一部分的厚度。这种去除处理可以包括使用蚀刻方法或研磨方法的减薄处理。然而，如果在半导体晶片200的整个区域上应用减薄处理，则可能出现发生弯曲并且后续处理的处理不容易的问题。因此，除了预定厚度或更多的边缘250之外，去除半导体晶片200的中心部分使得外延层被暴露是有利的。例如，去除半导体晶片的边缘之外的部分的步骤可以包括使用Tyco法研磨处理(Tycoprocess grinding process)去除的步骤。
在这种结构下，区分伴随着光刻处理的杂质掺杂浓度，并且因此对于用于区分外延层的下表面上的场截止区中的杂质激活程度的方法而言在实际上是不容易的。
因此，注入以形成场截止区的杂质的掺杂浓度在有源单元区上相等地施加，并且作为退火处理而在图6C中所示的激光退火处理，作为对注入杂质的初始场截止区70c的退火处理，在第一区域70a和第二区域70b中有差别地执行，从而形成场截止区70。所产生的场截止区70以如下方式形成：其中掺杂杂质的激活相对较强的区域70a和其中掺杂杂质的激活相对较弱的区域70b被重复交替地布置。可以执行区别激光退火处理的方法，使得激光能量和退火时间中的至少一个被差别地施加到第一区域70a和第二区域70b。
例如，可以对低激活区域，即功率半导体器件的场截止区70中的第二区域70b进行激光退火处理，使得与高激活区域，即功率半导体器件的场截止区70中的第一区域70a的相比，激光能量和退火时间中的至少一个相对小或短。
图8A和图8B示出了由于根据离子注入处理和随后的退火处理的激活而引起的晶格变化。
参照图8A和图8B，可以看出，由●表示的掺杂剂离子被注入的同时晶格断裂，并且通过激光退火处理恢复破裂的晶格并且激活载流子掺杂剂离子。
以上已经参照实施方式和比较例描述了本发明的技术思想。
图9示出了总结根据本发明的实施方式和比较例的功率半导体器件中的缓冲层结构、杂质浓度分布、效率和稳健性的表格。
参考图9，功率半导体器件包括：外延层10，其构成有源单元区的一部分并且掺杂有第一浓度的第一导电类型的杂质；场截止区70，位于外延层10下方并且以第二浓度掺杂有第一导电类型的杂质，该杂质然后被激活；以及集电极区71，其位于场截止区70下方并且掺杂有第二导电类型的杂质。这里，场截止区70可以被理解为缓冲层。
对于比较例1，如果场截止区70的厚度相对较小，则在切换至导通期间来自空穴的向上电流相对较高，因此开关速度(效率)是较好的。然而，存在在切换至截止期间来自电子的向下OFF电流相对较低并且因此稳健性较差的问题。
对于比较例2，如果场截止区70的厚度相对较大，则在切换至截止期间来自电子向下OFF电流相对较高，因此稳健性较好。然而，存在在切换至导通期间来自空穴的向上电流相对较低且因此开关速度(效率)较差的问题。
另一方面，在本发明的实施方式中，场截止区70具有交替布置的强区和弱区的结构。即，其中第一导电类型的掺杂杂质的激活相对较强的区域和其中第一导电类型的掺杂杂质的激活相对较弱的区域被重复交替地布置。确认的是，在此结构中，在切换至截止期间电子的向下OFF电流相对较高，且因此稳健性良好，且在切换至导通期间空穴的向上电流相对较高，且因此开关速度(效率)良好。
虽然已经参照实施方式描述了本发明，但是应当理解，本发明不限于所公开的实施方式，相反，本发明旨在覆盖包括在所附权利要求的精神和范围内的各种修改和等同布置。因此，本发明的真实范围应由所附权利要求的技术思想确定。

Claims (8)

1.一种功率半导体器件，包括：
外延层，构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；
场截止区，位于所述外延层下方并且以第二浓度掺杂有所述第一导电类型的杂质，所述第二浓度的所述第一导电类型的杂质随后被激活；以及
集电极区，位于所述场截止区下方并且掺杂有第二导电类型的杂质，
其中，所述场截止区通过重复交替地布置所述第一导电类型的杂质的激活相对较强的第一区域和所述第一导电类型的杂质的激活相对较弱的第二区域来形成，以及
其中，所述第一区域的厚度大于所述第二区域的厚度。
2.根据权利要求1所述的功率半导体器件，
其中，当所述功率半导体器件切换至导通时，穿过所述场截止区的激活相对较弱的区域的空穴电流大于穿过所述场截止区的激活相对较强的区域的空穴电流，并且
其中，当所述功率半导体器件切换至截止时，穿过所述场截止区的激活相对较强的区域的电流大于穿过所述场截止区的激活相对较弱的区域的电流。
3.根据权利要求1所述的功率半导体器件，
其中，所述场截止区中的所述第一导电类型的杂质的所述第二浓度高于所述外延层中的所述第一导电类型的杂质的所述第一浓度。
4.根据权利要求1所述的功率半导体器件，
其中，所述第一导电类型和所述第二导电类型是相反的导电类型并且各自是p型和n型中的一种。
5.一种用于制造功率半导体器件的方法，所述方法包括：
在半导体晶片上形成外延层，所述外延层构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；
在所述外延层上形成栅极结构；
去除所述半导体晶片的边缘之外的所述半导体晶片；
通过用第一导电类型的杂质以第二浓度掺杂所述外延层的下部并通过使用第一激光退火处理激活所述第二浓度的杂质来形成场截止区；以及
通过用第二导电类型的杂质掺杂所述外延层的下部的在所述场截止区下方的区域并通过使用第二激光退火处理激活所述第二导电类型的杂质来形成集电极区，
其中，执行所述第一激光退火处理，使得所述第一导电类型的所述第二浓度的杂质的激活相对较强的第一区域与所述第一导电类型的所述第二浓度的杂质的激活相对较弱的第二区域重复交替布置，以及
其中，所述第一区域的厚度大于所述第二区域的厚度。
6.一种用于制造功率半导体器件的方法，所述方法包括：
在半导体晶片上形成外延层，所述外延层构成有源单元区的一部分并且以第一浓度掺杂有第一导电类型的杂质；
在所述外延层上形成栅极结构；
去除所述半导体晶片的边缘之外的所述半导体晶片；
通过用第二导电类型的杂质掺杂所述外延层的下部并通过使用第二激光退火处理激活所述第二导电类型的杂质来形成集电极区；以及
通过用第一导电类型的杂质以第二浓度掺杂所述外延层的下部中的所述集电极区并通过使用第一激光退火处理激活所述第二浓度的杂质来形成场截止区，
其中，执行所述第一激光退火处理，使得所述第一导电类型的所述第二浓度的杂质的激活相对较强的第一区域与所述第一导电类型的所述第二浓度的杂质的激活相对较弱的第二区域重复交替布置，以及
其中，所述第一区域的厚度大于所述第二区域的厚度。
7.根据权利要求5或6所述的方法，
其中，以如下方式执行所述第一激光退火处理：将激光能量和退火时间中的至少一个有区别地应用到所述第一导电类型的杂质的激活相对较强的区域和所述第一导电类型的杂质的激活相对较弱的区域，使得所述第一导电类型的杂质的激活相对较强的区域和所述第一导电类型的杂质的激活相对较弱的区域重复交替布置在所述场截止区中。
8.根据权利要求5或6中任一项的所述的方法，
其中，去除所述半导体晶片的边缘之外的所述半导体晶片包括：使用Tyco法研磨处理进行去除的步骤。
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