CN109727848B - Manufacturing method of three-dimensional memory - Google Patents
Manufacturing method of three-dimensional memory Download PDFInfo
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- CN109727848B CN109727848B CN201811634603.1A CN201811634603A CN109727848B CN 109727848 B CN109727848 B CN 109727848B CN 201811634603 A CN201811634603 A CN 201811634603A CN 109727848 B CN109727848 B CN 109727848B
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The invention discloses a manufacturing method of a three-dimensional memory. The manufacturing method of the three-dimensional memory comprises the following steps: providing a first wafer, wherein an array layer of a three-dimensional memory is formed on the first wafer; providing a second wafer, wherein a peripheral device layer of the three-dimensional memory is formed on the second wafer; providing a bonding layer, wherein a first interconnection layer for interconnecting the back-stage metal of the array layer is formed in the bonding layer; bonding the first wafer, the second wafer and the bonding layer to enable the bonding layer to connect the array layer and the peripheral device layer in the height direction of the three-dimensional memory; the first bonding surface of the bonding layer is bonded with the array layer, the second bonding surface of the bonding layer is bonded with the peripheral device layer, and the array layer is electrically connected with the peripheral device layer through the bonding layer. The invention can solve the defects of long manufacturing period and low modularization degree in the prior art.
Description
Technical Field
The present invention relates to a method for manufacturing a memory, and more particularly, to a method for manufacturing a three-dimensional memory.
Background
With the continued emphasis on highly integrated electronic devices, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower powers and have increased device densities. To achieve this, devices with smaller dimensions and multi-layer devices with transistor cells arranged in horizontal and vertical arrays have been developed. The three-dimensional memory is an emerging flash memory type developed in the industry, the limitation caused by a two-dimensional or planar flash memory is solved by vertically stacking a plurality of layers of data storage units, the three-dimensional memory has excellent precision, higher storage capacity can be accommodated in a smaller space, storage equipment with the storage capacity being several times higher than that of the similar flash memory technology can be manufactured, the cost and the energy consumption are further effectively reduced, and the requirements of numerous consumer mobile equipment and the enterprise deployment with the severest requirements can be comprehensively met.
As shown in fig. 1A-1B, the conventional method for manufacturing a three-dimensional memory mainly includes:
(1) forming an array layer with bit line/word line contacts on a first wafer;
(2) forming a CMOS peripheral device on the second wafer;
(3) and mixing and bonding the array wafer and the CMOS wafer together.
The existing manufacturing method of the three-dimensional memory has the following defects:
1. the cycle time is long: the processing time to form the array wafer is much longer than the processing time to form the CMOS wafer, resulting in an overall cycle time to fabricate the three-dimensional memory that is too long.
2. The modularization degree is low: the array wafer forming process and the CMOS wafer forming process are highly interfered with each other, and modular production is difficult to carry out.
Therefore, there is a need in the art for a three-dimensional memory and a method for fabricating the same to overcome the above-mentioned drawbacks of the prior art.
Disclosure of Invention
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
In order to solve the above-mentioned defects of the prior art, the present invention provides a three-dimensional memory and a method for manufacturing the three-dimensional memory, so as to shorten the manufacturing period of the three-dimensional memory and improve the adaptability of the three-dimensional memory by improving the modularization degree.
The three-dimensional memory provided by the invention comprises: the array layer, the peripheral device layer and the bonding layer;
a first interconnection layer for interconnecting a back-end metal of the array layer is formed in the adhesive layer, and the adhesive layer connects the array layer and the peripheral device layer in the height direction of the three-dimensional memory; wherein the first bonding surface of the bonding layer is bonded to the array layer, the second bonding surface of the bonding layer is bonded to the peripheral device layer, and the array layer and the peripheral device layer are electrically connected through the bonding layer.
Preferably, in the three-dimensional memory provided in the present invention, the first interconnect layer may include: a bit line of the array layer and a bit line contact electrically connecting the bit line and the array layer, the bit line contact being exposed at the first bonding surface.
Preferably, in the three-dimensional memory provided by the present invention, the array layer may include: a graded layer stack, a channel hole penetrating the graded layer stack along the height direction, a channel layer located in the channel hole, and a drain contacting the channel layer, the drain being electrically connected to the bit line contact.
Optionally, in the three-dimensional memory provided in the present invention, the first interconnect layer may also include: a common source contact electrically connected to a common source line in the array layer and a wordline contact electrically connected to a wordline contact structure in the array layer, the common source contact and the wordline contact exposed to the first bonding surface.
Preferably, in the three-dimensional memory provided by the present invention, the array layer may include a hierarchical layer stack, a gate slit, a common source line, and a word line contact structure;
the gate slit penetrates through the hierarchical layer stack in the height direction, and the common source line is formed in the gate slit;
the word line contact structure partially penetrates through the hierarchical layer stack along the height direction to lead out the gate layer in the hierarchical layer stack.
Optionally, in the three-dimensional memory provided by the present invention, the adhesive layer may further include a first metal via, the first metal via electrically connects the first interconnect layer and the peripheral device layer, and the first metal via is exposed to the second adhesive surface.
Preferably, in the three-dimensional memory provided by the present invention, the peripheral device layer may include: a peripheral device and a second interconnect layer interconnecting back-end metals of the peripheral device, wherein the second interconnect layer may include: a second metal via electrically connected to the first metal via.
According to another aspect of the present invention, the present invention also provides a method for manufacturing a three-dimensional memory.
The manufacturing method of the three-dimensional memory provided by the invention comprises the following steps:
providing a first wafer, wherein an array layer of the three-dimensional memory is formed on the first wafer;
providing a second wafer, wherein a peripheral device layer of the three-dimensional memory is formed on the second wafer;
providing a bonding layer, wherein a first interconnection layer for interconnecting the back-stage metal of the array layer is formed in the bonding layer;
bonding the first wafer, the second wafer and the adhesive layer such that the adhesive layer connects the array layer and the peripheral device layer in a height direction of the three-dimensional memory; wherein the first bonding surface of the bonding layer is bonded to the array layer, the second bonding surface of the bonding layer is bonded to the peripheral device layer, and the array layer and the peripheral device layer are electrically connected through the bonding layer.
Preferably, in the method for manufacturing the three-dimensional memory provided by the present invention, providing the adhesive layer may further include:
providing a third substrate;
forming a first metal via hole in the adhesive layer and the first interconnection layer in this order on the upper surface of the third substrate, the surface of the first interconnection layer being the first adhesive surface;
bonding the first wafer, the second wafer, and the bonding layer may further include:
bonding the array layer of the first wafer to the first bonding surface;
peeling the third substrate to expose the second bonding surface of the bonding layer, the first metal via hole being exposed to the second bonding surface;
bonding the peripheral device layer of the second wafer to the second bonding surface.
Optionally, in the method for manufacturing the three-dimensional memory provided in the present invention, providing the adhesive layer may further include:
providing a third substrate;
sequentially forming the first interconnect layer and a first metal via in the adhesive layer on the upper surface of the third substrate, the first metal via being exposed to the second adhesive surface;
bonding the first wafer, the second wafer, and the bonding layer may further include:
bonding the peripheral device layer of the second wafer to the second bonding surface;
peeling the third substrate to expose the first bonding surface of the bonding layer, the first bonding surface being a surface of the first interconnection layer;
bonding the array layer of the first wafer to the first bonding surface.
Preferably, in the method for manufacturing the three-dimensional memory provided by the present invention, the providing a third substrate may further include:
forming a first dielectric layer on the upper part of the third substrate, wherein the bonding layer is formed on the upper surface of the first dielectric layer;
the peeling of the third substrate may further include:
and cutting the third substrate by taking the interface of the first medium layer in the third substrate as a cutting interface, and removing the first medium layer to expose the first bonding surface or the second bonding surface of the bonding layer.
Preferably, in the method for manufacturing the three-dimensional memory according to the present invention, the forming a first dielectric layer on the third substrate may further include:
and performing hydrogen injection treatment on the surface of the third substrate to form a hydrogen injection layer, wherein the first dielectric layer is the hydrogen injection layer.
Optionally, in the method for manufacturing a three-dimensional memory according to the present invention, the forming a first dielectric layer on the third substrate may further include:
and performing porous oxidation treatment on the surface of the third substrate to form a porous silicon oxide layer, wherein the first dielectric layer is the porous silicon oxide layer.
Based on the above description, the three-dimensional memory and the manufacturing method thereof provided by the present invention can separate the bonding layer from the array wafer and the CMOS wafer, and have the following advantages:
(1) by forming the bonding layer and the array layer separately, the processing time for forming the array wafer can be effectively shortened, thereby shortening the manufacturing time of the whole three-dimensional memory.
(2) By forming the bonding layer and the array layer respectively, the degree of cross interference between the array wafer forming process and the CMOS wafer forming process can be effectively reduced, and the adaptability is improved. If the process or structure of the array wafer or the CMOS wafer is changed, only the bonding layer structure needs to be changed accordingly, and the process or structure of the other wafer does not need to be changed.
Drawings
The above features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.
Fig. 1A shows a schematic structure diagram of a conventional three-dimensional memory array wafer.
Fig. 1B shows a schematic structure diagram of a conventional three-dimensional memory CMOS wafer.
Fig. 2A is a schematic structural diagram of a first wafer according to an embodiment of the present invention.
Fig. 2B shows a schematic structural diagram of a second wafer according to an embodiment of the invention.
Fig. 2C is a schematic view illustrating a hydrogen implantation process performed on an upper portion of a third substrate according to an embodiment of the present invention.
Fig. 2D shows a schematic structural diagram of a third substrate with a first dielectric layer according to an embodiment of the present invention.
Fig. 2E shows a schematic structural diagram of a third substrate with an adhesive layer according to an embodiment of the present invention.
Fig. 2F shows a schematic diagram of bonding an array layer of a first wafer to a first bonding surface provided by an embodiment of the invention.
Fig. 2G shows a schematic diagram of stripping a third substrate provided by one embodiment of the invention.
Fig. 2H shows a schematic diagram of removing the first dielectric layer according to an embodiment of the present invention.
Fig. 2I shows a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention.
Fig. 3 shows a schematic structural diagram of a third substrate with an adhesive layer according to an embodiment of the present invention.
Fig. 4 is a flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention.
Fig. 5 shows a schematic flow chart for providing an adhesive layer according to an embodiment of the present invention.
Fig. 6 shows a flow chart for bonding the first wafer, the second wafer and the bonding layer according to an embodiment of the present invention.
Reference numerals:
1 array layer;
2 bit line/word line contacts;
3 CMOS transistors;
10 a first wafer;
11 an array layer;
12 a word line contact structure;
13, a gate gap;
20 a second wafer;
21 a peripheral device layer;
22 CMOS transistors;
23 a second interconnect layer;
24 a second metal via;
31 a bonding layer;
32 a first interconnect layer;
33 a third substrate;
34 a first metal via;
35 a first dielectric layer;
36 a bonding layer;
41 a first bonding surface;
42 a second bonding surface;
43 cutting the interface;
201-204 a step of manufacturing a three-dimensional memory;
2031-2032 providing an adhesive layer;
2041-2043 bonding the first wafer, the second wafer and the bonding layer.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure. While the invention will be described in connection with the preferred embodiments, there is no intent to limit its features to those embodiments. On the contrary, the invention is described in connection with the embodiments for the purpose of covering alternatives or modifications that may be extended based on the claims of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be practiced without these particulars. Moreover, some of the specific details have been left out of the description in order to avoid obscuring or obscuring the focus of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Additionally, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," "vertical" and the like as used in the following description are to be understood as referring to the segment and the associated drawings in the illustrated orientation. The relative terms are used for convenience of description only and do not imply that the described apparatus should be constructed or operated in a particular orientation and therefore should not be construed as limiting the invention.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, regions, layers and/or sections, these elements, regions, layers and/or sections should not be limited by these terms, but rather are used to distinguish one element, region, layer and/or section from another element, region, layer and/or section. Thus, a first component, region, layer or section discussed below could be termed a second component, region, layer or section without departing from some embodiments of the present invention.
In order to solve the above-mentioned defects in the prior art, the present invention provides an embodiment of a three-dimensional memory and an embodiment of a method for manufacturing a three-dimensional memory, so as to shorten a manufacturing period of the three-dimensional memory and improve the adaptability of the three-dimensional memory by improving the degree of modularization.
As shown in fig. 4, the method for manufacturing a three-dimensional memory according to this embodiment may include:
201: a first wafer 10 as shown in fig. 2A is provided, and an array layer 11 of the three-dimensional memory is formed on the first wafer 10.
The array layer 11 is mainly used for the storage function of the three-dimensional memory, and specifically may include: a graded layer stack, a common source line, a word line, a channel hole penetrating the graded layer stack in the height direction, a channel layer located in the channel hole, and a drain electrode contacting the channel layer, the drain electrode being electrically connected to the bit line contact.
In some embodiments, the array layer 11 may include one or more insulating layers. The array layer 11 may further include one or more bit line contacts in an insulating layer, and one or more conductor layers. The conductive layer is made of a conductive material, and may specifically be made of a combination of one or more of tungsten, cobalt, copper, aluminum and metal silicide, or may be made of other suitable materials. The insulating layer is made of an insulating material, and may specifically be made of a combination of one or more of silicon oxide, silicon nitride, and a high-dielectric-constant insulating material, or may be made of other suitable materials.
Optionally, in another embodiment, the array layer 11 may also include: a graded layer stack, a gate gap 13, a common source line and a word line contact structure 12. The gate slit 13 penetrates the hierarchical layer stack in the height direction, and the common source line is formed in the gate slit 13 to connect out the common source line in the substrate. The word line contact structure 12 partially penetrates the level layer stack along the height direction to lead out the gate layer in the level layer stack.
It will be understood by those skilled in the art that the array layer 11 can be formed by existing or future semiconductor manufacturing processes, which are well known to those skilled in the art and will not be described herein.
202: a second wafer 20 is provided as shown in fig. 2B, and a peripheral device layer 21 of the three-dimensional memory is formed on the second wafer 20.
The peripheral device layer 21 may include: a peripheral device 22 and a second interconnect layer 23 interconnecting the back-end metal of the peripheral device 22. The peripheral device layer 21 may be formed by a conventional or future semiconductor manufacturing process, which is well known to those skilled in the art and will not be described herein.
The peripheral device 22 may include a plurality of transistors, which may be CMOS transistors, and a logic control circuit formed by the transistors, and is mainly used to control the second wafer 20 to be turned on and off, so as to conduct current from the flash memory string to the common source contact.
The second interconnection layer 23 may be formed by an existing or future semiconductor manufacturing process, which should be known to those skilled in the art and will not be described herein. The second interconnect layer 23 may include therein: and a second metal via 24, wherein the second metal via 24 is electrically connected to the first metal via 34, so as to connect the CMOS transistor 22 in the peripheral device layer 21 to a bit line, a word line and/or a common source line of the array layer 11.
The above-described second interconnect layer 23 covers the CMOS transistors for electrical signal conduction, and includes one or more interlayer insulating layers. The second interconnect layer 23 may further include: one or more contacts in the interlayer insulating layer, and one or more interconnect conductor layers. The contact and interconnect conductor layers are made of conductive materials, which may be one or a combination of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The interlayer insulating layer is made of an insulating material, and may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride and doped silicon oxide, or other suitable materials.
203: an adhesive layer 31 is provided as shown in fig. 2E, and a first interconnection layer 32 for interconnecting the back-end metals of the array layer is formed in the adhesive layer 31.
The first interconnection layer 32 may be formed by an existing or future semiconductor manufacturing process, which should be known to those skilled in the art and will not be described herein. The first interconnect layer 32 may include: bit lines and bit line contacts of the array layer 11, which are exposed at the first bonding surface 41 and electrically connect the bit lines and the array layer 11 as shown in fig. 2I, thereby connecting the bit lines of the array layer 11 to the CMOS transistors 22 in the peripheral device layer 21.
The first interconnect layer 32 may further include: a common source contact and a word line contact. The common source contact is electrically connected to the common source line of the array layer 11, the word line contact is electrically connected to the word line contact structure 12 in the array layer 11, and the common source contact and the word line contact are exposed at the first bonding surface 41, thereby connecting the word line and the common source line of the array layer 11 to the CMOS transistor 22 in the peripheral device layer 21.
As shown in fig. 5, providing the adhesive layer 31 may further include the steps of:
2031: a third substrate 33 is provided and a hydrogen implantation process is performed on the upper portion of the third substrate 33 as shown in fig. 2C to form a first dielectric layer 35 as shown in fig. 2D.
Accordingly, the first dielectric layer 35 may be a hydrogen injection layer. The third substrate 33 may be made of a suitable material including, but not limited to, silicon germanium, or a silicon-on-insulator (SOI).
2032: the first metal via 34 and the first interconnection layer 32 in the adhesive layer 31 are sequentially formed on the upper surface of the first dielectric layer 35, and the surface of the first interconnection layer 32 is taken as a first adhesive surface 41.
It can be understood by those skilled in the art that the method for providing the adhesion layer 31 provided in the above step 2031-2032 is only a preferred solution provided in the present embodiment, and is mainly used for forming the hydrogen injection layer 35 on the upper portion of the third substrate 33 to facilitate the subsequent operation of peeling off the third substrate 33.
In other embodiments, a person skilled in the art may also perform a porous oxidation process on the upper surface of the third substrate 33 to form a porous silicon oxide layer. The porous oxidation treatment is a method of forming an electrically insulating layer on a silicon surface by using both a porous treatment and a thermal oxidation process. The method overcomes the process difficulties of the plane method, the local oxidation isolation method, the air isolation method and the like, and is characterized in that a thicker insulating layer can be formed without high-temperature or long-time heat treatment. One skilled in the art can use a porous silicon oxide layer as the first dielectric layer 35 to also achieve the purpose of facilitating the subsequent stripping operation of the third substrate 33.
204: the first wafer 10, the second wafer 20, and the adhesive layer 31 are bonded such that the adhesive layer 31 connects the array layer 11 and the peripheral device layer 21 in the height direction of the three-dimensional memory.
The bonding operation refers to a technique of bonding wafers into a whole by van der waals force, molecular force, or even atomic force under a certain condition. Those skilled in the art will be aware of specific relevant technical details, which will not be described in detail herein.
The adhesive layer 31 connects the array layer 11 and the peripheral device layer 21 in the height direction (the up-down direction shown in fig. 2I) of the three-dimensional memory, wherein the first adhesive surface 41 of the adhesive layer 31 is adhered to the array layer 11, and the second adhesive surface 42 of the adhesive layer 31 is adhered to the peripheral device layer 21. The array layer 11 and the peripheral device layer 21 are electrically connected by an adhesive layer 31.
As shown in fig. 6, bonding the first wafer 10, the second wafer 20 and the bonding layer 31 may further include the steps of:
2041: as shown in fig. 2F, the array layer 11 of the first wafer 10 is bonded to the first bonding surface 41, thereby communicating the bit lines of the array layer 11 to the first interconnect layer 32 of the bonding layer 31.
2042: as shown in fig. 2G, the third substrate 33 is cut with the interface of the first dielectric layer 35 in the third substrate 33 as a cutting interface 43; and as shown in fig. 2H, the first dielectric layer 35 is removed to expose the second bonding surface 42 of the bonding layer 31, and the first metal via 34 is exposed to the second bonding surface 42.
The cutting may be performed by a smart cut method, and the uniformity of the cut interface 43 cut by the smart cut method is much higher than that of the interface cut by the hard mask deposition/photolithography/dry or wet etching method in the prior art. The skilled person will be aware of the specific process of smart-peeling and will not be described further here.
The first dielectric layer 35 may be removed by a dry or wet etching method, or may be performed by a smart cut (smart cut) method.
2043: the peripheral device layer 21 of the second wafer 20 is bonded to the second adhesive surface 42.
As shown in fig. 2I, the first bonding surface 41 of the bonding layer 31 is bonded to the array layer 11, and the second bonding surface 42 of the bonding layer 31 is bonded to the peripheral device layer 21. The array layer 11 and the peripheral device layer 21 are electrically connected by an adhesive layer 31.
It can be understood by those skilled in the art that the method for providing the adhesion layer 31 provided in the above steps 2031-2032 and the method for bonding the first wafer 10, the second wafer 20 and the adhesion layer 31 provided in the above steps 2041-2043 are only one specific solution provided in this embodiment. In other embodiments, one skilled in the art may also employ the following steps:
providing a third substrate 33;
the first interconnect layer 32 and the first metal via 34 in the adhesive layer 36 shown in fig. 3 are sequentially formed on the upper surface of the third substrate 33, and the first metal via 34 is exposed to the second adhesive surface 42. The structure of the adhesive layer 36 provided in fig. 3 is upside down from the adhesive layer 31 provided in fig. 2E.
Accordingly, the following steps can be further adopted by those skilled in the art:
bonding the peripheral device layer 21 of the second wafer 20 to the second bonding surface 42;
peeling off the third substrate 33 to expose the first bonding surface 41 of the bonding layer 31, wherein the first bonding surface 41 is a surface of the first interconnection layer 32;
the array layer 11 of the first wafer 10 is bonded to the first bonding surface 41, thereby obtaining a three-dimensional memory identical to that provided in fig. 2I.
Therefore, the method for providing the adhesive layer 36 and the method for bonding the first wafer 10, the second wafer 20 and the adhesive layer 36 provided in the above embodiments can achieve the same effects as those of the present embodiment.
Based on the above description, the method for manufacturing the three-dimensional memory provided in this embodiment can separate the adhesive layer 31 from the array layer 11 and the peripheral device layer 21, and has the following advantages:
(1) by forming the adhesive layer 31 and the array layer 11 separately, the processing time for forming the array wafer can be effectively shortened, thereby shortening the manufacturing time of the entire three-dimensional memory.
(2) By forming the adhesive layer 31 and the array layer 11 separately, the degree of cross-interference between the array wafer forming process and the CMOS wafer forming process can be effectively reduced, thereby improving the adaptability. If the process or structure of the array wafer or the CMOS wafer is changed, only the bonding layer structure needs to be changed accordingly, and the process or structure of the other wafer does not need to be changed.
While, for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more embodiments, occur in different orders and/or concurrently with other acts from that shown and described herein or not shown and described herein, as would be understood by one skilled in the art.
According to another aspect of the present invention, there is also provided an embodiment of a three-dimensional memory.
As shown in fig. 2I, the three-dimensional memory provided in this embodiment includes: the array layer 11, the peripheral device layer 21 and the adhesive layer 31, wherein a first interconnection layer 32 interconnected with the back-end metal of the array layer 11 is formed in the adhesive layer 31.
The array layer 11 is mainly used for the storage function of the three-dimensional memory, and specifically may include: a graded layer stack, a common source line, a word line, a channel hole penetrating the graded layer stack in the height direction, a channel layer located in the channel hole, and a drain electrode contacting the channel layer, the drain electrode being electrically connected to the bit line contact.
In some embodiments, the array layer 11 may include one or more insulating layers. The array layer 11 may further include one or more bit line contacts in an insulating layer, and one or more conductor layers. The conductive layer is made of a conductive material, and may specifically be made of a combination of one or more of tungsten, cobalt, copper, aluminum and metal silicide, or may be made of other suitable materials. The insulating layer is made of an insulating material, and may specifically be made of a combination of one or more of silicon oxide, silicon nitride, and a high-dielectric-constant insulating material, or may be made of other suitable materials.
The peripheral device layer 21 may include: a peripheral device 22 and a second interconnect layer 23 interconnecting the back-end metal of the peripheral device 22.
The peripheral device 22 may include a plurality of transistors, which may be CMOS transistors, and a logic control circuit formed by the transistors, and is mainly used to control the second wafer 20 to be turned on and off, so as to conduct current from the flash memory string to the common source contact.
The second interconnect layer 23 may be formed by existing or future technology semiconductor manufacturing processes, which may include: and a second metal via 24, wherein the second metal via 24 is electrically connected to the first metal via 34, so as to connect the CMOS transistor 22 in the peripheral device layer 21 to a bit line, a word line and/or a common source line of the array layer 11.
The above-described second interconnect layer 23 covers the CMOS transistors for electrical signal conduction, and includes one or more interlayer insulating layers. The second interconnect layer 23 may further include: one or more contacts in the interlayer insulating layer, and one or more interconnect conductor layers. The contact and interconnect conductor layers are made of conductive materials, which may be one or a combination of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The interlayer insulating layer is made of an insulating material, and may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride and doped silicon oxide, or other suitable materials.
The adhesive layer 31 connects the array layer 11 and the peripheral device layer 21 in the height direction (the up-down direction shown in fig. 2I) of the three-dimensional memory, wherein the first adhesive surface 41 of the adhesive layer 31 is adhered to the array layer 11, and the second adhesive surface 42 of the adhesive layer 31 is adhered to the peripheral device layer 21. The array layer 11 and the peripheral device layer 21 are electrically connected by an adhesive layer 31.
As shown in fig. 2E, the first interconnect layer 32 may include: bit lines and bit line contacts of the array layer 11, which are exposed at the first bonding surface 41 and electrically connect the bit lines and the array layer 11 as shown in fig. 2I, thereby connecting the bit lines of the array layer 11 to the CMOS transistors 22 in the peripheral device layer 21.
Accordingly, as shown in fig. 2A, the array layer 11 is mainly used for the storage function of the three-dimensional memory, and may include: a graded layer stack, a common source line, a word line, a channel hole penetrating the graded layer stack in the height direction, a channel layer located in the channel hole, and a drain electrode contacting the channel layer, the drain electrode being electrically connected to the bit line contact.
Those skilled in the art will understand that the structure of the first interconnect layer 32 shown in fig. 2E and the structure of the array layer 11 shown in fig. 2A are only a specific solution provided in the present embodiment, and the specific structure thereof may be modified accordingly according to the actual use requirement.
In other embodiments, one skilled in the art may also employ a first interconnect layer 32 structure that includes common source contacts and word line contacts. The common source contact is electrically connected to a common source line in the array layer 11, the word line contact is electrically connected to the word line contact structure 12 in the array layer 11, and the common source contact and the word line contact are exposed at the first bonding surface 41, thereby connecting the word line and the common source line of the array layer 11 to the CMOS transistor 22 in the peripheral device layer 21.
Accordingly, the array layer 11 may include: a graded layer stack, a gate gap 13, a common source line and a word line contact structure 12. The gate slit 13 penetrates the gradation layer stack in the height direction, and the common source line is formed in the gate slit 13 to connect the common source line in the substrate. The word line contact structure 12 partially penetrates the level layer stack along the height direction to lead out the gate layer in the level layer stack.
In other embodiments, those skilled in the art may also adopt the structure of the adhesive layer 36 shown in fig. 3 corresponding to the manufacturing method of the array layer 11 on the bottom and the peripheral device layer 21 on the top, so as to sequentially form bit line contacts and bit lines on the top surface of the first dielectric layer 35; or word line contacts, word lines, common source contacts, and common source lines, to communicate the array layer 11 of the first wafer 10 and the peripheral device layers 21 of the second wafer 20.
As shown in fig. 2E, the adhesive layer 31 may further include: a first metal via 34, the first metal via 34 electrically connecting the first interconnect layer 32 and the peripheral device layer 21. The first metal via 34 is exposed at the second bonding surface 42.
Accordingly, as shown in fig. 2B, the peripheral device layer 21 may include: a peripheral device 22 and a second interconnect layer 23 interconnecting the back-end metal of the peripheral device 22. The second interconnect layer 23 may include therein: and a second metal via 24, wherein the second metal via 24 is electrically connected to the first metal via 34, so as to connect the CMOS transistor 22 in the peripheral device layer 21 to a bit line, a word line and/or a common source line of the array layer 11.
Those skilled in the art will understand that the structure of the first interconnect layer 32 shown in fig. 2E and the structure of the peripheral device layer 21 shown in fig. 2B are only one specific solution provided by the present embodiment. In other embodiments, a person skilled in the art may also change the specific structure of the device according to the actual use requirement.
Based on the above description, the present embodiment provides the above three-dimensional memory, which can separate the adhesive layer 31 from the array layer 11 and the peripheral device layer 21, and has the following advantages: the bonding layer 31 and the array layer 11 which are manufactured respectively can effectively reduce the degree of mutual interference between the array wafer forming process and the CMOS wafer forming process, thereby improving the adaptability. If the process or structure of the array wafer or the CMOS wafer is changed, only the structure of the bonding layer 31 needs to be changed accordingly, and the process or structure of another wafer does not need to be changed.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A method of fabricating a three-dimensional memory, comprising:
providing a first wafer, wherein an array layer of the three-dimensional memory is formed on the first wafer;
providing a second wafer on which a peripheral device layer of the three-dimensional memory is formed;
providing a bonding layer, wherein a first interconnection layer for interconnecting the back-end metal of the array layer is formed in the bonding layer;
bonding the first wafer, the second wafer and the bonding layer to make the bonding layer connect the array layer and the peripheral device layer in a height direction of the three-dimensional memory; wherein the first bonding surface of the bonding layer is bonded to the array layer, the second bonding surface of the bonding layer is bonded to the peripheral device layer, and the array layer and the peripheral device layer are electrically connected through the bonding layer.
2. The method of manufacturing of claim 1, wherein providing the bonding layer further comprises:
providing a third substrate;
sequentially forming a first metal through hole in the bonding layer and the first interconnection layer on the upper surface of the third substrate, wherein the surface of the first interconnection layer is the first bonding surface;
bonding the first wafer, the second wafer, and the bonding layer further comprises:
bonding the array layer of the first wafer to the first bonding surface;
peeling the third substrate to expose the second bonding surface of the bonding layer, the first metal via being exposed to the second bonding surface;
bonding the peripheral device layer of the second wafer to the second bonding surface.
3. The method of manufacturing of claim 1, wherein providing the bonding layer further comprises:
providing a third substrate;
sequentially forming the first interconnection layer and a first metal through hole in the bonding layer on the upper surface of the third substrate, wherein the first metal through hole is exposed to the second bonding surface;
bonding the first wafer, the second wafer, and the bonding layer further comprises:
bonding the peripheral device layer of the second wafer to the second bonding surface;
peeling the third substrate to expose the first bonding surface of the bonding layer, the first bonding surface being a surface of the first interconnect layer;
bonding the array layer of the first wafer to the first bonding surface.
4. The method of manufacturing of claim 2 or 3, wherein the providing a third substrate further comprises: forming a first dielectric layer on the upper part of the third substrate, wherein the bonding layer is formed on the upper surface of the first dielectric layer;
the peeling off the third substrate further includes: and cutting the third substrate by taking the interface of the first medium layer in the third substrate as a cutting interface, and removing the first medium layer to expose the first bonding surface or the second bonding surface of the bonding layer.
5. The method of manufacturing of claim 4, wherein forming a first dielectric layer over the third substrate further comprises:
and carrying out hydrogen injection treatment on the surface of the third substrate to form a hydrogen injection layer, wherein the first dielectric layer is the hydrogen injection layer.
6. The method of manufacturing of claim 4, wherein forming a first dielectric layer over the third substrate further comprises:
and carrying out porous oxidation treatment on the surface of the third substrate to form a porous silicon oxide layer, wherein the first dielectric layer is the porous silicon oxide layer.
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| CN110574162B (en) * | 2019-08-02 | 2021-02-12 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
| KR102611127B1 (en) | 2019-08-02 | 2023-12-08 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3D memory devices and manufacturing methods thereof |
| CN110648932B (en) * | 2019-11-28 | 2020-04-17 | 长江存储科技有限责任公司 | Semiconductor chip and manufacturing method thereof |
| CN111211126B (en) * | 2020-01-13 | 2023-12-12 | 长江存储科技有限责任公司 | Three-dimensional memory and forming method thereof |
| KR20210145417A (en) * | 2020-05-25 | 2021-12-02 | 에스케이하이닉스 주식회사 | Three dimensional memory device and method for fabricating threrof |
| CN111937149B (en) * | 2020-07-16 | 2021-07-09 | 长江存储科技有限责任公司 | Method for bonding semiconductor structure and semiconductor device thereof |
| CN113555352B (en) * | 2021-07-20 | 2022-08-26 | 长江存储科技有限责任公司 | Three-dimensional memory |
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| US7863748B2 (en) * | 2003-06-24 | 2011-01-04 | Oh Choonsik | Semiconductor circuit and method of fabricating the same |
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| JP2018152419A (en) * | 2017-03-10 | 2018-09-27 | 東芝メモリ株式会社 | Semiconductor memory device |
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