CN109716532A - 氧化物半导体装置及其制造方法 - Google Patents

氧化物半导体装置及其制造方法 Download PDF

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CN109716532A
CN109716532A CN201780056959.9A CN201780056959A CN109716532A CN 109716532 A CN109716532 A CN 109716532A CN 201780056959 A CN201780056959 A CN 201780056959A CN 109716532 A CN109716532 A CN 109716532A
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oxide semiconductor
semiconductor devices
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tft
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后藤哲也
水村通伸
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Tohoku University NUC
V Technology Co Ltd
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Abstract

本发明提供一种氧化物半导体装置及其制造方法。具备由氧化物半导体构成的活性层区域的氧化物半导体装置中,可提高施加压力时的稳定性。氧化物半导体装置具备由铟(In)、镓(Ga)、锌(Zn)的氧化物半导体构成的活性层区域,该活性层区域中,在以数密度为1×1016~1×1020cm‑3的范围内含有选自第4族元素的钛(Ti)、锆(Zr)、铪(Hf)或第14族元素的碳(C)、硅(Si)、锗(Ge)、锡(Sn)的元素。

Description

氧化物半导体装置及其制造方法
技术领域
本发明涉及一种氧化物半导体装置及其制造方法。
背景技术
TFT(薄膜晶体管,Thin Film Transistor)作为形成于玻璃基板上的平板显示器用的有源元件而普及。TFT作为基本结构为具备栅极端子、源极端子及漏极端子的3端子元件,其具有将形成于基板上的半导体薄膜用作供电子或电洞移动的通道层,对栅极端子施加电压而控制在通道层流动的电流,并切换源极端子与漏极端子之间的电流的功能。
作为TFT的通道层,广泛使用多晶硅薄膜和非晶硅薄膜,随着以智能手机为首的移动电子设备的普及,要求小型画面的显示器具有超高清晰/高画质且低电耗的图像显示性能,作为能够应对该性能的TFT材料,氧化物半导体受到关注。
众所周知,氧化物半导体当中作为铟(In)、镓(Ga)、锌(Zn)的氧化物的IGZO与以往的非晶硅等相比,是可实现显示器的高清晰化和低电耗化的TFT材料。下述专利文献1中示出一种透明非晶质氧化物薄膜,其利用气相成膜法形成膜且由元素In、Ga、Zn及O构成,关于氧化物的组成,经过结晶化的组成为InGaO3(ZnO)m(m为小于6的自然数),将不添加杂质离子而电子迁移率超过1cm2/(V·秒)并且电子载流子浓度为1016/cm3以下的半绝缘性的透明半绝缘性非晶质氧化物薄膜设为TFT的通道层。
现有技术文献
专利文献
专利文献1:日本特开2010-219538号公报
发明内容
发明要解决的技术课题
如上述,IGZO作为显示器用TFT的通道材料有效,但有待于改进由缺氧引起的缺陷所造成的TFT特性、尤其阈值电压的压力施加时的稳定性。尤其,移动电子设备以在室外使用作为前提,因此要求可应对太阳光照射、温度上升等的容易受压力的使用状况,并且,引起因长时间连续运行而导致基于背光的光压力的累积的问题。
本发明是为了解决这种问题而提出的。即,本发明的课题在于,提高具备氧化物半导体的活性层区域的氧化物半导体装置中压力施加时的稳定性。
用于解决技术课题的手段
为了解决这种问题,基于本发明的氧化物半导体装置为具备以下结构的装置。
一种氧化物半导体装置,其具备铟(In)、镓(Ga)、锌(Zn)的氧化物半导体的活性层区域,该氧化物半导体装置的特征在于,具备在以数密度为1×1016~1×1020cm-3的范围内含有选自第4族元素的钛(Ti)、锆(Zr)、铪(Hf)或第14族元素的碳(C)、硅(Si)、锗(Ge)、锡(Sn)的元素的所述活性层区域。
附图说明
图1是表示TFT的结构例的说明图。
图2是表示具备经Si离子注入的IGZO活性层区域的TFT具有施加压力时的稳定性的曲线图。
图3是表示对经Si离子注入的IGZO活性层区域进行激光退火,由此能够减少TFT的滞后电压的曲线图。
具体实施方式
以下,参考附图对本发明的实施方式进行说明。图1表示作为本发明的实施方式所涉及的氧化物半导体装置的TFT的结构例。TFT1中,在玻璃基板10上形成有栅极端子11,以覆盖该栅极端子11的方式形成有栅极绝缘膜12,在栅极绝缘膜12上形成有通道层13、与通道层接触的源极端子14及漏极端子15。并且,以覆盖通道层13、源极端子14及漏极端子15的方式形成有钝化膜16。
关于各端子的材料,例如栅极端子11、源极端子14及漏极端子15由TiN构成,栅极绝缘膜12及钝化膜16由SiO2构成。而且,如后所述,作为活性层区域的通道层13由注入了特定元素的In、Ga及Zn的氧化物半导体(IGZO)构成。该TFT1具有对栅极端子11施加电压以控制在通道层13流动的电流,并且切换源极端子14与漏极端子15之间的电流的功能。
注入于通道层13的元素是作为第4族元素的Ti、Zr、Hf或作为第14族元素的C、Si、Ge、Sn。以下,以注入Si的情况为例进行说明,但只要是上述的各元素,则能够获得相同的效果。这里的,元素注入量为对氧化物半导体注入使块状材料以外的材料起到杂质的功能的程度的量,由此,能够改善由缺氧引起的缺陷所导致的TFT特性,尤其阈值电压的稳定性。优选的元素注入量以数密度为1×1016~1×1020cm-3的范围。
以下,示出获得图1所示的结构的TFT1的具体的工序例(第1实施例)。首先,通过溅射在玻璃基板10上形成150nm左右的TiN膜,并通过光刻和蚀刻进行图案化,由此形成栅极端子11。栅极端子11的材料不限于TiN,也可以是Al、Ti、Mo及W等。
接着,通过等离子体CVD(气体SiH4、O2、Ar)形成膜SiO2,以形成栅极绝缘膜12。栅极绝缘膜12的材料不限于SiO2,也可以是硅氮化膜和Al2O3等。
之后,使用IGZO(In:Ga:Zn=1:1:1)的靶,通过溅射成膜通道层13。作为成膜条件的一例,将膜厚设定为50nm,并在Ar/O2环境下将压力设为5mTorr,将O2分压设为16%。这里的,成膜中例如能够使用旋转磁铁溅射装置。通道层13中的IGZO的元素比率并不限定于上述的比率(In:Ga:Zn=1:1:1)。
另外,上述的O2分压16%是通过之后所进行的水蒸气环境的400℃退火,缺氧量成为1×1017cm-3以下的条件。另一方面,不进行元素注入的以往的IGZO膜(通道层)中,以O2分压2%成膜。这种情况下,400℃的退火后的缺氧量成为1×1018cm-3左右。
上述的成膜之后,对IGZO的通道层13使用离子注入机注入Si。关于注入条件,作为一例将Si+离子以能量40keV注入1×1013cm-2的剂量。由此,Si原子以1×1018cm-3的密度注入于IGZO膜。Si原子在IGZO中的密度为1×1016~1×1020cm-3,优选为1×1017~1×1019cm-3
注入Si之后,在水分环境(H2O/O2=100/900sccm)、400℃下进行1小时退火。退火温度不限于400℃,可以为300℃~800℃,优选为350℃~500℃。并且,这里的,退火不限于水分环境,也可以是氧气环境。
注入有Si的IGZO膜在上述的退火之后,通过光刻和蚀刻而进行图案形成,从而形成岛状的通道层13。
之后,将成为源极端子14和漏极端子15的TiN例如形成150nm的膜,并通过光刻和蚀刻形成源极端子14和漏极端子15。源极端子14和漏极端子15的材料不限于Ti,也可以是Al、Ti、Mo、W等。之后,将成为钝化膜16的SiO2通过等离子体CVD等成膜,之后,通过光刻和蚀刻以能够与各端子(源极端子14、漏极端子15、栅极端子11)电接触的方式形成连接端子。
通过试验证实,如此获得的TFT1(参考图1)对负偏压/光压力的连续施加显示出稳定的TFT特性。关于试验条件,器件尺寸为通道长度:40μm、通道宽度:20μm,作为压力条件,对栅极电压施加-20V,在环境气体温度60℃下进行了基于白色LED的光照射(30,000lx)。
图2表示随时间施加上述的压力时的TFT1的阈值电压的变化(ΔVT(V))。如图2所示,确认到相对于具备未注入Si离子的IGZO膜的通道层的TFT相比,具备注入有Si离子的IGZO膜的通道层13的TFT1的阈值电压的随时间变化(ΔVT(V))更少。
这种试验结果表示,在活性层区域的IGZO膜中规定量注入Si,由此TFT动作的稳定性提高。认为出现这种结果的原因不在于由缺氧引起的载波,而在于Si起到掺杂剂的作用,且供给作为载波的电子,并且还在于因缺氧形成的IGZO的带隙内的较深的能级的捕集量减少。
接着,对其他工序例(第2实施例)进行说明。该例中,进行上述的工序例(第1实施例)中的水分环境下的退火之前,进行了基于波长400nm以下的XeF激光的局部激光退火。其他工序与第1实施例相同。
激光退火中的激光能量密度设为一次照射下150mJ/cm2,并将此重叠,由此进行了退火。关于退火的区域,设为60μm×60μm,并以包括成为TFT的通道层13的活性层区域的方式进行了退火。在激光照射的对位中,使用了栅极端子11的图案。另外,在制作顶栅极TFT时,无法将栅极端子11使用在对位中,但自如地形成任意的对位图案,由此能够在活性层区域精确地实施局部激光退火。
图3是将依据在上述的工序例中制作的TFT的传递特性(漏极电流的栅极电压依存性)求出的阈值电压附近的滞后电压,相对于XeF激光退火的shot(发射)次数标绘的的曲线图。图3中,示出没有Si离子注入的情况和没有Si离子注入的情况。
曲线图纵轴的滞后电压(V)是将栅极电压从负到正扫描的情况的电压特性与从正到负扫描而求出的电压特性的偏差,具体而言,作为依据两者的电压特性求出的阈值电压的差而进行了评价。
如从图3所知,能够确认到通过导入XeF激光的局部退火,将IGZO使用于活性层区域的TFT的滞后电压减少,TFT的稳定性提高的情况。若在IGZO膜中存在例如俘获电子的陷阱能级,则滞后电压增加,且导致成为不稳定的器件,但认为在IGZO的活性层区域注入Si而进行激光退火,由此如俘获电子的陷阱能级变少。
如以上说明,若依本发明的实施方式的氧化物半导体装置及其制造方法,则能够提高施加压力时的稳定性,且能够提高在室外使用和长时间使用等情况下的耐久性。并且,通过追加对活性层区域的激光退火,能够获得高稳定性的器件。
符号说明
1-TFT,10-玻璃基板,11-栅极端子,12-栅极绝缘膜,13-通道层,14-源极端子,15-漏极端子,16-钝化膜。

Claims (3)

1.一种氧化物半导体装置,其具有由铟(In)、镓(Ga)、锌(Zn)的氧化物半导体构成的活性层区域,该氧化物半导体装置的特征在于,具备在以数密度为1×1016~1×1020cm-3的范围内含有选自第4族元素的钛(Ti)、锆(Zr)、铪(Hf)或第14族元素的碳(C)、硅(Si)、锗(Ge)、锡(Sn)中的元素的所述活性层区域。
2.根据权利要求1所述的氧化物半导体装置,其特征在于,
所述活性层区域为照射波长400nm以下的激光而进行退火的区域。
3.一种氧化物半导体装置的制造方法,所述氧化物半导体装置具有由铟(In)、镓(Ga)、锌(Zn)的氧化物半导体构成的活性层区域,该氧化物半导体装置的制造方法的特征在于,具有:
对所述活性层区域以数密度为1×1016~1×1020cm-3的范围内离子注入选自第4族元素的钛(Ti)、锆(Zr)、铪(Hf)或第14族元素的碳(C)、硅(Si)、锗(Ge)、锡(Sn)中的元素的工序;及
对离子注入后的所述活性层区域照射波长400nm以下的激光而进行退火的工序。
CN201780056959.9A 2016-10-21 2017-09-04 氧化物半导体装置及其制造方法 Pending CN109716532A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114008237A (zh) * 2019-06-28 2022-02-01 株式会社爱发科 溅射靶及溅射靶的制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019225250A1 (ja) * 2018-05-21 2019-11-28 ソニー株式会社 固体撮像素子及びその製造方法
CN112335058B (zh) * 2018-06-21 2024-03-08 株式会社爱发科 氧化物半导体薄膜、薄膜晶体管及其制造方法、以及溅射靶材
JP7230743B2 (ja) * 2019-08-27 2023-03-01 株式会社デンソー 半導体装置の製造方法
US11430898B2 (en) * 2020-03-13 2022-08-30 Applied Materials, Inc. Oxygen vacancy of amorphous indium gallium zinc oxide passivation by silicon ion treatment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101027A (ja) * 2009-03-31 2011-05-19 Panasonic Corp フレキシブル半導体装置およびその製造方法
CN102163625A (zh) * 2011-03-17 2011-08-24 复旦大学 用于氧化物薄膜晶体管的半导体层材料铟锌钛氧化物
JP2012028481A (ja) * 2010-07-22 2012-02-09 Fujifilm Corp 電界効果型トランジスタ及びその製造方法
JP2013110176A (ja) * 2011-11-18 2013-06-06 Semiconductor Energy Lab Co Ltd 半導体装置および半導体装置の作製方法
CN103688364A (zh) * 2011-07-29 2014-03-26 富士胶片株式会社 场效晶体管的制造方法及场效晶体管、显示装置、图像传感器及x射线传感器
JP2015228495A (ja) * 2014-05-08 2015-12-17 株式会社Flosfia 結晶性積層構造体、半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019337B1 (ko) 2004-03-12 2011-03-07 도꾸리쯔교세이호징 가가꾸 기쥬쯔 신꼬 기꼬 아몰퍼스 산화물 및 박막 트랜지스터
JP5052693B1 (ja) * 2011-08-12 2012-10-17 富士フイルム株式会社 薄膜トランジスタ及びその製造方法、表示装置、イメージセンサー、x線センサー並びにx線デジタル撮影装置
KR102125822B1 (ko) * 2014-07-22 2020-06-23 가부시키가이샤 플로스피아 결정성 반도체막 및 판상체 및 반도체장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101027A (ja) * 2009-03-31 2011-05-19 Panasonic Corp フレキシブル半導体装置およびその製造方法
JP2012028481A (ja) * 2010-07-22 2012-02-09 Fujifilm Corp 電界効果型トランジスタ及びその製造方法
CN102163625A (zh) * 2011-03-17 2011-08-24 复旦大学 用于氧化物薄膜晶体管的半导体层材料铟锌钛氧化物
CN103688364A (zh) * 2011-07-29 2014-03-26 富士胶片株式会社 场效晶体管的制造方法及场效晶体管、显示装置、图像传感器及x射线传感器
JP2013110176A (ja) * 2011-11-18 2013-06-06 Semiconductor Energy Lab Co Ltd 半導体装置および半導体装置の作製方法
JP2015228495A (ja) * 2014-05-08 2015-12-17 株式会社Flosfia 結晶性積層構造体、半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114008237A (zh) * 2019-06-28 2022-02-01 株式会社爱发科 溅射靶及溅射靶的制造方法
US12012650B2 (en) 2019-06-28 2024-06-18 Ulvac, Inc. Sputtering target and method of producing sputtering target

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