CN109698236B

CN109698236B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN109698236B
Application number: CN201811242525.0A
Authority: CN
Inventors: 山田文生
Original assignee: Sumitomo Electric Device Innovations Inc
Current assignee: Sumitomo Electric Device Innovations Inc
Priority date: 2017-10-24
Filing date: 2018-10-24
Publication date: 2023-09-01
Anticipated expiration: 2038-10-24
Also published as: US20190123152A1; US10546935B2; TW201935688A; TWI772545B; CN109698236A; JP6874928B2; JP2019079909A

Abstract

A semiconductor device implementing a field plate is disclosed. The semiconductor device includes a source electrode, a gate electrode, and a drain electrode; an insulating film covering at least the drain electrode; a field plate including a first portion overlapping the gate electrode and a second portion not overlapping the gate electrode; and a source interconnect connected to the source electrode. The semiconductor device of the present application is characterized in that the first portion and the second portion are each electrically connected to the source interconnect.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Cross Reference to Related Applications

The present application is based on and claims priority from japanese patent application No.2017-205093 filed on 24, 10, 2017, which is incorporated herein by reference in its entirety.

Technical Field

The present application relates to a semiconductor device, and more particularly, to a semiconductor device mainly made of a nitride semiconductor material.

Background

Japanese patent application laid-open No. jp2008-277604a has disclosed a Field Effect Transistor (FET) of a semiconductor device type having a field plate. Semiconductor devices made mainly of nitride semiconductor materials sometimes provide field plates in order to mitigate the electric field induced at the edges of their gate electrodes. The field plate generally covers the gate electrode with an insulating film therebetween, and can suppress a reduction in leakage current after the rigid condition of the high drain bias and the deep gate bias occurring simultaneously is just removed, which is generally referred to as drain current collapse. The field plate also isolates the gate electrode from the drain electrode.

The field plate is typically connected to the source electrode such that the field plate extends to a passive region surrounding the active region of the device and is in contact with a source interconnect (source interconnection) extending from the source electrode, wherein those arrangements of the field plate, the source electrode and the source interconnect are disclosed in, for example, the related patent documents mentioned above. However, the field plate may break at a step inherently formed by one side of the gate electrode.

Disclosure of Invention

One aspect of the present application relates to a semiconductor device including a source electrode, a drain electrode, and a gate electrode; an insulating film; a field plate; and a source interconnect. Those electrodes extend in the longitudinal direction. The insulating film covers at least the gate electrode and extends between the gate electrode and the drain electrode. The field plate provides a first portion overlapping the gate electrode with the insulating film interposed therebetween, and a second portion not overlapping the gate electrode, the second portion extending over the insulating film between the gate electrode and the drain electrode. The source interconnect is in contact with and extends from the source electrode. The semiconductor device of the present application is characterized in that not only the second portion of the field plate is electrically connected to the source interconnect, but also the first portion is electrically connected to the source interconnect.

Drawings

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the application with reference to the drawings, in which:

fig. 1 is a plan view showing a semiconductor device according to an embodiment of the present application;

fig. 2A and 2B are cross-sectional views of the semiconductor device shown in fig. 1 taken along lines IIa-IIa and IIb-IIb, respectively, in fig. 1;

fig. 3A and 3B are a plan view and a sectional view, respectively, in the process of forming the semiconductor device shown in fig. 1, wherein fig. 3B is taken along a line IIIb-IIIb shown in fig. 3A;

fig. 4A and 4B are a plan view and a sectional view, respectively, in the process of forming the semiconductor device shown in fig. 1, wherein fig. 4B is taken along a line IVb-IVb shown in fig. 4A;

fig. 5A and 5B are a plan view and a cross-sectional view, respectively, in forming the semiconductor device shown in fig. 1 in the process of forming the same, wherein fig. 5B is taken along a line Vb-Vb shown in fig. 5A;

fig. 6A and 6B are a plan view and a cross-sectional view, respectively, of the semiconductor device shown in fig. 1 in the process of forming the same, wherein fig. 6B is taken along line VIb-VIb shown in fig. 6A;

fig. 7 is a plan view of a conventional semiconductor device having a field plate; and

fig. 8A to 8C are sectional views of the conventional semiconductor device shown in fig. 7, wherein fig. 8A to 8C are taken along lines VIIIa to VIIIa, VIIIb to VIIIb, VIIIc to VIIIc, respectively, shown in fig. 7.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Next, embodiments according to the present application will be described with reference to the drawings. The application is not, however, limited to the embodiments described and has all changes and modifications and equivalents within the scope as defined by the appended claims. In the description of the drawings, numerals or symbols identical or similar to each other will refer to elements identical or similar to each other without repeated explanation.

Fig. 1 is a plan view showing a semiconductor device 1A according to an embodiment of the present application. Fig. 2A and 2B are sectional views of the semiconductor device 1A taken along lines IIa-IIa and IIb-IIb, respectively, shown in fig. 1. For simplicity of explanation, the insulating films 21 to 23 are omitted in fig. 1.

The semiconductor device 1A of the present embodiment provides a substrate 11, a semiconductor stack 18 provided on the substrate 11, and a drain electrode 31, a source electrode 32, and a gate electrode 33 provided on the semiconductor stack 18, respectively. The substrate 11 is prepared for epitaxially growing a semiconductor layer on a planar main surface thereof, and the substrate 11 may be made of silicon carbide (SiC), sapphire (Al ₂ O ₃ ) Silicon (Si), diamond (C), etc. The substrate may have a thickness of about 500 μm.

The semiconductor device 1A of the present embodiment is a Field Effect Transistor (FET), specifically a High Electron Mobility Transistor (HEMT), which includes a channel layer 12 and a barrier layer 13 in a semiconductor stack 18, wherein the channel layer 12 and the barrier layer 13 are epitaxially grown on a substrate 11, and a two-dimensional electron gas (2 DEG) is induced in the channel layer 12 at an interface with the barrier layer 13. The 2DEG may be used as a channel of the HEMT 1A. The channel layer 12 may be made of gallium nitride (GaN) to a thickness of about 1 μm, specifically, 0.5 μm to 1.2 μm. The barrier layer 13 may be made of, for example, aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and/or indium aluminum gallium nitride (InAlGaN), and has a thickness of about 20nm, specifically, 10nm to 30nm. The present embodiment provides a composition comprising Al _0.25 Ga _0.75 N is a barrier layer 13 of thickness 20 nm. The semiconductor stack 18 may also provide a cap layer on the barrier layer 13, wherein the cap layer may be made of GaN or n-type GaN, with a thickness of about 5nm.

The semiconductor stack 18 is divided into two parts, one of which is an active area A1 and the other of which is an inactive area A2 surrounding the active area A1. The active region A1 may be used as the semiconductor device 1A, while the inactive region A2 has no carriersA function of transmission; specifically, the inactive region A2 is formed by implanting argon ions (Ar ⁺ ) To increase the resistivity thereof. Thus, the inactive region A2 may electrically isolate the active region A1.

The drain electrode 31 and the source electrode 32 are disposed in and in contact with the active region A1. The semiconductor device 1A of the present embodiment provides one drain electrode 31 and two source electrodes 32, with the drain electrode 31 sandwiched between the two source electrodes 32. The drain electrode 31 and the source electrode 32, and a so-called ohmic electrode exhibiting non-rectifying characteristics, are formed by alloying a stacked titanium (Ti) metal having a thickness of about 10nm and an aluminum (Al) metal having a thickness of about 300nm, wherein the drain electrode 31 and the source electrode 32 have rectangular planar shapes extending in respective longitudinal directions (specifically, in the up-down direction in fig. 1). Another Ti layer having a thickness of about 10nm may cover the Al layer.

The drain electrode 31 and the source electrode 32 may be in contact with the barrier layer 13. In an alternative, the electrode may be in contact with the cap layer when the semiconductor stack 18 provides the cap layer on the barrier layer 13. In another alternative, the drain electrode 31 and the source electrode 32 may be in contact with the channel layer 12 by removing a portion of the blocking layer 13.

The inactive area A2 may provide a drain interconnect 41, which drain interconnect 41 connects the individual semiconductor devices 1A that are all insulated due to the presence of the inactive area A2. The inactive region A2 may also provide a source interconnect 42, the source interconnect 42 connecting source electrodes disposed in the respective active regions A1. In the present embodiment, the drain interconnect 41 and the source interconnect 42 extend in the longitudinal direction of the drain electrode 31 and the source electrode 32, and are led out (extracted) in the longitudinal direction but in the opposite direction. That is, the drain interconnect 41 overlaps the drain electrode 31 and is led upward in fig. 1; while source interconnect 42 overlaps source electrode 32 but is routed downward in fig. 1. More specifically, the drain electrode 31 is led out through the drain interconnect 41, and the drain interconnect 41 extends along the longitudinal direction of the drain electrode 31 and passes over one end of the (cross) drain electrode 31, but the other end 41a thereof is within the drain electrode 31.

The source electrode 32 is led out through the source interconnect 42, the source interconnect 42 extending in the longitudinal direction of the source electrode 32 across one end of the source electrode 32, but the other end 42a of the source interconnect 42 is present in the inactive area A2 to be connected with the field plate 34 therein. The drain interconnect 41 and the source interconnect 42 may be formed by plating gold (Au) with a thickness of 4 μm to 6 μm.

The gate electrode 33 extends from the active region A1 to the inactive region A2 in the longitudinal direction at the side of the drain interconnect 41. The present embodiment provides two gate electrodes 33 sandwiching the drain electrode 31 therebetween, and places the gate electrodes 33 between the drain electrode 31 and the respective source electrodes 32. Accordingly, the gate electrode 33 is disposed parallel to the drain electrode 31 and the source electrode 32. The gate electrode 33 may have stacked metals nickel (Ni), palladium (Pd), and gold (Au), wherein these metals may have thicknesses of about 0.1 μm, about 50nm, and about 0.5 μm, respectively, wherein Ni forms a schottky contact with the semiconductor stack 18. The gate electrode 33 preferably has a total thickness or height of more than 0.3 μm in consideration of deposition conditions of the respective metals, but the total thickness or height of the gate electrode 33 is less than 0.7 μm from the viewpoint of stably covering the gate electrode 33 with the second insulating film 22. The two gate electrodes 33 are connected to gate interconnects 36, and the gate interconnects 36 extend laterally in the inactive region A2 along the edges of the active region A1. The gate interconnect 36 connects each semiconductor device 1A formed on the substrate 11.

The gate electrode 33 is bent at one end thereof toward the source interconnect 42 in the inactive region A2. Specifically, the gate electrode 33 passes through the interface between the active region A1 and the inactive region A2 on the opposite side from the gate interconnect 36, and is bent toward the source interconnect 42 at the extension portion 33a thereof. An extension portion 33a of the gate electrode 33 exists outside the source electrode 32. As shown in fig. 2B, the extension portion 33a of the gate electrode 33 is placed between the inactive area A2 and the source interconnect 42, and the inactive area A2 and the source interconnect 42 sandwich the field plate 34 therebetween.

As shown in fig. 2A and 2B, the HEMT 1A of the present embodiment also provides the first to third insulating films 21 to 23 and the field plate 34. The insulating films 21 to 23 passivate surfaces of the semiconductor stack 18, the drain electrode 31, the source electrode 32, the gate electrode 33, and the field plate 34.

The first insulating film 21 covering the semiconductor stack 18 exposed between the drain electrode 31, the source electrode 32, and the gate electrode 33 provides at least three openings in which the surface of the semiconductor stack 18 is exposed, wherein the openings are a drain opening, a source opening, and a gate opening. The drain electrode 31 fills the drain opening, the source electrode 32 fills the source opening, and the gate electrode fills the gate opening. The drain electrode 31, the source electrode 32, and the gate electrode 33 may be in direct contact with the surface of the semiconductor stack 18 in the respective openings. The gate opening has a length of 0.4 μm along the direction connecting the drain electrode 31 and the source electrode 32, i.e., the HEMT has a gate length of 0.4 μm. The first insulating film 21 may be an inorganic material containing silicon (Si), typically silicon nitride (SiN) having a thickness of about 50 nm.

The second insulating film 22 provided on the first insulating film 21 covers the drain electrode 31, the source electrode 32, and the gate electrode 33. The second insulating film 22 has an opening 22c and an opening 22d on the drain electrode 31 and the source electrode 32, and a drain interconnect 41 and a source interconnect 42 are formed through the opening 22c and the opening 22 d. The drain interconnect 41 may contact the drain electrode 31 through the opening 22c, and the source interconnect 42 may contact the source electrode 32 through the opening 22 d.

The second insulating film 22 provides a portion 22a covering the gate electrode 33 and another portion 22b existing between the gate electrode 33 and the drain electrode 31, wherein the former portion 22a is disposed on and above the gate electrode 33 and the latter portion 22b is disposed above the active region A1 between the gate electrode 33 and the drain electrode 31. The two portions 22a and 22b constitute a step resulting from the presence of the gate electrode 33. The second insulating film 22 may also be made of an inorganic material containing Si, typically SiN having a thickness of 0.4 μm to 0.6 μm, wherein this embodiment has the second insulating film 22 having a thickness of 0.5 μm.

The third insulating film 23 provided on the second insulating film 22 covers the drain interconnect 41 and the source interconnect 42. The third insulating film 23 may also be made of an inorganic material containing Si, typically SiN, preferably SiN having a thickness of 0.1 μm. The third insulating film 23 can prevent the drain interconnect 41 and the source interconnect 42 from being shorted and oxidized.

The field plate 34 may be made of a metal such as titanium (Ti) and gold (Au) stacked from one side of the substrate 11, for example. The field plate 34 of the present embodiment provides two parts. As shown in fig. 1, one of the portions (i.e., the portion indicated by the sparse dot region 34a in fig. 2A and 2B) may extend above the gate electrode 33, and the other portion (i.e., the portion indicated by the dense dot region 34B in fig. 2A and 2B) may extend to the region between the gate electrode 33 and the drain electrode 31. In addition, as shown in fig. 2A, the field plate 34 overlaps the gate electrode 33 at a first portion 34a thereof, and extends over the second insulating film 22 between the gate electrode 33 and the drain electrode 41 in a second portion 34b thereof which does not overlap the gate electrode 33. The first portion 34a preferably has a width narrower than 2 μm. The field plate 34 is covered with the third insulating film 23 to prevent oxidation of the field plate 34.

The field plate 34 may electrically shield the gate electrode 33 from the drain electrode 31 and weaken the electric field concentrated at the edge of the gate electrode 33. The field plate 34 preferably has a thickness less than that of the gate electrode 33. For example, the field plate 34 of the first metal (which may be made of titanium (Ti)) in contact with the second insulating film 22 has a thickness of 5nm to 30nm, typically 10nm; while the second metal, which may be made of gold (Au), disposed over the first metal, preferably has a thickness of 0.1 μm to 0.3 μm, typically 0.2 μm.

The field plate 34 protrudes from the active region A1 at its end opposite the gate interconnect 36, extends into the inactive region A2, is bent here at approximately 90 °, and extends into a region outside the end of the source electrode 32. That is, the respective portions 34a and 34b of the field plate 34 are present in the region outside the source electrode 32 in the inactive region A2.

The first portion 34a (which overlaps the gate electrode 33, and the second insulating film 22a is interposed between the gate electrode 33 and the first portion 34 a) also protrudes from the active region A1 into the inactive region A2, where it is bent at 90 ° toward the source electrode 32, and where it is in contact with the source interconnect 42.

Further, the second portion 34b of the field plate 34 (which covers a portion of the second insulating film 22b between the gate electrode 33 and the drain electrode 31) extends beyond the active region A1 into the inactive region A2 outside the source electrode 32 to surround the first portion 34a of the field plate 34; and then contacts the source interconnect 42 there. Therefore, even if the first portion 34a and the second portion 34b are physically isolated by the step formed in the second insulating film 22 due to the thickened gate electrode 33, the two portions 34a and 34b are commonly connected to the source interconnect 42 outside the source electrode 32 in the inactive region A2.

The field plate 34 preferably has a width W2 in the inactive region A2 outside the source electrode 42 that is the total width of the first and second portions 34a and 34b, which is greater than a width W1 that is the total width of the first and second portions 34a and 34b in the active region A1. The width W1 may be, for example, 0.5 μm to 2.0 μm, in this embodiment 1.0 μm, and the width W2 may be, for example, 0.5 μm to 10 μm, in this embodiment 3.0 μm.

Next, a process of forming the semiconductor device 1A according to an embodiment of the present application will be described. Fig. 3A, 4A, 5A, and 6A are plan views of the semiconductor device shown in fig. 1 at various steps in the process of forming the device 1A, and fig. 3B, 4B, 5B, and 6B are cross-sectional views corresponding to fig. 3A, 4A, 5A, and 6A, respectively, wherein the cross-sectional views are taken along respective lines shown in the drawings corresponding thereto.

The process first prepares a semiconductor stack 18 by sequentially and epitaxially growing a nitride semiconductor layer including a channel layer 12 and a barrier layer 13 on a substrate 11. Metal Organic Chemical Vapor Deposition (MOCVD) techniques can readily grow semiconductor layers. Thereafter, the semiconductor stack 18 is divided into an active region A1 and an inactive region A2. Specifically, the region to be converted into the active region A1 is covered with a mask, and the mask is filled with, for example, argon (Ar ⁺ ) Ion implantation of ions into the remaining regions not covered by the mask may form inactive regions A2 surrounding the active region A1. Thereafter, a drain electrode 31 and a source electrode 32 may be formed on the active region A1. As shown in fig. 3A, the drain electrode 31 and the source electrode 32 have rectangular planar shapes.

Thereafter, the drain electrode 31, the source electrode 32, and other areas exposed from the drain electrode 31 and the source electrode 32 are completely covered with the first insulating film 21, wherein the first insulating film 21 may be formed by a chemical vapor deposition technique. In the alternative, the first insulating film 21 is first deposited on the semiconductor stack 18; then, an opening is formed in the first insulating film 21. A drain electrode 31 and a source electrode 32 are formed in the semiconductor stack 18 to fill the opening. Then, an opening 21a, i.e., a gate opening, is formed in the first insulating film 21 to expose the surface of the semiconductor stack 18 in the opening, and a gate electrode 33 is deposited to fill the gate opening 21a and the gate electrode 33 extends partially over the first insulating film 21 around the gate opening 21a, as shown in fig. 4B. In the present embodiment, as shown in fig. 4A, the gate electrode 33 protrudes from the active region A1 and is bent toward the source electrode 32 in the inactive region A2 to form an extension portion 33a therein. Accordingly, the extension portion 33a of the gate electrode 33 is present outside the source electrode 32 in the inactive region A2, and the gate electrode 33 is in direct contact with the semiconductor stack 18 at its extension portion 33a, but has no influence on the operation of the semiconductor device 1A because the extension portion 33a is present in the inactive region A2.

Thereafter, as shown in fig. 5A and 5B, the second insulating film 22 covers the drain electrode 31, the source electrode 32, and the gate electrode 33, wherein the second insulating film 22 can be deposited by CVD technique. Thereafter, the process forms a field plate 34. Specifically, a patterned photoresist (not shown in the drawings) having openings corresponding to the field plates 34 is first prepared on the second insulating film 22. The opening in the photoresist combines a region for the first portion 34a with another region for the second portion 34 b. Metal is deposited on the second insulating film 22 and on the patterned photoresist and the residual metal accumulated on the patterned photoresist is removed, and only the first portion 34a and the second portion 34b of the field plate 34 may remain on the second insulating film 22, which is commonly referred to as a lift-off process. As shown in fig. 5B, because of the steps in the second insulating film 22, the first portion 34a, which is denoted as a sparse dot area in fig. 5A, overlapping the gate electrode 33 is physically isolated from the second portion 34B, which is denoted as a dense dot area.

Thereafter, as shown in fig. 6A and 6B, the process exposes the drain electrode 31, the source electrode 32, and the gate electrode 33 by forming respective openings 22c and 22d in the second insulating film 22. Then, the drain interconnect 41 and the source interconnect 42 are formed by gold plating (Au). The drain interconnect 41 extends toward the opposite side of the active region A1 from the gate interconnect 36; meanwhile, the source interconnect 42 extends toward the gate interconnect 36 side. Further, the source interconnect 42 also extends beyond the edge of the source electrode 32 in the side face of the drain interconnect 41, and protrudes within the inactive region A2 outside the source electrode 32. Where the source interconnect 42 may then be in contact with both the first portion 34a and the second portion 34b of the field plate 34. Accordingly, although the first and second portions 34a and 34b are physically isolated within the active region A1 due to the steep step formed in the second insulating film 22, the first and second portions 34a and 34b may be in physical contact with the source interconnect 42. Finally, the semiconductor device 1A of the present embodiment can be completed by covering the drain interconnect 41, the source interconnect 42, the gate interconnect 36, and the first portion 34a and the second portion 34b of the field plate 34 with the third insulating film 23, wherein the third insulating film 23 can be formed by a CVD process.

The advantages of the semiconductor device 1A and the process of forming the same will be described in comparison with the conventional semiconductor device shown in fig. 7. Fig. 7 is a plan view of a conventional semiconductor device 100. Fig. 8A to 8C are cross-sectional views of conventional apparatus 100 taken along lines VIIIa-VIIIa, VIIIb-VIIIb, and VIIIc-VIIIc, respectively, shown in fig. 7. Fig. 7 omits the insulating films 21 to 23.

The field plate is generally formed by evaporating a metal, for example, in vacuum to easily remove the residual metal accumulated on the photoresist, which makes it difficult for the metal for the field plate to cover the side of the gate electrode or the side of the step in the second insulating film 22 (which reflects the large thickness of the gate metal). The gate electrode needs to be formed thicker to reduce its gate resistance, while the field plate can be formed thin because no current flows therein and its resistance becomes negligible. Thus, the step resulting from the thickened gate electrode may lead to cracking of the field plate. The above-described cracking of the field plate may occur irregularly in the semiconductor device 1A.

Referring to fig. 7 and 8A to 8C, the conventional semiconductor device 100 does not have the extension portion 33a of the gate electrode 33; that is, only the field plate 34 extends outside the source electrode 32 and is connected thereto with the source interconnect 42. When the gate electrode 33, in particular the step originating from the thickened gate metal, may break in the gate metal between the part overlapping the gate metal and another part surrounding the gate metal but not overlapping the gate metal, the former part is not electrically connected to the source interconnect 42, which reduces the function of the field plate 34, i.e. shields the gate electrode 33 from the drain electrode 31 and mitigates the field strength formed by the gate electrode 33. In addition, the rupture of the field plate 34 may change the parasitic capacitance between the gate electrode 33 and the source electrode 32.

The semiconductor device 1A according to the present embodiment extends the gate electrode 33 to the outside of the source electrode 32 to form the extension portion 33a therein, which means that not only the second portion 34b exists outside the source electrode 32 but also the first portion 34a exists outside the source electrode 32, and even when the first portion 34a and the second portion 34b are physically isolated by a break at a step in the second insulating layer 22 originating from the thickened gate electrode 33, the first portion 34a and the second portion 34b can be electrically connected with the source interconnect 42. Accordingly, the field plate 34 can be stably connected to the source electrode 32 and stabilize its potential. As the conventional semiconductor device 100, the second portion 34b of the field plate 34 may also be stably connected with the source electrode 32.

The field plate 34 outside the source electrode 32 may preferably have a width W2 in the longitudinal direction of the electrodes 31 to 33 that is greater than the width W1 in the lateral direction of the electrodes 31 to 33, which enables an electrical connection to be made between the field plate 34 and the source interconnect 42. Since the extension portion 33a of the gate electrode 33 exists in the inactive region A2 of the semiconductor device 1A, the performance of the semiconductor device 1A, specifically, the current-voltage performance around the gate electrode 33 may not be affected.

Although specific embodiments of the application have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. For example, the above-described embodiments focus on a semiconductor device type HEMT made mainly of a nitride semiconductor material, and the present application can be applied to other types of semiconductor devices and made of materials other than nitride semiconductor materials. Further, the embodiments focus on a semiconductor device having two gate electrodes and two field plates. However, the present application may be applied to devices having a single gate electrode with a single field plate, or to devices having three or more gate electrodes each with a corresponding field plate. It is therefore intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present application.

Claims

1. A semiconductor device, comprising:

a source electrode, a gate electrode, and a drain electrode each extending in a longitudinal direction;

an insulating film that covers at least the gate electrode and extends between the gate electrode and the drain electrode;

a field plate having a first portion overlapping the gate electrode with the insulating film interposed therebetween and a second portion not overlapping the gate electrode and extending on the insulating film between the gate electrode and the drain electrode; and

a source interconnect electrically connected to and extending from the source electrode,

wherein the first portion and the second portion are electrically connected to the source interconnect,

the semiconductor device further includes an active region in which the source electrode, the drain electrode, and the gate electrode are present,

wherein the gate electrode has an extension portion in an outer region of the source electrode in the inactive region, the extension portion being covered by the first portion of the field plate and surrounded by the second portion, the insulating film being interposed between the extension portion and the first portion of the field plate,

wherein the field plate is in contact with the source interconnect in the outer region of the source electrode at the first and second portions thereof.

2. The semiconductor device according to claim 1,

wherein the first portion and the second portion of the field plate are physically isolated from each other.

3. The semiconductor device according to claim 1,

wherein the source electrode and the drain electrode have rectangular planar shapes along a longitudinal direction thereof,

wherein the width of the field plate in the longitudinal direction in the outer region of the source electrode is wider than the width in the transverse direction intersecting the longitudinal direction in the region between the source electrode and the drain electrode.

4. The semiconductor device according to any one of claim 1 to 3,

wherein the thickness of the gate electrode is 0.3 μm to 0.7 μm, and the thickness of the field plate is 0.1 μm to 0.3 μm.

5. The semiconductor device according to any one of claim 1 to 3,

wherein the thickness of the insulating film is 0.1 μm to 0.3 μm.

6. The semiconductor device according to any one of claim 1 to 3,

wherein the source interconnect has a thickness of 4 μm to 6 μm.