KR20150039481A - Power semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, provided is a power semiconductor device having an improved vertical breakdown voltage. According to the embodiment of the present invention, the power semiconductor device comprises: an insulation layer; a substrate arranged on the top of the insulation layer; an epitaxial layer arranged on the top of the substrate; a gate electrode arranged on the top of the epitaxial layer; and a source and a drain contact which pass through the epitaxial layer and are separately arranged from each other around a gate.

Description

[0001] Power semiconductor device [0002]

An embodiment relates to a power semiconductor device.

Gallium nitride (GaN) materials with broad energy bandgap characteristics are suitable for power semiconductor devices such as power switches, such as excellent forward characteristics, high breakdown voltage, and low intrinsic carrier density.

Schottky barrier diodes, metal semiconductor field effect transistors, and high electron mobility transistors (HEMTs) are known as power semiconductor devices.

Such a power semiconductor device has a problem that it can be destroyed when the breakdown voltage, in particular, the vertical breakdown voltage is low.

Embodiments provide a power semiconductor device having an improved vertical breakdown voltage.

The power semiconductor device of the embodiment includes: an insulating layer; A substrate disposed over the insulating layer; An epi layer disposed on the substrate; A gate electrode disposed on the epi layer; And source and drain contacts that are spaced apart from each other across the gate and through the epi layer.

The power semiconductor device may further include a passivation layer disposed over the epi layer, wherein the gate electrode, the source contact, and the drain contact may be disposed through the passivation layer.

The passivation layer and the insulating layer may comprise the same material.

The thickness of the passivation layer and the thickness of the insulating layer may be the same.

The insulating layer may have a thickness of 1 to 100 [mu] m.

The insulating layer may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, and SOD.

The substrate may comprise silicon, and the epi layer may comprise a nitride semiconductor.

The insulating layer may be formed by LPCVD.

The power semiconductor device may further include a gate insulating layer disposed between the gate electrode and the epi layer.

The power semiconductor device according to the embodiment may have a desired high vertical breakdown voltage due to the insulating layer disposed under the substrate even when the thickness of the transition layer is not thick enough to obtain a desired vertical breakdown voltage, An insulating layer may be formed during the formation of the passivation layer, so that a separate process for forming the insulating layer is not required and the manufacturing process may not be complicated.

1 is a cross-sectional view of a power semiconductor device according to an embodiment.
Figure 2 shows a cross-sectional view of an embodiment of the epi layer of Figure 1;
3A and 3B are graphs showing the vertical breakdown voltage.
4A to 4I are process cross-sectional views illustrating a method of manufacturing the power semiconductor device illustrated in FIG. 1 according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the embodiment according to the present invention, in the case of being described as being formed on the "upper" or "on or under" of each element, on or under includes both elements being directly contacted with each other or one or more other elements being indirectly formed between the two elements. Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

It is also to be understood that the terms "first" and "second", "upper" and "lower", etc., as used below, do not necessarily imply or imply any physical or logical relationship or order between such entities or elements And may be used only to distinguish one entity or element from another entity or element.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

1 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

The power semiconductor device 100 illustrated in Figure 1 includes an insulating layer 104, a substrate 110, an epi layer 120, a passivation layer 130, an intermediate dielectric layer 140, A pad 152, a drain pad 154, a source contact 160, a gate electrode 170, a drain contact 180, and a gate dielectric 190.

Referring to FIG. 1, a substrate 110 is disposed on an insulating layer 104. The insulating layer 104 serves to raise the vertical breakdown voltage of the power semiconductor device 100. If the first thickness t1 of the insulating layer 104 is less than 1 angstrom, the effect of increasing the vertical breakdown voltage is small. If the first thickness t1 of the insulating layer 104 is greater than 100 mu m, it may be difficult to grasp the power semiconductor element 100 to be mounted on the package body, and it may be difficult to arrange the wires (not shown) . Thus, the first thickness t1 of the insulating layer 104 may be between 1 A and 100 mu m.

In addition, the insulating layer 104 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

In addition, the insulating layer 104 may be formed by low pressure chemical vapor deposition (CVD) at a high temperature greater than 700 ° C as described later.

The substrate 110 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 110.

In addition, the substrate 110 can be defined by being divided into an isolation region (IA) and an active region (AA). The active region AA of the substrate 110 is an area where the epi layer 120 is disposed and the element isolation region IA is an area that electrically isolates adjacent power semiconductor elements from each other.

On the other hand, an epi layer 120 is disposed on the substrate 110.

Figure 2 shows a cross-sectional view of an epi layer 120 of Figure 1, according to embodiment 120A.

1 and 2, an epi layer 120 disposed on a substrate 110 in an active region AA includes a transition layer 122, a first nitride semiconductor layer (or buffer layer) 124, And a nitride semiconductor layer (or barrier layer) 126. Thus, the epi layer 120 may include a nitride semiconductor.

The first nitride semiconductor layer 124 is disposed on the substrate 110. The first nitride semiconductor layer 124 may be an undoped semiconductor layer. The first nitride semiconductor layer 124 may be formed of a semiconductor compound. 3-group-5 or group-6-group compound semiconductors. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The first nitride semiconductor layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP. Do not.

The channel layer 124A may be formed on top of the first nitride semiconductor layer 124 adjacent to the second nitride semiconductor layer 126. That is, the channel layer 124A is disposed on the first nitride semiconductor layer 124 below the interface between the second nitride semiconductor layer 126 and the first nitride semiconductor layer 124. [

In addition, a transition layer 122 may be further disposed between the substrate 110 and the first nitride semiconductor layer 124. The transition layer 122 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and the like, but the embodiment is not limited thereto and the transition layer 122 may be omitted.

The second nitride semiconductor layer 126 is disposed on the first nitride semiconductor layer 124. The second nitride semiconductor layer 126 is a layer disposed to help form the channel layer 124A, and serves to bend the band gap energy. The second nitride semiconductor layer 126 has a larger band width than the channel layer 124A and can have a uniform polarization density over the entire layer and the second nitride semiconductor layer 126 and the first nitride semiconductor layer 124 Dimensional electron gas (2DEG) may be generated in the channel layer 124A by heterogeneous bonding having different band gap energy of the channel layer 124A.

For example, the second nitride semiconductor layer 126 may be formed of a compound semiconductor such as a group III-V element or a group II-VI element. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The second nitride semiconductor layer 126 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

The thickness of the second nitride semiconductor layer 126 may be 20 nm or less, but the embodiment is not limited to the thickness of the second nitride semiconductor layer 126.

On the other hand, the passivation layer 130 is disposed on the epi layer 120 of the active region AA, but the embodiment is not limited to the arrangement structure of such a passivation layer 130. The passivation layer 130 is formed by etching the epitaxial layer 120 in the process of forming the gate electrode 170, the source contact 160, and the drain contact 180 by a metal etching method, (Or protecting) the user.

If the second thickness t2 of the passivation layer 130 is less than 100 ANGSTROM it may not be sufficient to protect the epi layer 120 from etching and the second thickness t2 of the passivation layer 130 may be less than If it is greater than 2000 Å, the field plate may not be able to perform properly. Thus, the second thickness t2 of the passivation layer 130 may be between 100 A and 2000 A, although embodiments are not limited in this regard.

The above-described passivation layer 130 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD, and may be formed by various methods.

According to the embodiment, the insulating layer 104 and the passivation layer 130 may include the same material or may be formed of different materials.

The first thickness t1 of the insulating layer 104 and the second thickness t2 of the passivation layer 130 may be the same or different from each other.

Meanwhile, the gate electrode 170 is disposed on the epi-layer 120 through the passivation layer 130. The gate electrode 170 may comprise a metallic material. For example, the gate electrode 170 may be a refractory metal or a mixture of such refractory metals. Alternatively, the gate electrode 170 may comprise at least one of Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten) or WSi ₂ (Tungstem silicide) have.

A gate insulating layer 190 is disposed between the gate electrode 170 and the epi layer 120 and between the gate electrode 170 and the passivation layer 130 as illustrated in FIG. 1, a gate insulating layer 190 is disposed between the intermediate dielectric layer 140 and the passivation layer 130 in the active region AA and an intermediate dielectric layer 140 in the device isolation region IA. And the substrate 110, but the embodiment is not limited to this. That is, the gate insulating layer 190 disposed between the intermediate dielectric layer 140 and the substrate 110 in the element isolation region IA may be omitted. The gate insulating layer 190 disposed between the intermediate dielectric layer 140 and the passivation layer 130 in the vicinity of the gate electrode 170 in the active area AA may also be omitted.

The gate insulating layer 170 is formed of Al ₂ O ₃ A silicon oxide layer such as SiO ₂ , or a silicon nitride layer, and may have a thickness of, for example, 100 Å to 300 Å, but the embodiments are not limited thereto.

Source contact and drain contacts 160 and 180 are in contact with the epi layer 120 through the passivation layer 130 and the gate insulating layer 190 and are spaced apart from each other with the gate electrode 170 therebetween. In other words, the source contact and drain contacts 160 and 180 are spaced apart from the gate electrode 170. Each of the source and drain contacts 160 and 180 may be formed of a metal. In addition, the source and drain contacts 160 and 180 may comprise the same material as the gate electrode 170 material. Further, the source and drain contacts 160 and 180 may be formed of a reflective electrode material having an ohmic characteristic. For example, each of the source and drain contacts 160 and 180 includes at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu) Layer structure or a multi-layer structure.

BACKGROUND ART Generally, as a method for suppressing a leakage current of a GaN-based power semiconductor device, a floating gate, a field-modulating plate, an overlapping gate structure, a source extension field plate extended field palettes, and multiple field plates are being developed. For example, a field plate (not shown) is disposed to alleviate the electric field concentration at the edge of the gate electrode 170.

However, in the case of the power semiconductor device shown in FIG. 1, since the wing portions 172 and 174 of the gate electrode 170 serve as a field plate, it is not necessary to form a separate field plate. Thus, the wing portions 172 and 174 of the gate electrode 170 serve as the field plates, so that the concentration of the electric field can be relaxed and the breakdown voltage of the power semiconductor element 100 can be improved. That is, the electric field concentrated on the edge of the penetrating portion 176 can be dispersed by the wing portions 172 and 174.

The intermediate dielectric layer 140 is disposed on the gate insulating layer 190 while covering the gate electrode 170 and exposing the upper surfaces of the source contact 160 and the drain contact 180. The intermediate dielectric layer 140 may include, but is not limited to, the same material as the passivation layer 130. The intermediate dielectric layer 140 may comprise at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

The source and drain pads 152 and 154 are electrically connected to the source contact 160 and the drain contact 180 through the intermediate dielectric layer 140, respectively. The source and drain pads 152 and 154 may be formed by at least one of gold (Au), aluminum (Al), or copper (Cu) It is not limited.

Meanwhile, the power semiconductor device 100 may further include a lower metal layer 102. When the power semiconductor element 100 is bonded to a lead frame (not shown) by a solder (not shown), the lower metal layer 102 serves to improve the bonding force between the power semiconductor element 100 and the lead frame do. The lower metal layer 102 may have a single layer or a multi-layer structure. If the solder comprises silver (Ag), the bottom layer in the bottom metal layer 102 having a multi-layer structure may comprise Ag. Embodiments are not limited to the presence of such a bottom metal layer 102 or the structure and constituent materials of the bottom metal layer 102.

FIGS. 3A and 3B are graphs showing vertical breakdown voltages. FIG. 3A is a graph showing vertical breakdown voltages on a log scale, and FIG. 3B is a graph showing vertical breakdown voltages on a linear scale. In each graph, the horizontal axis represents the bias voltage and the vertical axis represents the current.

Generally, the horizontal breakdown voltage of the power semiconductor device 100 is determined by the distance between the gate electrode 170 and the drain contact 180. In addition, the vertical breakdown voltage is determined by the thickness of the transition layer 122 within the epi layer 120. However, due to the difference in lattice constant between the first nitride semiconductor layer 124 and the silicon substrate 110, it may be difficult to deposit the transition layer 122 thick enough to satisfy the vertical breakdown voltage. Thus, even if the horizontal breakdown voltage is ensured by sufficiently leaving a gap between the gate electrode 170 and the drain contact 180, if the thickness of the transition layer 122 is not thick enough to satisfy the desired vertical breakdown voltage, 100) may be destroyed.

However, according to an embodiment, the power semiconductor device 100 may have an insulating layer 104 under the substrate 110 so that even if the thickness of the transition layer 122 is not thick enough to obtain the desired vertical breakdown voltage , And can have the desired high vertical breakdown voltage.

Referring to FIGS. 3A and 3B, it can be seen that the vertical breakdown voltage is improved in the present embodiment (204, 214 (.circle-solid.)) Than in the conventional cases 202 and 212 (1).

Hereinafter, a method of manufacturing the power semiconductor device 100 illustrated in FIG. 1 will be described with reference to FIGS. 4A to 4I. However, the manufacturing method described below is merely one example, and it goes without saying that the power semiconductor element 100 illustrated in FIG. 1 may be manufactured by other methods.

4A to 4I are process cross-sectional views illustrating a method of manufacturing the power semiconductor device 100 illustrated in FIG. 1 according to an embodiment.

Referring to FIG. 4A, an epi layer 120 is formed on a substrate 110. The substrate 110 may be formed using silicon, silicon carbide, GaN, sapphire, or the like. The epitaxial layer 120A may be formed by sequentially laminating a transition layer 122, a first nitride semiconductor layer 124 and a second nitride semiconductor layer 126 on a substrate 110 as illustrated in FIG. 2 have.

The transition layer 122 may be formed using aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like.

The first nitride semiconductor layer 124 may be an undoped semiconductor layer. The first nitride semiconductor layer 124 may be formed of a semiconductor compound, and may be formed of a compound semiconductor such as a group III-V element or a group II-VI element. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) (124) can be formed. The first nitride semiconductor layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP. Do not.

The second nitride semiconductor layer 126 may be formed using a compound semiconductor such as a group III-V element or a group II-VI element. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) The second nitride semiconductor layer 126 can be formed of at least one of AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

Next, referring to FIG. 4B, a photoresist pattern 222 is formed on the epi-layer 120A, exposing the element isolation region IA and covering the active region AA.

4C, the epi-layer 120 is etched using the photoresist pattern 222 as an etch mask to expose the element isolation region IA of the substrate 110. Next, as shown in FIG. For example, etching of the epi layer 120 may utilize dry etching. Thereafter, the photoresist pattern 222 used as the etching mask is removed by ashing and / or strip.

Next, referring to FIG. 4D, a passivation layer 130 is formed on the epi layer 120. At the same time, the insulating layer 104 may be formed under the substrate 110, but the embodiment is not limited thereto. That is, the insulating layer 104 may be formed before or after the formation of the passivation layer 130. If the passivation layer 130 and the insulating layer 104 are formed at the same time, the first thickness t1 of the insulating layer 104 and the second thickness t2 of the passivation layer 130 may be equal to each other In addition, the constituent material of the insulating layer 104 and the constituent material of the passivation layer 130 may be the same. However, depending on the case, the first and second thicknesses t1 and t2 may be different from each other, and the constituent material of the insulating layer 104 and the constituent material of the passivation layer 130 may be different from each other.

The passivation layer 130 and the insulating layer 104 may be formed using a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a PECVD method, a LPCVD, a molecular beam epitaxy (MBE) , Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD), Hydride Vapor Phase Epitaxy (HVPE), and the like, but the present invention is not limited thereto.

As described above, when the insulating layer 104 is formed while the passivation layer 130 is formed, a separate process for forming the insulating layer 104 is not required. Therefore, even if the power semiconductor element 100 includes the insulating layer 104, the manufacturing process of the power semiconductor element 100 is not complicated.

4E, the passivation layer 130 is patterned using conventional photolithography (e.g., photolithography) to expose the portion 223 where the gate insulating layer 190 is to be embedded and the penetration portion 176 of the gate electrode 170 is to be formed photolithography) process.

4F, a gate insulating layer 190 is formed on the passivation layer 130 and the element isolation region IA of the substrate 110 including the exposed portion 223 of the epi layer 120 . The gate insulating layer 190 may be formed to a thickness of, for example, 15 nm by an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, or the like, but the embodiment is not limited thereto. For example, the gate insulating layer 190 may be formed of aluminum oxide (Al ₂ O ₃ ) by atomic layer deposition.

4G, a passivation layer 130 and a gate insulating layer 190 are formed to expose the epi layer 120 of the portions 224 and 226 where the source contact and drain contacts 160 and 180 are to be formed. Is etched by a photolithography process.

Next, referring to FIG. 4H, a metal layer (not shown) is formed on the exposed portions 224 and 226 of the epi layer 120 and the top surface of the gate insulating layer 190. The metal layer may be formed using e-beam evaporation or a metal sputter. When the metal layer is formed on the gate insulating layer 190 by the metal sputtering, the metal layer can be buried better than in the electron beam evaporation method. After the metal layer is buried, a subsequent heat treatment can be performed. For example, rapid thermal annealing may be performed at 400 캜 for 10 minutes.

Subsequently, a photoresist pattern covering only the portion where the source contact 160, the gate electrode 170, and the drain contact 180 are to be formed and exposing another portion is formed on the metal layer, and then, using the photoresist pattern as an etching mask The metal layer is etched back and etched. At this time, the gate insulating layer 190 may be etched together or may remain. Since the passivation layer 130 is etched instead of the epi layer 120 after the gate insulating layer 190 is etched while the metal layer is etched using the photoresist pattern as an etch mask, Can be protected from etching. Thus, the passivation layer 130 serves to protect the epi layer 120 from the etching of the gate electrode 170 and the metal layer to form the source and drain contacts 160 and 180.

If the second thickness t2 of the passivation layer 130 is less than 100 angstroms, the epilayers 120 may be etched while the metal layer is etched. If the second thickness t2 is greater than 2000 angstroms, The wings 172 and 174 may not be able to disperse the electric field induced at the corners of the wafer 170. Accordingly, the second thickness t2 of the passivation layer 130 may be between 100 A and 2000 A.

Next, by removing the photoresist pattern used for etching the metal layer, the gate electrode 170, the source contact 160, and the drain contact 180 are completed as illustrated in FIG. 4H.

Next, referring to FIG. 4I, an intermediate dielectric layer 140 exposing the top of the region to be contacted with the source and drain contacts 160 and 180 and the source and drain pads 152 and 154, respectively, and covering the gate electrode 170 . The intermediate dielectric layer 140 may be formed of the same material as the passivation layer 130, but the embodiment is not limited thereto.

Referring now to FIG. 1, source and drain pads 152 and 154 are formed that respectively contact the source contact 160 and the drain contact 180. While the bottom metal layer 102 may be formed at the same time while the source and drain pads 152, 154 are formed, the embodiment is not limited to this. That is, the bottom metal layer 102 may be formed after the source and drain pads 152, 154 are formed.

Although the photolithography process has been described as an example of the etching process in the above-described embodiments, the present invention is not limited thereto. It is needless to say that the etching process can also be performed by the e-bem lithography method or the nano-imprinted lithography method.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100: power semiconductor element 102: lower metal layer
104: insulating layer 110:
120: epi layer 122: transition layer
124: first nitride semiconductor layer 126: second nitride semiconductor layer
130: passivation layer 140: intermediate dielectric layer
152: source pad 154: drain pad
160: source contact 170: gate electrode
180: drain contact 190: gate insulating layer

Claims (9)

Insulating layer;
A substrate disposed over the insulating layer;
An epi layer disposed on the substrate;
A gate electrode disposed on the epi layer; And
And source and drain contacts spaced from each other across the gate and across the epi layer. 2. The device of claim 1, further comprising a passivation layer disposed over the epilayer,
Wherein the gate electrode, the source contact, and the drain contact are disposed through the passivation layer. 3. The power semiconductor device of claim 2, wherein the passivation layer and the insulating layer comprise the same material. The power semiconductor device according to claim 2, wherein the thickness of the passivation layer and the thickness of the insulating layer are the same. The power semiconductor device according to claim 1, wherein the insulating layer has a thickness of 1 to 100 mu m. The power semiconductor device according to claim 1, wherein the insulating layer comprises at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD. 2. The power semiconductor device of claim 1, wherein the substrate comprises silicon and the epilayer comprises a nitride semiconductor. The power semiconductor device according to claim 1 or 3, wherein the insulating layer is formed by LPCVD. The power semiconductor device of claim 1, further comprising a gate insulating layer disposed between the gate electrode and the epi layer.

Images