CN118266084A - Nitride-based semiconductor device and method of manufacturing the same - Google Patents

Abstract

The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, source and drain electrodes, a doped nitride-based semiconductor layer, first and second gate electrodes, and a third gate electrode. The source electrode and the drain electrode are disposed over the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor and between the source electrode and the drain electrode. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The third gate electrode is disposed over the first gate electrode and the second gate electrode and is in contact with a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode.

Description

Nitride-based semiconductor device and method of manufacturing the same

Technical Field

The present disclosure relates generally to a nitride-based semiconductor device. More particularly, the present disclosure relates to nitride-based semiconductor devices having auxiliary gate electrodes.

Background

In recent years, serious research into High Electron Mobility Transistors (HEMTs) has been widespread, particularly in high power switches and high frequency applications. The group III nitride based HEMT utilizes a heterojunction interface between two materials with different band gaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region, meeting the requirements of high power/frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs), and modulation doped FETs (MODFETs) in addition to HEMTs.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, source and drain electrodes, a doped nitride-based semiconductor layer, first and second gate electrodes, and a third gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and a band gap of the second nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed over the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor and between the source electrode and the drain electrode. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The third gate electrode is disposed over the first gate electrode and the second gate electrode and is in contact with a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode.

According to an aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has the following steps. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A doped nitride-based semiconductor layer is formed over the second nitride-based semiconductor layer. A first gate electrode and a second gate electrode are formed over the doped nitride-based semiconductor layer. A protective layer is formed to cover the first gate electrode and the second gate electrode. A source electrode and a drain electrode are formed in the protective layer to be in contact with the second nitride-based semiconductor layer. A portion of the protective layer is formed to expose the first gate electrode and the second gate electrode and to expose a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode. A third gate electrode is formed in contact with the first gate electrode and the second gate electrode and with the exposed portion of the doped nitride-based semiconductor layer.

According to an aspect of the present disclosure, there is provided a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, first and second gate electrodes, a protective layer, and a third gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and a band gap of the second nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The protective layer covers a top surface of the second nitride-based semiconductor layer, a top surface of the doped nitride-based semiconductor layer, and a top surface of the first gate electrode and a top surface of the second gate electrode. The third gate electrode is disposed over the first gate electrode and the second gate electrode, and extends from the top surface of the protective layer to a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode.

With the above configuration, the structure of the present disclosure uses a gate-first electrode (gate-last electrode) in combination with a gate-last electrode (gate-last electrode), thereby improving defects as compared with using only a gate-first electrode or only a gate-last electrode.

Drawings

Aspects of the disclosure are readily understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Embodiments of the present disclosure are described in more detail below with reference to the attached drawing figures, wherein:

fig. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

Fig. 2A, 2B, 2C, and 2D illustrate different stages of a method for fabricating a nitride-based semiconductor device according to some embodiments of the present disclosure;

fig. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

Fig. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to designate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions of a plane, such as "on … …," "above … …," "below … …," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above … …," "below … …," etc., with respect to a component or a group of components are specified with respect to the orientation of the component(s) shown in the associated figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that the actual implementation of the structures described herein may be spatially arranged in any orientation or manner without departing from the advantages of the embodiments of the present disclosure due to such arrangement.

Further, it should be noted that, due to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, have rounded edges, have slightly uneven thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.

In the following description, a semiconductor device/die/package, a manufacturing method thereof, and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, can be made without departing from the scope and spirit of the disclosure. Specific details may be omitted to avoid obscuring the disclosure; however, the present disclosure is written to enable any person skilled in the art to practice the teachings herein without undue experimentation.

Fig. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, electrodes 20 and 22, a doped nitride-based semiconductor layer 30, gate electrodes 32, 34, 36, passivation layers 40 and 42, a contact via 50, and a patterned conductive layer 52.

The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, for example, but are not limited to Si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)), or other suitable substrate materials. In some embodiments, the substrate 10 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 may be configured to reduce lattice mismatch and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 14, thereby solving defects due to mismatch/difference. Buffer layer 12 may include a III-V compound. The III-V compounds may include, for example, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for buffer layer 12 may also include, for example, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the substrate 10 and the group III nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, for example, but are not limited to, alN or any alloy thereof.

The nitride-based semiconductor layer 14 may be disposed on/over (above) the buffer layer 12. The nitride-based semiconductor layer 16 may be disposed on/over/on the nitride-based semiconductor layer 14. Exemplary materials for nitride-based semiconductor layer 14 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _xAl_yGa_(1–x–y) N (where x+y.ltoreq.1), al _xGa_(1–x) N (where x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 16 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _xAl_yGa_(1–x–y) N (where x+y.ltoreq.1), al _yGa_(1–y) N (where y.ltoreq.1).

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the bandgap of the nitride-based semiconductor layer 16 (i.e., the forbidden bandwidth) is greater than/higher than the bandgap of the nitride-based semiconductor layer 14, which results in their electron affinities being different from each other and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 14 is an undoped GaN layer having a band gap of about 3.4eV, nitride-based semiconductor layer 16 may be selected as an AlGaN layer having a band gap of about 4.0 eV. In this way, the nitride-based semiconductor layers 14 and 16 may function as a channel layer and a barrier layer, respectively. A triangle trap potential is generated at a junction interface between the channel layer and the barrier layer such that electrons accumulate in the triangle trap, thereby generating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A may include at least one GaN-based High Electron Mobility Transistor (HEMT).

Electrodes 20 and 22 are disposed on nitride-based semiconductor layer 16. The electrode 20 may be in contact with the nitride-based semiconductor layer 16. The electrode 22 may be in contact with the nitride-based semiconductor layer 16. Both electrodes 20 and 22 may be used as source or drain electrodes.

In some embodiments, electrodes 20 and 22 may include, for example, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds (e.g., silicides and nitrides), other conductor materials, or combinations thereof. Exemplary materials for electrodes 20 and 22 may include, for example, but are not limited to Ti, alSi, tiN or combinations thereof. The electrodes 20 and 22 may be a single layer or may be multiple layers having the same or different compositions. In some embodiments, electrodes 20 and 22 form ohmic contacts with nitride-based semiconductor layer 16. Ohmic contact may be achieved by applying Ti, al, or other suitable materials to the electrodes 20 and 22.

In some embodiments, each of electrodes 20 and 22 is formed of at least one conformal layer(s) and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer are, for example, but not limited to Ti, ta, tiN, al, au, alSi, ni, pt or combinations thereof. Exemplary materials for the conductive filler may include, for example, but are not limited to AlSi, alCu, or combinations thereof.

The doped nitride-based semiconductor layer 30 is disposed over the nitride-based semiconductor layer 30. Doped nitride-based semiconductor layer 30 is located between electrodes 20 and 22. The doped nitride-based semiconductor layer 30 may be p-type. The doped nitride-based semiconductor layer 30 is configured to put the device into an enhancement mode. The doped nitride-based semiconductor layer 30 may be a p-type doped III-V semiconductor layer.

Exemplary materials for doped nitride-based semiconductor layer 30 may include, for example, but are not limited to, p-doped group III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is implemented using p-type impurities such as Be, mg, zn, cd and Mg.

Gate electrodes 32 and 34 are disposed on the doped nitride-based semiconductor layer 30. The gate electrodes 32 and 34 are spaced apart from each other. The width of the doped nitride-based semiconductor layer 30 is greater than the distance from the gate electrode 32 to the gate electrode 34.

Gate electrodes 32 and 34 may be used as prior gate electrodes. For example, gate electrodes 32 and 34 may be formed prior to the formation of electrodes 20 and 22. Gate electrodes 32 and 34 may be used as etch marks for the back gate opening.

Exemplary materials for electrodes 32 and 34 may include metals or metal compounds. The electrodes 32 and 34 may be formed as a single layer, or may be formed as a plurality of layers having the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds. In some embodiments, gate electrodes 32 and 34 are formed by patterning the same conductive layer, so gate electrodes 32 and 34 have the same material.

A gate electrode 36 is disposed over the doped nitride-based semiconductor layer 30. A gate electrode 36 is disposed over electrodes 32 and 34. The gate electrode 36 may be in contact with a portion of the doped nitride-based semiconductor layer 30 between the gate electrodes 32 and 34.

Gate electrode 36 may extend along the boundaries of gate electrodes 32 and 34 to form a stepped profile. For example, the gate electrode 32 has a top surface and a side surface connected to each other to form a corner. In some embodiments, the corner has a right angle. The gate electrode 36 may extend along the top and side surfaces of the gate electrode 32 to cover the corners.

The gate electrode 36 may be used as a back gate electrode. For example, gate electrode 36 may be formed after formation of electrodes 20 and 22. The width of gate electrode 36 is greater than the distance from gate electrode 32 to gate electrode 34.

Typically, the gate electrode is a single layer in contact with the p-doped GaN layer, the work function difference of which will be reduced due to the annealing process for improving the ohmic contact of the source and drain electrodes. The reduced work function difference thus makes the breakdown voltage smaller. Alternatively, for a structure to which the back gate electrode is applied, the back gate electrode is formed after a removal process of a dielectric layer covering the p-doped GaN layer. During the removal process, the p-doped GaN layer is damaged once the dislocation etch occurs.

The structure in the exemplary illustration of fig. 1 uses a gate-first electrode in combination with a gate-last electrode, as compared to either the gate-first electrode or the gate-last electrode, to ameliorate the aforementioned drawbacks.

The gate electrodes 32 and 34 are islands on the doped nitride-based semiconductor layer 30, rather than a layer that occupies a majority of the area of the doped nitride-based semiconductor layer 30, and thus these islands may serve as alignment symbols during the gate opening of the gate electrode 36. Further, since the area of such islands is smaller than that of a single layer, the influence of the gate electrodes 32 and 34 on the doped nitride-based semiconductor layer 30, such as element diffusion, can be reduced.

Exemplary materials for electrode 36 may include metals or metal compounds. The electrode 36 may be formed as a single layer, or may be formed as a plurality of layers having the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds. In some embodiments, gate electrode 36 has at least one material that is different from the material of gate electrodes 32 and 34.

A passivation layer 40 is disposed over the nitride-based semiconductor layer 16. The passivation layer 40 may cover the doped nitride-based semiconductor layer and the gate electrodes 32 and 34. The passivation layer 40 may be formed for protection purposes, and thus the passivation layer 40 may also be referred to as a protective layer.

The passivation layer 40 is formed after the gate electrodes 32 and 34 are formed, and thus the passivation layer 40 may further cover the top surfaces of the gate electrodes 32, 34. The gate electrodes 32 and 34 have side surfaces opposite to each other and are covered with a passivation layer 40. Passivation layer 40 has sidewalls extending upward from the top surfaces of gate electrodes 32 and 34.

Since gate electrodes 32 and 34 may be used as alignment symbols during the gate opening of gate electrode 36, the gate opening may be aligned with gate electrodes 32 and 34. In this way, the inner sidewalls of the passivation layer are inclined with respect to the top surfaces of the gate electrodes 32 and 34.

The gate electrode 36 is formed after the passivation layer 40 is formed, and thus the gate electrode 36 may extend horizontally along the top surface of the passivation layer 40. The gate electrode 36 penetrates the passivation layer 40. More specifically, the gate electrode 36 may extend from a portion of the doped nitride-based semiconductor layer 30 to a top surface of the passivation layer 40, wherein the portion of the doped nitride-based semiconductor layer 30 is located between the gate electrodes 32 and 34. The gate electrode 36 contacts the sidewall of the passivation layer 40.

The electrodes 20 and 22 are formed after the passivation layer 40 is formed, and thus the electrodes 20 and 22 may penetrate the passivation layer 40 to be in contact with the nitride-based semiconductor layer 16.

Passivation layer 42 covers electrodes 20 and 22 and gate electrode 36. In some embodiments, passivation layer 42 may function as a planarization layer having a planar top surface that supports other layers/elements. In some embodiments, passivation layer 42 may be formed as a thicker layer and passivation layer 42 is subjected to a planarization process, such as a Chemical Mechanical Polishing (CMP) process, to remove excess portions, thereby forming a planar top surface. The material of passivation layer 42 may include, for example, but is not limited to, a dielectric material. For example, the passivation layer 140 may include SiN _x、SiO_x, siON, siC, siBN, siCBN, an oxide, a nitride, a Plasma Enhanced Oxide (PEOX), or a combination thereof.

Contact via 50 is disposed within passivation layer 42. The contact via 50 may penetrate the passivation layer 42. Contact via 50 may extend longitudinally to connect to electrodes 20 and 22 and gate electrode 36. The upper surface of the contact via 50 is not covered by the passivation layer 42. Exemplary materials for contact via 50 may include, for example, but are not limited to, conductive materials, such as metals or alloys.

Patterned conductive layer 52 is disposed on/over passivation layer 140 and contact via 50. The patterned conductive layer 52 is in contact with the contact via 50. Patterned conductive layer 52 may have metal lines, pads, traces, or a combination thereof, such that patterned conductive layer 52 is capable of forming at least one circuit. Thus, patterned conductive layer 52 may be used as a patterned circuit layer. Patterned conductive layer 52 may be connected to electrodes 20 and 22 and gate electrode 36 through contact via 50. The external electronic device may send at least one electronic signal to the semiconductor device 1A and vice versa through the patterned conductive layer 52. Exemplary materials for patterned conductive layer 52 may include, for example, but are not limited to, conductive materials. Patterned conductive layer 52 may comprise a single film or a multilayer film having Ag, al, cu, mo, ni, ti, an alloy thereof, an oxide thereof, a nitride thereof, or a combination thereof.

Different stages of the method for manufacturing the semiconductor device 1A are shown in fig. 2A, 2B, 2C and 2D described below. Hereinafter, deposition techniques may include, for example, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to fig. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/on the substrate 10. A nitride-based semiconductor layer 14 is formed on the buffer layer 12. A nitride-based semiconductor layer 16 is formed on the nitride-based semiconductor layer 14. A doped nitride-based semiconductor layer 30 is formed on/over/on the nitride-based semiconductor layer 16. Gate electrodes 32 and 34 are formed over the doped nitride-based semiconductor layer 30. In some embodiments, gate electrodes 32 and 34 may be formed from a single blanket conductive layer. A single blanket conductive layer may be patterned to obtain gate electrodes 32 and 34.

Referring to fig. 2B, a passivation layer 40 may be formed over the nitride-based semiconductor layer 16. The passivation layer 40 may cover the doped nitride-based semiconductor layer 30 and the gate electrodes 32 and 34.

Referring to fig. 2C, electrodes 20 and 22 are formed within the protective layer 40 to be in contact with the nitride-based semiconductor layer 16. Forming the electrodes 20 and 22 includes performing an annealing process to improve ohmic contacts between the electrode 20 and the nitride-based semiconductor layer 16 and between the electrode 22 and the nitride-based semiconductor layer 16. The annealing process may be performed under high temperature conditions. The gate electrodes 30 and 32 are completely covered by the passivation layer 40 at least until the electrodes 20 and 22 are formed. Since the gate electrodes 30 and 32 serve as islands rather than a single layer having a larger area, the influence of the gate electrodes 30, 32 on the doped nitride-based semiconductor layer 30, such as element diffusion, can be reduced.

Referring to fig. 2D, a portion of passivation layer 40 between gate electrodes 32 and 34 is removed. In this way, a portion of the doped nitride-based semiconductor layer 30 between the gate electrodes 30 and 32 is exposed. A portion of gate electrodes 32 and 34 are exposed. In some embodiments, removing portions of passivation layer 40 is performed by using an ion etching process. During the ion etching process, the gate electrodes 32 and 34 may be used as alignment marks, and thus the target portion of the passivation layer 40 to be removed may be removed more accurately.

Thereafter, gate electrodes may be formed to contact the gate electrodes 32 and 34 and the exposed portions of the doped nitride-based semiconductor layer 30, thereby completing post gate formation. Then, a passivation layer, a contact via and a patterned conductive layer are formed to obtain the structure as described above.

Fig. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the semiconductor device 1A described and illustrated with reference to fig. 1, except that the gate electrodes 32 and 34 of the semiconductor device 1A are replaced with gate electrodes 32B and 34B. The gate electrode 32B has a side surface inclined with respect to the top surface of the doped nitride-based semiconductor layer 30. The gate electrode 34B has a side surface inclined with respect to the top surface of the doped nitride-based semiconductor layer 30.

Fig. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the semiconductor device 1A described and illustrated with reference to fig. 1, except that the gate electrodes 32, 34, 36 of the semiconductor device 1A are replaced with gate electrodes 32C, 34C, 36C. The gate electrode 32 has a side surface inclined with respect to the top surface of the doped nitride-based semiconductor layer 30. The gate electrode 34B has a side surface inclined with respect to the top surface of the doped nitride-based semiconductor layer 30.

The doped nitride-based semiconductor layer 30 has sidewalls (i.e., left and right sidewalls) opposite to each other. The distance from the left sidewall to the gate electrode 32C is different from the distance from the right sidewall to the gate electrode 36B. This configuration relates to the operation of the semiconductor device 1A when a high voltage is applied to the drain. The gate-drain side faces a high electric field and thus the distance difference may improve the problem. In addition, potential leakage current on the gate-drain side can also be reduced.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications as are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "generally," "substantially," "about," and "about" are used to describe and consider small variations. When used in connection with an event or circumstance, the terms can include instances where the event or circumstance occurs accurately and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a range of less than or equal to ±10% of the numerical value, such as a range of less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces within a few microns that are positioned along a same plane, such as two surfaces within 40 microns, within 30 microns, within 20 microns, within 10 microns, or within 1 micron that are positioned along a same plane.

As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, an element disposed "on" or "over" another element may encompass the situation in which the former element is directly on (e.g., in physical contact with) the latter element, as well as the situation in which one or more intervening elements are located between the former element and the latter element.

While the present disclosure has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn necessarily to scale. There may be differences between the technical reproductions and the actual equipment in the present disclosure due to manufacturing processes and tolerances. Furthermore, it should be appreciated that the actual devices and layers may deviate from the rectangular layer depiction in the figures due to fabrication processes such as conformal deposition, etching, etc., and may include angled surfaces or edges, rounded corners, etc. Other embodiments of the present disclosure not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation.

Claims (25)

1. A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer, and having a band gap greater than that of the first nitride-based semiconductor layer;

A source electrode and a drain electrode disposed over the second nitride-based semiconductor layer;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode;

A first gate electrode and a second gate electrode disposed on the doped nitride-based semiconductor layer and spaced apart from each other; and

And a third gate electrode disposed over the first gate electrode and the second gate electrode and in contact with a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode.

2. A nitride-based semiconductor device as claimed in any one of the preceding claims, wherein the third gate electrode extends along a top surface and side surfaces of the first gate electrode.

3. The nitride-based semiconductor device of any one of the preceding claims, wherein the top surface and the side surface of the first gate electrode are connected to form a corner.

4. The nitride-based semiconductor device of any one of the preceding claims, wherein the side surface of the first gate electrode is inclined with respect to a top surface of the doped nitride-based semiconductor layer.

5. The nitride-based semiconductor device of any one of the preceding claims, further comprising:

And a protective layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer, wherein the protective layer also covers a top surface of the first gate electrode and a top surface of the second gate electrode.

6. The nitride-based semiconductor device of any one of the preceding claims, wherein the protective layer has sidewalls extending upward from a top surface of the first gate electrode.

7. The nitride-based semiconductor device of any one of the preceding claims, wherein the sidewalls of the protective layer are inclined with respect to a top surface of the first gate electrode.

8. A nitride-based semiconductor device according to any one of the preceding claims, wherein the third gate electrode is in contact with the sidewall of the protective layer.

9. The nitride-based semiconductor device of any one of the preceding claims, wherein the doped nitride-based semiconductor layer has a first sidewall and a second sidewall opposite each other, and a distance from the first sidewall to the first gate electrode is different from a distance from the second sidewall to the second gate electrode.

10. The nitride-based semiconductor device of any one of the preceding claims, wherein a width of the third gate electrode is greater than a distance from the first gate electrode to the second gate electrode.

11. The nitride-based semiconductor device of any one of the preceding claims, wherein a width of the doped nitride-based semiconductor layer is greater than a distance from the first gate electrode to the second gate electrode.

12. A nitride-based semiconductor device according to any one of the preceding claims, wherein the first and second gate electrodes have the same material.

13. A nitride-based semiconductor device according to any one of the preceding claims, wherein the third gate electrode has at least one material different from the material of the first gate electrode and the material of the second gate electrode.

14. The nitride-based semiconductor device of any one of the preceding claims, further comprising:

And a protective layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer, wherein the third gate electrode extends horizontally along a top surface of the protective layer.

15. A nitride-based semiconductor device according to any one of the preceding claims, wherein the source and drain electrode layers penetrate the protective layer to be in contact with the second nitride-based semiconductor layer.

16. A method for fabricating a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

Forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a doped nitride-based semiconductor layer over the second nitride-based semiconductor layer;

Forming a first gate electrode and a second gate electrode over the doped nitride-based semiconductor layer;

Forming a protective layer covering the first gate electrode and the second gate electrode;

forming a source electrode and a drain electrode within the protective layer to be in contact with the second nitride-based semiconductor layer;

removing a portion of the protective layer to expose the first gate electrode and the second gate electrode and expose a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode; and

A third gate electrode is formed in contact with the first and second gate electrodes and with the exposed portion of the doped nitride-based semiconductor layer.

17. The method of any of the preceding claims, wherein forming the source electrode and the drain electrode comprises performing an annealing process to improve ohmic contacts between the source electrode and the second nitride-based semiconductor layer and between the drain electrode and the second nitride-based semiconductor layer.

18. The method of any preceding claim, wherein the first and second gate electrodes are completely covered by the protective layer at least until the source and drain electrodes are formed.

19. A method according to any preceding claim, wherein removing the portion of the protective layer is performed by using an ion etching process.

20. The method of any of the preceding claims, wherein the first gate electrode and the second gate electrode are formed from a single blanket conductive layer.

21. A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer, and having a band gap greater than that of the first nitride-based semiconductor layer;

A doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer;

A first gate electrode and a second gate electrode disposed on the doped nitride-based semiconductor layer and spaced apart from each other;

a protective layer covering a top surface of the second nitride-based semiconductor layer, a top surface of the doped nitride-based semiconductor layer, and a top surface of the first gate electrode and a top surface of the second gate electrode; and

And a third gate electrode disposed over the first gate electrode and the second gate electrode and extending from a top surface of the protective layer to a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode.

22. The nitride-based semiconductor device of any one of the preceding claims, wherein the first and second gate electrodes have side surfaces that are opposite each other and covered by the protective layer.

23. The nitride-based semiconductor device of any one of the preceding claims, wherein a width of the doped nitride-based semiconductor layer is greater than a distance from the first gate electrode to the second gate electrode.

24. A nitride-based semiconductor device according to any one of the preceding claims, wherein the third gate electrode extends horizontally along a top surface of the protective layer.

25. The nitride-based semiconductor device of any one of the preceding claims, further comprising:

and a source electrode and a drain electrode layer disposed over the second nitride-based semiconductor layer and penetrating the protective layer to be in contact with the second nitride-based semiconductor layer.