CN109686658B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109686658B CN109686658B CN201811526241.4A CN201811526241A CN109686658B CN 109686658 B CN109686658 B CN 109686658B CN 201811526241 A CN201811526241 A CN 201811526241A CN 109686658 B CN109686658 B CN 109686658B
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
Abstract
The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: sequentially arranging a first dielectric layer, a waveguide layer and a second dielectric layer on the surface of the first substrate to form a first structure to be bonded; forming a pre-detection structure comprising a second substrate and a second pre-detection layer arranged on the surface of the second substrate, wherein the second pre-detection layer comprises a first sub-structure layer and a second sub-structure layer which are sequentially overlapped along the direction far away from the second substrate or comprises a second sub-structure layer, and the growth temperature of the second sub-structure layer is higher than that of the first sub-structure layer; a third dielectric layer is arranged on the surface of the second substructure layer to form a second structure to be bonded, and the second dielectric layer and the third dielectric layer are made of the same material; bonding the first structure to be bonded and the second structure to be bonded to form a bonded structure; and removing at least the second substrate, and only remaining the second substructure layer in the pre-detection structure. The detector prepared by the manufacturing method has small dark current.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
In the prior art, germanium detectors are widely used in various fields, and in conventional germanium detectors, a germanium layer is grown directly on a substrate silicon layer, but silicon and germanium have a lattice mismatch of 4.2%, which makes germanium more susceptible to defects when grown on silicon, and the growth process of germanium generally comprises: firstly, low-temperature growth is carried out at 300-450 ℃, and then high-temperature growth is carried out at 600-1000 ℃. Due to the growth mode, defects generated during low-temperature growth are more, the dark current of the germanium detector is larger, and the performance of the detector is influenced.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor device and a method for fabricating the same, so as to solve the problem of large dark current of a germanium detector in the prior art.
In order to achieve the above object, according to an aspect of the present application, there is provided a semiconductor device, the above manufacturing method including: sequentially arranging a first dielectric layer, a waveguide layer and a second dielectric layer on the surface of a first substrate to form a first structure to be bonded; forming a pre-detection structure comprising a second substrate and a second pre-detection layer arranged on the surface of the second substrate, wherein the second pre-detection layer comprises a first sub-structure layer and a second sub-structure layer which are sequentially overlapped along the direction far away from the second substrate or comprises a second sub-structure layer, the growth temperature of the second sub-structure layer is higher than that of the first sub-structure layer, the growth temperature of the second sub-structure layer is 600-1000 ℃, and the second pre-detection layer comprises Ge and/or GeSi; arranging a third dielectric layer on the surface of the second substructure layer to form a second structure to be bonded, wherein the second dielectric layer and the third dielectric layer are made of the same material; bonding the first structure to be bonded and the second structure to be bonded to form a bonded structure, wherein in the bonded structure, the second dielectric layer and the third dielectric layer are arranged in a contact manner; and removing at least the second substrate to enable only the second substructure layer to remain in the pre-detection structure.
Further, the pre-probing structure is a GOI structure, and the GOI structure includes the second substrate, the insulating layer, and the second sub-structure layer, which are sequentially stacked.
Further, the process of forming the first structure to be bonded includes: sequentially arranging the first dielectric layer and the waveguide material layer on the surface of the first substrate; etching the waveguide material layer to form a waveguide layer including a plurality of grating portions arranged in sequence along a first direction, the first direction being perpendicular to the thickness direction of the first substrate; and arranging a second dielectric layer on the surface of the waveguide layer far away from the first dielectric layer.
Further, the material of the first dielectric layer is the same as the material of the second dielectric layer.
Further, after sequentially removing the second substrate and a portion of the second pre-detection layer, the method includes: etching the rest second pre-detection layer to expose part of the surface of the third medium layer to form a detection layer; performing ion implantation on a portion of the detection layer to form a P region and an N region in the detection layer, wherein an undoped I region is formed between the P region and the N region, the P region, the I region, and the N region are arranged in a second direction, the first direction is perpendicular to the second direction, and the second direction is perpendicular to a thickness direction of the first substrate; arranging a fourth dielectric layer on the surfaces of the exposed detection layer and the exposed third dielectric layer; forming two through holes in the fourth dielectric layer, wherein the two through holes are respectively abutted with the N region and the P region; filling a conductive material in each through hole to form a conductive plug; and providing contact electrodes on the surface of each conductive plug far away from the detection layer to form two contact electrodes.
Further, the first dielectric layer and the second dielectric layer are both silicon dioxide layers, the first substrate is a silicon layer, and the waveguide layer is made of Si and Si3N4And in SiONAt least one of them.
Further, the thickness of the second dielectric layer and/or the third dielectric layer is between 100nm and 2 μm.
According to another aspect of the present application, there is provided a semiconductor device fabricated by any one of the above-described fabrication methods.
According to still another aspect of the present application, there is provided a semiconductor device including: the waveguide layer is formed by sequentially stacking a first substrate, a first medium layer, a waveguide layer, a second medium layer and a third medium layer; the detection layer is positioned on the partial surface, far away from the second dielectric layer, of the third dielectric layer and comprises a P area, an I area and an N area which are sequentially arranged along a second direction, the second direction is vertical to the thickness direction of the first substrate, the growth temperature of the detection layer is 600-1000 ℃, and the detection layer comprises Ge and/or GeSi; a fourth dielectric layer located on the surfaces of the third dielectric layer and the detection layer far from the substrate, wherein the fourth dielectric layer has two through holes which are respectively abutted with the N region and the P region; the two conductive plugs are correspondingly positioned in the through holes one by one; and the two contact electrodes are correspondingly positioned on the surface of the conductive plug, which is far away from the detection layer.
Further, the waveguide layer includes a plurality of grating portions arranged in sequence in a first direction, and the first direction is perpendicular to a thickness direction of the first substrate.
By applying the technical scheme of the application, in the manufacturing method, the second pre-detection layer is arranged on the surface of the first substrate in a bonding mode, and in the bonded structure, the second sub-structure layer is arranged closer to the third dielectric layer than the second substrate, so that the second substrate and part of the structure in the second pre-detection layer can be removed subsequently, only the second sub-structure layer with higher growth temperature is reserved, and the second sub-structure layer has higher growth temperature, so that the layer has better quality and fewer defects, dark current in the finally prepared detector is smaller, and the performance of the detector is better. In addition, in the manufacturing method, the materials of the second dielectric layer and the third dielectric layer which are directly contacted during bonding are the same, so that the bonding strength is further ensured to be better, the defects in the structure formed after bonding are fewer, and the detector is further ensured to have better performance.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 to 11 show a manufacturing flow of a manufacturing method of a semiconductor device;
FIG. 12 shows a top view of FIG. 11;
fig. 13 shows a schematic structural view of another semiconductor device of the present application.
Wherein the figures include the following reference numerals:
10. a first substrate; 20. a first dielectric layer; 30. a waveguide layer; 300. a waveguide material layer; 31. a grating section; 40. a second dielectric layer; 50. a third dielectric layer; 60. a detection layer; 600. a second pre-detection layer; 61. an N region; 62. a region I; 63. a P region; 70. a fourth dielectric layer; 71. a through hole; 80. a conductive plug; 90. a contact electrode; 100. a fifth dielectric layer; 110. a barrier layer; 01. a first structure to be bonded; 02. a second structure to be bonded; 021. pre-probing the structure; 022. a second substrate; 023. an insulating layer; 03. and (5) bonding structure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the germanium detector in the prior art, defects generated when the germanium layer is directly arranged on the silicon substrate and the germanium layer grows at a low temperature are more, so that the dark current of the germanium detector is larger, and the performance of the detector is affected.
In an exemplary embodiment of the present application, there is provided a method of manufacturing a semiconductor device, the method including: sequentially arranging a first dielectric layer 20, a waveguide layer 30 and a second dielectric layer 40 on the surface of a first substrate 10 to form a first structure to be bonded 01, as shown in fig. 1; forming a pre-detection structure 021 comprising a second substrate 022 and a second pre-detection layer 60 arranged on the surface of the second substrate 022, wherein the second pre-detection layer 600 comprises a first substructure layer and a second substructure layer which are sequentially stacked along the direction far away from the second substrate 022 or the second pre-detection layer 600 comprises a second substructure layer, the growth temperature of the second substructure layer is higher than that of the first substructure layer, the growth temperature of the second substructure layer is between 600 and 800 ℃, and the second pre-detection layer 600 comprises Ge and/or GeSi; a third dielectric layer 50 is disposed on the surface of the second substructure layer to form a second structure to be bonded 02, as shown in fig. 2, wherein the second dielectric layer 40 and the third dielectric layer 50 are made of the same material; bonding the first structure to be bonded 01 and the second structure to be bonded 02, as shown in fig. 3, to form a bonded structure 03 in fig. 4, wherein in the bonded structure 03, the second dielectric layer 40 and the third dielectric layer 50 are disposed in contact; at least the second substrate 022 is removed, so that only the second sub-structure layer remains in the pre-probing structure 021, thereby forming the structure shown in fig. 5.
In the manufacturing method, the second pre-detection layer is arranged on the surface of the first substrate in a bonding mode, and in the bonded structure, the second sub-structure layer is arranged closer to the third dielectric layer than the second substrate, so that the second substrate and part of the structure in the second pre-detection layer can be removed subsequently, only the second sub-structure layer with higher growth temperature is reserved, and the second sub-structure layer has higher growth temperature, so that the layer has better quality and fewer defects, the dark current in the finally prepared detector is smaller, and the performance of the detector is better. In addition, in the manufacturing method, the materials of the second dielectric layer and the third dielectric layer which are directly contacted during bonding are the same, so that the bonding strength is further ensured to be better, the defects in the structure formed after bonding are fewer, and the detector is further ensured to have better performance.
It should be noted that, as can be seen from the above, the second pre-detection layer of the present application has at least two configurations, the first configuration is composed of a first sub-structure layer and a second sub-structure layer, and the second configuration is only the second sub-structure layer. For the first mode, because the growth temperature of the first substructure layer is lower than that of the second substructure layer, the defect removal in the first substructure layer is large, the quality is poor, after bonding, the manufacturing method sequentially removes the second substrate and the first substructure layer, and retains the second substructure layer. For the second mode, only the second substructure layer is included, and after bonding, only the second substrate can be removed or the second substrate and a part of the second substructure layer can be removed in sequence according to actual needs, and at least a part of the second substructure layer is reserved, so that the dark current of the detector is ensured to be small, and the detection performance is good.
In this case, the second pre-detection layer may include a first sub-structure layer and a second sub-structure layer that are sequentially disposed, and after bonding, the first sub-structure layer needs to be removed; in a specific embodiment of the present application, the pre-probing structure 021 is a GOI structure, and a process for manufacturing the GOI structure includes: forming a first substructure by providing an insulating layer 023 on a surface of the second substrate 022, the insulating layer being a silicon dioxide layer; sequentially arranging the first substructure layer and the second substructure layer on the surface of a third substrate, wherein the first substructure layer and the second substructure layer form a first pre-detection layer 60, and further form a second substructure; bonding the first substructure and the second substructure such that the second substructure layer is in contact with the insulating layer 023 to form a probing preliminary structure; at least the third substrate and the first substructure layer in the pre-detection structure are sequentially removed to form the GOI structure as shown in fig. 2, and the first pre-detection layer becomes the second pre-detection layer.
The utility model provides a waveguide layer can be the strip waveguide layer, also can be ridge waveguide layer, still can be for the waveguide layer that includes grating portion, in order to further improve optical coupling efficiency, and then improve the sensitivity of detector etc. in an embodiment of this application, the process that forms above-mentioned first structure of waiting to bond includes: sequentially disposing the first dielectric layer 20 and the waveguide material layer 300 on the surface of the first substrate 10; etching the waveguide material layer 300 to form a waveguide layer 30 including a plurality of grating portions 31 sequentially arranged in a first direction perpendicular to a thickness direction of the first substrate 10; a second dielectric layer 40 is disposed on the surface of the waveguide layer 30 remote from the first dielectric layer 20 to form the structure shown in fig. 1.
In order to further ensure that the detector has high sensitivity and high detection efficiency, in a specific embodiment of the present application, the material of the first dielectric layer is the same as the material of the second dielectric layer, so that light can propagate along a predetermined direction, and the coupling efficiency of light is further ensured.
In order to form a complete photodetector, in a specific embodiment of the present application, after sequentially removing the second substrate and a portion of the second pre-detection layer, the manufacturing method includes: etching the remaining second pre-detection layer 600 to expose a part of the surface of the third dielectric layer 50, thereby forming a detection layer 60 as shown in fig. 6; performing ion implantation on a portion of the probe layer 60 to form a P region 63 and an N region 61 in the probe layer 60, wherein an undoped I region 62 is disposed between the P region 63 and the N region 61, and the P region 63, the I region 62, and the N region 61 are arranged in a second direction, as shown in fig. 7, the first direction is perpendicular to the second direction, and the second direction is perpendicular to the thickness direction of the first substrate 10; providing a fourth dielectric layer 70 on the exposed surfaces of the detection layer 60 and the exposed surface of the third dielectric layer 50, as shown in fig. 8; forming two through holes 71 in the fourth dielectric layer 70, wherein the two through holes 71 are respectively in contact with the N region 61 and the P region 63, as shown in fig. 8; filling each of the through holes 71 with a conductive material to form a conductive plug 80 as shown in fig. 9; a contact electrode 90 is provided on a surface of each of the conductive plugs 80 remote from the probe layer 60, and two of the contact electrodes 90 are formed as shown in fig. 10.
In a more specific embodiment, the manufacturing method further includes: the fifth dielectric layer 100 is disposed on the exposed surfaces of the fourth dielectric layer 70 and the exposed surface of the contact electrode 90, and an opening is formed by etching, so that a part of the contact electrode 90 is exposed by the opening, and the structure shown in fig. 11 is formed, and the disposition of the fifth dielectric layer 100 can further protect other structures such as the contact electrode 90.
In another more specific embodiment, before the conductive material is filled in the via hole 71, an adhesive material may be further disposed to form an adhesive layer (not shown), and then the via hole with the adhesive layer is filled with a barrier material, so as to form a barrier layer 110 on the bottom wall and the sidewall of the via hole 71, so as to prevent the conductive material filled subsequently from diffusing into the dielectric layer, and then the via hole 71 is filled with the conductive material to form the conductive plug 80, as shown in fig. 13, the barrier layer may be Ti and/or TiN.
Since the first direction and the second direction are perpendicular to each other, the plurality of grating sections arranged along the first direction, which is a direction perpendicular to the paper surface or the screen, cannot be seen in the cross-sectional views of fig. 6 to 11, and form a grating coupler.
The substrates such as the first substrate, the second substrate, and the like can be set according to actual conditions, and can be silicon substrates or substrates made of other materials, each dielectric layer can also be set according to actual conditions, and can be silicon dioxide or silicon nitride, and similarly, the material of the waveguide layer can also be selected according to actual conditions.
In a specific embodiment of the present application, the first dielectric layer and the second dielectric layer are both silicon dioxide layers, the first substrate is a silicon layer, and the waveguide layer is made of Si or Si3N4And SiON.
In order to further ensure that the bonded structure has better bonding strength, and ensure that the second dielectric layer and the third dielectric layer in the bonded structure have less influence on the detection process of light and introduce fewer defects, in an embodiment of the present application, the thickness of the second dielectric layer and/or the third dielectric layer is between 100nm and 2 μm.
In the setting process of each structural layer in the present application, any feasible setting manner in the prior art may be selected according to actual conditions, such as specific materials, for example, a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, a thermal oxidation method, a vacuum evaporation method, or a magnetron sputtering method may be adopted.
The "removing" process in the above manufacturing method may adopt any method capable of removing a part of the structure in the prior art, such as wet etching, dry etching, or chemical mechanical polishing, and the like, and an appropriate method may be selected according to specific situations, for example, for the removing process after bonding, a chemical mechanical polishing method may be adopted for implementation; for the formation of the grating portion, wet etching or dry etching may be used.
In another exemplary embodiment of the present application, a semiconductor device is provided, which is formed by any one of the above-described manufacturing methods.
The semiconductor device is formed by adopting any one of the methods, so that the dark current is small, and the performance of the device is good.
In still another exemplary embodiment of the present application, there is provided a semiconductor device, as shown in fig. 10 or 11, including:
the multilayer waveguide structure comprises a first substrate 10, a first medium layer 20, a waveguide layer 30, a second medium layer 40 and a third medium layer 50 which are sequentially stacked;
a detection layer 60, located on a part of the surface of the third dielectric layer 50 away from the second dielectric layer 40, wherein the detection layer 60 includes a P region 63, an I region 62 and an N region 61 sequentially arranged along a second direction, the second direction is perpendicular to the thickness direction of the first substrate 10, the growth temperature of the detection layer 60 is 600-800 ℃, and the detection layer 60 includes Ge and/or GeSi;
a fourth dielectric layer 70 disposed on the surfaces of the third dielectric layer 50 and the detection layer 60 away from the substrate, wherein the fourth dielectric layer 70 has two through holes 71, and the two through holes 71 are respectively abutted to the N region 61 and the P region 63;
two conductive plugs 80, wherein the conductive plugs 80 are located in the through holes 71 in a one-to-one correspondence;
two contact electrodes 90, wherein the contact electrodes 90 are located on the surface of the conductive plug 80 away from the detection layer 60 in a one-to-one correspondence.
In the semiconductor device described above, the detection layer 60 is formed of a material layer having a relatively high growth temperature, so that the material layer has relatively few defects and relatively high quality, and the device has relatively low dark current and relatively good performance.
In order to further improve the optical coupling efficiency and further improve the sensitivity of the detector, in an embodiment of the present application, the waveguide layer 30 includes a plurality of grating portions 31 sequentially arranged along a first direction, where the first direction is perpendicular to the thickness direction of the first substrate 10, as shown in fig. 12.
It should be noted that the semiconductor device of the present application may be a photodetector, or may also be a photonic integrated device including a photodetector, and for the latter, the manufacturing process of the semiconductor device further includes manufacturing steps of other photonic devices, which may be set according to specific situations, and details are not described herein.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.
Examples
The semiconductor device is a photoelectric detector, and the manufacturing process of the semiconductor device is formed by at least the following steps:
first, a first structure to be bonded 01 is formed, specifically as follows:
sequentially disposing a first dielectric layer 20 and a waveguide layer 30 on a surface of a first substrate 10;
the waveguide layer 30 is etched to form a structure including a plurality of grating portions 31 arranged along a first direction, as shown in fig. 1, a second dielectric layer 40 is disposed on the waveguide layer 30 to form the structure shown in fig. 1, wherein the first substrate 10 is a silicon substrate, the first dielectric layer 20 and the second dielectric layer 40 are silicon dioxide layers, and the waveguide layer 30 is a silicon layer.
Secondly, a second structure to be bonded 02 is formed, and the specific process includes:
forming a GOI structure as shown in FIG. 2, wherein the second pre-detection layer 60 in the GOI structure is a second sub-structure layer, the growth temperature of the second pre-detection layer is 600-1000 ℃, a third dielectric layer 50 is arranged on the GOI structure, a second to-be-bonded structure 02 as shown in FIG. 2 is formed, and the third dielectric layer 50 is a silicon dioxide layer.
As shown in fig. 3, bonding the first structure to be bonded 01 and the second structure to be bonded 02 to form a bonded structure 03 as shown in fig. 4, wherein in the bonded structure 03, the second dielectric layer 40 and the third dielectric layer 50 are disposed in contact;
sequentially removing the second substrate 022 and a portion of the second substructure layer, where the remaining portion of the second substructure layer is the second pre-detection layer 60, so as to form the structure shown in fig. 5;
etching the remaining second pre-detection layer 600 to expose a part of the surface of the third dielectric layer 50, thereby forming a detection layer 60 as shown in fig. 6;
performing ion implantation on a portion of the probe layer 60 to form a P region 63 and an N region 61 in the probe layer 60, wherein an undoped I region 62 is formed between the P region 63 and the N region 61, the P region 63, the I region 62, and the N region 61 are arranged in a second direction as shown in fig. 7, and metal contacts not shown in the drawings are formed in the N region 61 and the P region 63, respectively, wherein the first direction is perpendicular to the second direction, and the second direction is perpendicular to the thickness direction of the first substrate 10;
providing a fourth dielectric layer 70 on the exposed surfaces of the detection layer 60 and the exposed surface of the third dielectric layer 50, as shown in fig. 8;
forming two through holes 71 in the fourth dielectric layer 70, wherein the two through holes 71 are respectively in contact with the N region 61 and the P region 63, as shown in fig. 8;
filling a conductive material in each of the through holes 71 to form a conductive plug 80 as shown in fig. 9, where the conductive plug 80 is specifically a tungsten plug;
providing a contact electrode 90 on a surface of each of the conductive plugs 80 away from the probe layer 60, forming two of the contact electrodes 90 as shown in fig. 10;
the fifth dielectric layer 100 is disposed on the exposed surfaces of the fourth dielectric layer 70 and the exposed surface of the contact electrode 90, and an opening is formed by etching, so that a part of the contact electrode 90 is exposed by the opening, and the structure shown in fig. 11 is formed, and the disposition of the fifth dielectric layer 100 can further protect other structures such as the contact electrode 90.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the manufacturing method of the semiconductor device, the second pre-detection layer is arranged on the surface of the first substrate in a bonding mode, and in the bonded structure, the second sub-structure layer is arranged closer to the third dielectric layer than the second substrate, so that the second substrate and part of the structure in the second pre-detection layer can be removed later, only the second sub-structure layer with higher growth temperature is reserved, and the growth temperature of the second sub-structure layer is higher, so that the quality of the layer is better, the defects are fewer, the dark current in the finally prepared detector is smaller, and the performance of the detector is better. In addition, in the manufacturing method, the materials of the second dielectric layer and the third dielectric layer which are directly contacted during bonding are the same, so that the bonding strength is further ensured to be better, the defects in the structure formed after bonding are fewer, and the detector is further ensured to have better performance.
2) In the semiconductor device, the detection layer is formed by the material layer with higher growth temperature, so that the material layer has fewer defects and higher quality, dark current in the device is less, and the performance of the device is better. The dark current is small, and the performance of the device is good.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for manufacturing a semiconductor device, the method comprising:
sequentially arranging a first dielectric layer, a waveguide layer and a second dielectric layer on the surface of a first substrate to form a first structure to be bonded;
forming a pre-detection structure comprising a second substrate and a second pre-detection layer arranged on the surface of the second substrate, wherein the second pre-detection layer comprises a first sub-structure layer and a second sub-structure layer which are sequentially overlapped along the direction far away from the second substrate, the growth temperature of the second sub-structure layer is higher than that of the first sub-structure layer, the growth temperature of the second sub-structure layer is 600-1000 ℃, and the second pre-detection layer comprises Ge and/or GeSi;
arranging a third dielectric layer on the surface of the second substructure layer to form a second structure to be bonded, wherein the second dielectric layer and the third dielectric layer are made of the same material;
bonding the first structure to be bonded and the second structure to be bonded to form a bonded structure, wherein in the bonded structure, the second dielectric layer and the third dielectric layer are arranged in a contact manner;
and removing at least the second substrate, so that only the second substructure layer remains in the pre-detection structure.
2. The method of claim 1, wherein the pre-probing structure is a GOI structure, and the GOI structure comprises the second substrate, the insulating layer and the second sub-structure layer stacked in sequence.
3. The method according to claim 1, wherein the step of forming the first structure to be bonded comprises:
sequentially arranging the first dielectric layer and the waveguide material layer on the surface of the first substrate;
etching the waveguide material layer to form a waveguide layer comprising a plurality of grating parts which are sequentially arranged along a first direction, wherein the first direction is vertical to the thickness direction of the first substrate;
and arranging a second dielectric layer on the surface of the waveguide layer far away from the first dielectric layer.
4. The method of claim 1, wherein the material of the first dielectric layer is the same as the material of the second dielectric layer.
5. The fabrication method according to claim 3, wherein after sequentially removing the second substrate and a portion of the second pre-detection layer, the fabrication method comprises:
etching the remaining second pre-detection layer to expose part of the surface of the third dielectric layer to form a detection layer;
performing ion implantation on a part of the detection layer, forming a P region and an N region in the detection layer, wherein an undoped I region is arranged between the P region and the N region, the P region, the I region and the N region are arranged according to a second direction, the first direction is vertical to the second direction, and the second direction is vertical to the thickness direction of the first substrate;
arranging a fourth medium layer on the surfaces of the exposed detection layer and the exposed third medium layer;
forming two through holes in the fourth dielectric layer, wherein the two through holes are respectively abutted with the N region and the P region;
filling a conductive material in each through hole to form a conductive plug;
and arranging contact electrodes on the surface of each conductive plug far away from the detection layer to form two contact electrodes.
6. The method according to any one of claims 1 to 5, wherein the first dielectric layer and the second dielectric layer are both silicon dioxide layers, the first substrate is a silicon layer, and the material of the waveguide layer comprises Si and Si3N4And SiON.
7. The method according to any one of claims 1 to 5, wherein the thickness of the second dielectric layer and/or the third dielectric layer is between 100nm and 2 μm.
8. A semiconductor device, characterized in that it is manufactured by the manufacturing method of any one of claims 1 to 7.
9. A semiconductor device manufactured by the manufacturing method of any one of claims 1 to 7, comprising:
the waveguide layer is formed by sequentially stacking a first substrate, a first medium layer, a waveguide layer, a second medium layer and a third medium layer;
the detection layer is positioned on the partial surface of the third dielectric layer far away from the second dielectric layer, the detection layer comprises a P area, an I area and an N area which are sequentially arranged along a second direction, the second direction is vertical to the thickness direction of the first substrate, the growth temperature of the detection layer is 600-1000 ℃, and the detection layer comprises Ge and/or GeSi;
the fourth medium layer is positioned on the surfaces, far away from the substrate, of the third medium layer and the detection layer, and is provided with two through holes which are respectively abutted against the N area and the P area;
the two conductive plugs are correspondingly positioned in the through holes one by one;
the two contact electrodes are located on the surface, far away from the detection layer, of the conductive plug in a one-to-one correspondence mode.
10. The semiconductor device according to claim 9, wherein the waveguide layer includes a plurality of grating portions arranged in sequence in a first direction, the first direction being perpendicular to a thickness direction of the first substrate.
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| CN110854017B (en) * | 2019-11-22 | 2022-07-12 | 中国科学院微电子研究所 | Integration method of germanium-based detector |
| CN111129228B (en) * | 2019-12-30 | 2022-04-15 | 中国科学院微电子研究所 | Method for manufacturing photoelectric detector |
| CN111509080A (en) * | 2020-01-20 | 2020-08-07 | 中国科学院微电子研究所 | Detector and manufacturing method thereof |
| CN112652676A (en) * | 2020-12-02 | 2021-04-13 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
| CN112713215A (en) * | 2020-12-03 | 2021-04-27 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
| CN113013287A (en) * | 2021-02-02 | 2021-06-22 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
| CN113013288A (en) * | 2021-02-05 | 2021-06-22 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393944A (en) * | 2007-09-19 | 2009-03-25 | 中国科学院半导体研究所 | Germanium/silicon mixed integrated waveguide type photoelectric converter and manufacturing method thereof |
| CN103928562A (en) * | 2014-05-04 | 2014-07-16 | 厦门大学 | Method for preparing Ge photoelectric detector with transverse p-i-n structure |
| CN104882368A (en) * | 2013-12-20 | 2015-09-02 | 加州大学董事会 | Bonding of heterogeneous material grown on silicon to a silicon photonic circuit |
| CN106328751A (en) * | 2015-07-02 | 2017-01-11 | 中兴通讯股份有限公司 | Silicon-based germanium photodetector |
| CN106611739A (en) * | 2015-10-27 | 2017-05-03 | 中国科学院微电子研究所 | Substrate and manufacturing method thereof |
| US9726841B1 (en) * | 2016-07-12 | 2017-08-08 | Inphi Corporation | Integrated photo detector, method of making the same |
| CN108063168A (en) * | 2017-12-14 | 2018-05-22 | 中国科学院微电子研究所 | Ge photodetectors based on strain regulation and control and preparation method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4237102B2 (en) * | 2004-05-21 | 2009-03-11 | 日本電信電話株式会社 | Manufacturing method of optical waveguide |
| CN101661137B (en) * | 2008-08-27 | 2010-12-22 | 中国科学院半导体研究所 | Method for making silicon waveguide photoelectric converter used in 1.55mu m communication wave band |
| EP2685297B1 (en) * | 2012-07-13 | 2017-12-06 | Huawei Technologies Co., Ltd. | A process for manufacturing a photonic circuit with active and passive structures |
| GB2513531A (en) * | 2012-11-30 | 2014-11-05 | Ibm | Semiconductor structure and method for manufacturing a semiconductor structure |
| JP2017508295A (en) * | 2014-03-10 | 2017-03-23 | コリアント・アドヴァンスド・テクノロジー・エルエルシー | Germanium metal non-contact near-infrared photodetector |
| CN107863399B (en) * | 2017-02-24 | 2019-06-14 | 西藏民族大学 | N-Ge-i-Ge-p-Si structured waveguide type photodetector based on LRC technique and preparation method thereof |
-
2018
- 2018-12-13 CN CN201811526241.4A patent/CN109686658B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393944A (en) * | 2007-09-19 | 2009-03-25 | 中国科学院半导体研究所 | Germanium/silicon mixed integrated waveguide type photoelectric converter and manufacturing method thereof |
| CN104882368A (en) * | 2013-12-20 | 2015-09-02 | 加州大学董事会 | Bonding of heterogeneous material grown on silicon to a silicon photonic circuit |
| CN103928562A (en) * | 2014-05-04 | 2014-07-16 | 厦门大学 | Method for preparing Ge photoelectric detector with transverse p-i-n structure |
| CN106328751A (en) * | 2015-07-02 | 2017-01-11 | 中兴通讯股份有限公司 | Silicon-based germanium photodetector |
| CN106611739A (en) * | 2015-10-27 | 2017-05-03 | 中国科学院微电子研究所 | Substrate and manufacturing method thereof |
| US9726841B1 (en) * | 2016-07-12 | 2017-08-08 | Inphi Corporation | Integrated photo detector, method of making the same |
| CN108063168A (en) * | 2017-12-14 | 2018-05-22 | 中国科学院微电子研究所 | Ge photodetectors based on strain regulation and control and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 《A high-responsivity photodetector absent metalgermanium direct contact》;Yi Zhang et al;《OPTICS EXPRESS》;20140502;第22卷(第9期);第11367-11369页、附图1a * |
| 《近红外波段Ge光电探测器的研究进展》;柯星星 等;《趋势与展望》;20150403;第40卷(第4期);第241-247页 * |
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