CN111129228B - Method for manufacturing photoelectric detector - Google Patents

Method for manufacturing photoelectric detector Download PDF

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CN111129228B
CN111129228B CN201911403215.7A CN201911403215A CN111129228B CN 111129228 B CN111129228 B CN 111129228B CN 201911403215 A CN201911403215 A CN 201911403215A CN 111129228 B CN111129228 B CN 111129228B
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semiconductor substrate
layer
detection layer
doped region
silicon
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CN111129228A (en
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张鹏
唐波
李志华
李彬
刘若男
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1876—Particular processes or apparatus for batch treatment of the devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention discloses a manufacturing method of a photoelectric detector, which comprises the following steps: providing a first semiconductor substrate; forming a detection layer on the upper surface of the first semiconductor substrate by adopting a bonding process; etching the detection layer to expose part of the upper surface of the first semiconductor substrate; and forming a dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer. According to the manufacturing method of the photoelectric detector, the detection layer is formed on the upper surface of the semiconductor substrate by adopting a bonding process, so that the dark current of the silicon-based germanium detector can be reduced.

Description

Method for manufacturing photoelectric detector
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a photoelectric detector.
Background
Nowadays, the technology fields such as information industry and biomedicine are more and more concerned, and novel photoelectron and optical communication technologies are inevitably developed at a faster speed. The silicon-based photoelectronic integration adopts a mature and cheap microelectronic processing technology to integrate an optical device with a microelectronic circuit with multiple functions, and is an effective way for realizing popularization and development of optical communication and optical interconnection. The silicon-based photoelectric detector is one of key devices of a silicon-based optical communication system, and with the breakthrough development of silicon-based germanium material epitaxy technology in recent years, the germanium detector becomes a hot spot of current research because of taking silicon-based photoelectron integration and efficient detection of optical communication wave bands into consideration.
In conventional germanium detectors, the germanium layer is grown directly on the substrate silicon layer, but since silicon and germanium have a 4.2% lattice mismatch, germanium is more prone to defects when grown on silicon, resulting in large dark current of the germanium detector, which affects the performance of the germanium detector.
Disclosure of Invention
The invention aims to solve the problem that a germanium detector manufactured by the prior art has large dark current.
The invention is realized by the following technical scheme:
a method of fabricating a photodetector, comprising:
providing a first semiconductor substrate;
forming a detection layer on the upper surface of the first semiconductor substrate by adopting a bonding process;
etching the detection layer to expose part of the upper surface of the first semiconductor substrate;
and forming a dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer.
Optionally, the forming a detection layer on the upper surface of the first semiconductor substrate by using a bonding process includes:
providing a second semiconductor substrate;
growing the detection layer on the upper surface of the second semiconductor substrate;
connecting the detection layer and the first semiconductor substrate by adopting a bonding process;
and removing the second semiconductor substrate.
Optionally, the first semiconductor substrate is an SOI substrate, the SOI substrate includes a first silicon substrate, a buried oxide layer, and a top silicon layer, which are stacked in sequence from bottom to top, and the second semiconductor substrate is a second silicon substrate.
Optionally, after the providing the first semiconductor substrate, the method further includes:
and doping the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the etched detection layer is positioned right above the intrinsic region.
Optionally, before forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer, the method further includes:
and doping the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the etched detection layer is positioned right above the intrinsic region.
Optionally, after forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer, the method further includes:
forming a first through hole and a second through hole which penetrate through the dielectric layer, wherein the lower bottom surface of the first through hole is abutted with the N-type heavily doped region, and the lower bottom surface of the second through hole is abutted with the P-type heavily doped region;
filling a conductive material into the first through hole and the second through hole to form a first conductive plug and a second conductive plug;
and depositing a metal film on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.
Optionally, the etching the detection layer includes:
and etching the detection layer by adopting a dry etching process.
Optionally, the forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer includes:
and forming the dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer by adopting a physical vapor deposition process or a chemical vapor deposition process.
Optionally, the dielectric layer is made of silicon dioxide.
Optionally, the detection layer is made of germanium or silicon-germanium, and the thickness of the detection layer is 1 to 4 micrometers.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the manufacturing method of the photoelectric detector, the detection layer is formed on the upper surface of the first semiconductor substrate by adopting a bonding process, because the detection layer is epitaxially grown before being bonded, the detection layer is grown at a low temperature and then at a high temperature, the detection layer grown at the low temperature has more defects, and the detection layer grown at the high temperature has less defects, so that after the detection layer and the first semiconductor substrate are bonded, the detection layer close to the first semiconductor substrate has less defects, the detection layer far away from the first semiconductor substrate has more defects, the current of the photoelectric detector flows between the first semiconductor substrate and the detection layer, the detection layer connected with the first semiconductor substrate has less defects, and the dark current of the photoelectric detector is smaller. Therefore, the manufacturing method of the photoelectric detector provided by the invention can achieve the purpose of reducing the dark current of the silicon-based germanium detector.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 to 11 are schematic structural diagrams of a manufacturing process of a photodetector according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
The present embodiment provides a method for manufacturing a photodetector, including the steps of:
providing a first semiconductor substrate;
forming a detection layer on the upper surface of the first semiconductor substrate by adopting a bonding process;
etching the detection layer to expose part of the upper surface of the first semiconductor substrate;
and forming a dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer.
Specifically, the first semiconductor substrate may be a Silicon substrate, or may be an SOI (Silicon On Insulator) substrate. When the first semiconductor substrate is an SOI substrate, the photodetector may be integrated with a waveguide device. In this embodiment, the first semiconductor substrate is an SOI substrate as an example. As shown in fig. 1, the SOI substrate includes a first silicon substrate 11, a buried oxide layer 12, and a top silicon layer 13, which are stacked in this order from bottom to top. There may be a variety of methods for forming the SOI substrate, and in an alternative implementation, the SOI substrate may be formed using a separation by implantation of oxygen technique (SIMOX), namely: providing a third semiconductor substrate; and implanting oxygen ions into the third semiconductor substrate. The buried oxide layer 12 is formed by implanting oxygen ions into the third semiconductor substrate, the third semiconductor substrate is divided into an upper part and a lower part by the buried oxide layer 12, the part below the buried oxide layer 12 is the first silicon substrate 11, and the part above the buried oxide layer 12 is the top silicon layer 13. In a specific embodiment, the oxygen buried layer 12 is formed in silicon by high-energy and large-dose oxygen injection, and the dose of the oxygen ions can be 3 x 1017-2 x 1018cm < -2 >; the energy may be around 200 kev. In another alternative implementation, the SOI substrate may BE formed using a bonding thinning technique (BE), that is: providing a fourth semiconductor substrate, and forming a first oxidation layer on the fourth semiconductor substrate; providing a fifth semiconductor substrate, and forming a second oxide layer on the fifth semiconductor substrate; and connecting the first oxide layer and the second oxide layer in a bonding mode. The first oxide layer and the second oxide layer are connected to serve as the buried oxide layer 12, the fourth semiconductor substrate serves as the silicon substrate 11, and the fifth semiconductor substrate serves as the top silicon layer 13. In the embodiment, the material of the buried oxide layer 12 is silicon dioxide, and the thickness of the buried oxide layer 12 is 2 to 3 micrometers; the material of the top silicon layer 13 is silicon, and the thickness of the top silicon layer 13 is 200 nm to 240 nm.
As shown in fig. 2, in an alternative implementation manner, after the first semiconductor substrate is provided, doping treatment may be performed on the top silicon layer 13 to form an intrinsic region I, an N-type lightly doped region N + located at one side of the intrinsic region I, a P-type lightly doped region P + located at the other side of the intrinsic region, an N-type heavily doped region N + + located at one side of the N-type lightly doped region away from the intrinsic region, and a P-type heavily doped region P + +, located at one side of the P-type lightly doped region away from the intrinsic region, in the top silicon layer 13. The intrinsic region I is an undoped region, and the width of the intrinsic region I, i.e., the distance between the N + type lightly doped region and the P + type lightly doped region, may be 100 nm to 400 nm; the N-type impurity in the N-type lightly doped region N + and the N-type heavily doped region N + + may be phosphorus, the doping concentration of the N + in the N-type lightly doped region may be 1E +19 to 5E +20cm "3, and the doping concentration of the N + + in the N-type heavily doped region may be 1E +20 to 1E +21 cm" 3; the P-type impurity in the P-type lightly doped region P + and the P-type heavily doped region P + + may be boron, the doping concentration of the P-type lightly doped region P + may be 1E +19 to 5E +20cm "3, and the doping concentration of the P-type heavily doped region P + + may be 1E +20 to 1E +21 cm" 3. In another alternative implementation manner, after the first semiconductor substrate is provided, a detection layer is formed on the upper surface of the first semiconductor substrate by directly using a bonding process, and the doping treatment is performed on the top silicon layer before the dielectric layer is formed.
As shown in fig. 3, a second semiconductor substrate 14 is provided, and the detection layer 15 is grown on the upper surface of the second semiconductor substrate 14. In this embodiment, the probe layer 15 is grown on the upper surface of the second semiconductor substrate 14 by a sample epitaxial growth process. The second semiconductor substrate 14 is a second silicon substrate, the detection layer 15 is made of germanium or silicon-germanium, and the thickness of the detection layer 15 is 1 micrometer to 4 micrometers.
As shown in fig. 4, the probe layer 15 and the first semiconductor substrate are connected by a bonding process, i.e. the probe layer 15 and the top silicon layer 13 are connected by a bonding process.
As shown in fig. 5, since the probe layer 15 is epitaxially grown at a low temperature and then at a high temperature, the probe layer grown at a low temperature has a large number of defects and the probe layer grown at a high temperature has a small number of defects, so that after the probe layer 15 and the top silicon layer 13 are connected, the probe layer near the top silicon layer 13 has a small number of defects and the probe layer near the second semiconductor substrate 14 has a large number of defects.
As shown in fig. 6, the second semiconductor substrate 14 may be removed using an etching process, a chemical mechanical polishing process, or a lift-off process.
As shown in fig. 7, the detection layer 15 may be etched by a dry etching process to expose the portion of the upper surface of the first semiconductor substrate, i.e., to expose the portion of the upper surface of the top silicon layer 13.
As shown in fig. 8, a chemical vapor deposition process may be used to form the dielectric layer 16 on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer 15. In this embodiment, the dielectric layer 16 is made of silicon dioxide, and the thickness of the dielectric layer 16 on the first semiconductor substrate is 1.2 to 5 micrometers.
Further, in order to form a complete photodetector, after forming the dielectric layer 16 on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer 16, the method further includes:
forming a first through hole and a second through hole which penetrate through the dielectric layer, wherein the lower bottom surface of the first through hole is abutted with the N-type heavily doped region, and the lower bottom surface of the second through hole is abutted with the P-type heavily doped region;
filling a conductive material into the first through hole and the second through hole to form a first conductive plug and a second conductive plug;
and depositing a metal film on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.
As shown in fig. 9, the dielectric layer 16 is etched to form the first via 211 and the second via 212. The lower bottom surface of the first through hole 211 abuts against the N-type heavily doped region N + +, and the lower bottom surface of the second through hole 212 abuts against the P-type heavily doped region P + +.
As shown in fig. 10, a conductive material is filled into the first via 211 to form the first conductive plug 221; the second via 212 is filled with a conductive material to form the second conductive plug 222. In an alternative implementation manner, before filling the first through hole 211 and the second through hole 212 with the conductive material, an adhesion material and a barrier material may be further disposed on inner walls of the first through hole 211 and the second through hole 212, and an adhesion layer and a barrier layer are formed on the inner walls of the first through hole 211 and the second through hole 212 to prevent the subsequently filled conductive material from diffusing into the dielectric layer.
It should be noted that the shapes of the first through hole 211 and the second through hole 212 may be any shapes that can be manufactured by a manufacturing method, such as a circular through hole or a square through hole, and the manufacturing process of these through holes is simple; the material of the first conductive plug 221 and the second conductive plug 222 may be any conductive material, such as low resistivity materials like aluminum copper alloy, tungsten, and copper; the material of the adhesion layer can be titanium and the like, and the material of the barrier layer can be titanium nitride and the like.
As shown in fig. 11, a physical vapor deposition process may be used to deposit a metal film on the upper surface of the first conductive plug 221 to form the first contact electrode 231; a metal film is deposited on the upper surface of the second conductive plug 222 to form the second contact electrode 232. As a specific embodiment, the material of the first contact electrode 231 and the second contact electrode 232 may be pure aluminum, aluminum copper alloy, aluminum silicon, or aluminum silicon copper, and the thickness of the first contact electrode 231 and the second contact electrode 232 is 200 nanometers to 3 micrometers. If the material of the first contact electrode 231 and the second contact electrode 232 is an aluminum copper alloy, the copper content may be 0.5%; if the material of the first contact electrode 231 and the second contact electrode 232 is aluminum silicon, the content of silicon may be 1%; if the material of the first contact electrode 231 and the second contact electrode 232 is al-si-cu, the si content may be 0.5% and the cu content may be 0.5%.
It should be noted that, in the manufacturing process of this embodiment, the manufacturing process includes a manufacturing process of the photodetector, and when the photodetector is integrated in the optoelectronic integrated chip, the manufacturing process is only a partial manufacturing process of the integrated chip, and the partial manufacturing process does not conflict with a manufacturing process of other devices.
In the manufacturing method of the germanium detector provided in this embodiment, the detection layer 15 is formed on the upper surface of the first semiconductor substrate by using a bonding process, and since the epitaxial growth of the detection layer 15 is performed by performing low-temperature growth and then performing high-temperature growth, the detection layer grown at low temperature generates a lot of defects, and the detection layer grown at high temperature generates a few defects, after the detection layer 15 and the first semiconductor substrate are bonded, the detection layer close to the first semiconductor substrate has fewer defects, the detection layer far from the first semiconductor substrate has more defects, the current of the photodetector flows between the first semiconductor substrate and the detection layer 15, the detection layer connected to the first semiconductor substrate has fewer defects, and the dark current of the photodetector is smaller. Therefore, the manufacturing method of the photoelectric detector provided by the invention can achieve the purpose of reducing the dark current of the silicon-based germanium detector.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (8)

1. A method of fabricating a photodetector, comprising:
providing a first semiconductor substrate, wherein the first semiconductor substrate is an SOI (silicon on insulator) substrate, and the SOI substrate comprises a first silicon substrate, a buried oxide layer and a top silicon layer which are sequentially stacked from bottom to top; forming a detection layer on the upper surface of the first semiconductor substrate by adopting a bonding process, wherein the detection layer is made of germanium or germanium-silicon;
etching the detection layer to expose part of the upper surface of the first semiconductor substrate;
forming a dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer;
wherein after the providing of the first semiconductor substrate or before forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer, further comprising: and doping the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the etched detection layer is positioned right above the intrinsic region.
2. The method of manufacturing a photodetector according to claim 1, wherein the forming a detection layer on the upper surface of the first semiconductor substrate by using a bonding process comprises:
providing a second semiconductor substrate;
growing the detection layer on the upper surface of the second semiconductor substrate;
connecting the detection layer and the first semiconductor substrate by adopting a bonding process;
and removing the second semiconductor substrate.
3. The method of manufacturing a photodetector according to claim 2, wherein the second semiconductor substrate is a second silicon substrate.
4. The method of manufacturing a photodetector according to claim 1, further comprising, after forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer:
forming a first through hole and a second through hole which penetrate through the dielectric layer, wherein the lower bottom surface of the first through hole is abutted with the N-type heavily doped region, and the lower bottom surface of the second through hole is abutted with the P-type heavily doped region;
filling a conductive material into the first through hole and the second through hole to form a first conductive plug and a second conductive plug;
and depositing a metal film on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.
5. The method of claim 1, wherein the etching the detection layer comprises:
and etching the detection layer by adopting a dry etching process.
6. The method of claim 1, wherein the forming a dielectric layer on the portion of the upper surface of the first semiconductor substrate and the upper surface of the detection layer comprises:
and forming the dielectric layer on the part of the upper surface of the first semiconductor substrate and the upper surface of the detection layer by adopting a physical vapor deposition process or a chemical vapor deposition process.
7. The method of claim 1, wherein the dielectric layer is made of silicon dioxide.
8. The method of claim 1, wherein the detection layer has a thickness of 1 to 4 microns.
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CN111290148A (en) * 2020-02-19 2020-06-16 联合微电子中心有限责任公司 Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof
CN112652676A (en) * 2020-12-02 2021-04-13 广东省大湾区集成电路与系统应用研究院 Integration structure and integration method of detector
CN112713215A (en) * 2020-12-03 2021-04-27 广东省大湾区集成电路与系统应用研究院 Integration structure and integration method of detector
CN113013287A (en) * 2021-02-02 2021-06-22 广东省大湾区集成电路与系统应用研究院 Integration structure and integration method of detector
CN113013288A (en) * 2021-02-05 2021-06-22 广东省大湾区集成电路与系统应用研究院 Integration structure and integration method of detector

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