CN109671667B - Three-dimensional memory and forming method of channel hole structure thereof - Google Patents
Three-dimensional memory and forming method of channel hole structure thereof Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 50
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- 239000000758 substrate Substances 0.000 claims description 133
- 239000002346 layers by function Substances 0.000 claims description 93
- 150000004767 nitrides Chemical class 0.000 claims description 45
- 238000003860 storage Methods 0.000 claims description 40
- 230000000903 blocking effect Effects 0.000 claims description 36
- 230000005641 tunneling Effects 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 25
- 230000000149 penetrating effect Effects 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 description 23
- 238000005530 etching Methods 0.000 description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
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- 230000006870 function Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The embodiment of the invention discloses a three-dimensional memory and a method for forming a channel hole structure of the three-dimensional memory, wherein the channel hole structure in the three-dimensional memory is formed by two through hole forming processes of a first through hole and a second through hole, so that the process difficulty and the cost of the channel hole structure are greatly reduced, the problems of high process difficulty and high cost caused by an overlarge depth-to-width ratio of the through holes under the same caliber are solved, and the process difficulty and the cost of manufacturing the three-dimensional memory are also reduced.
Description
The scheme is based on a divisional application with the application number of 201710134782.1
Technical Field
The invention relates to the technical field of three-dimensional memories, in particular to a three-dimensional memory and a forming method of a channel hole structure of the three-dimensional memory.
Background
As the number of stacked ONs (Oxide/Nitride) in a three-dimensional memory (e.g., 3D NAND) is increased, the depth of a channel hole formed in the three-dimensional memory is increased, and when a single etching process is used to form the channel hole, the greater the depth of the channel hole is, the greater the etching difficulty is. Particularly, when the number of the laminated layers in the three-dimensional memory reaches 120 or more and a single etching method is adopted to form the channel holes penetrating through the laminated layers, the phenomenon that the etching time is exponentially increased exists, the process efficiency is low, and the cost is high.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a three-dimensional memory and a method for forming a channel hole structure thereof, so as to reduce process difficulty and cost of the channel hole structure in the three-dimensional memory.
In order to solve the above problems, the embodiments of the present invention provide the following technical solutions:
a method of forming a via hole structure in a three-dimensional memory, the method comprising: providing a substrate, wherein a first stacking layer and a first insulating connecting layer are formed on the surface of the substrate, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in an interlaced mode; forming a first via hole extending completely through the first stack layer and the first insulating connection layer and into the substrate surface; forming a first channel structure on the surface of the substrate exposed by the first through hole; forming a first functional layer on the side wall of the first through hole; sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer; forming a first groove in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate; forming a third channel structure in the first groove, wherein the third channel structure is in contact with the second channel structure, and the third channel structure protrudes out of the first functional layer along the radial outward direction of the first through hole; sequentially forming a second stacked layer and a second insulating connecting layer on one side of the third channel structure, which is far away from the substrate, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; forming a second via completely penetrating through the second stacked layer and the second insulating connection layer and extending into the third channel structure surface, a projection of the second via on the substrate at least partially overlapping a projection of the first via on the substrate; forming a second functional layer on the side wall of the second through hole; sequentially forming a fourth channel structure and a second filling structure on the side wall of the second functional layer and the bottom surface of the second through hole, wherein the surface of the second filling structure is lower than the surface of the fourth channel structure; and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
Optionally, forming a first functional layer on the sidewall of the first through hole includes: forming a first tunneling layer on the side wall of the first through hole and the surface of the first channel structure for generating charges; forming a first storage layer on the surface of the first tunneling layer for storing charges; forming a first blocking layer on the surface of the first storage layer, wherein the first blocking layer is used for blocking the charge in the first storage layer from flowing out; forming a first protective layer on the surface of the first barrier layer, wherein the first protective layer is used for protecting the first barrier layer from being damaged in a subsequent removing process; and removing the first protective layer, the first blocking layer, the first storage layer and the first tunneling layer to form a first functional layer.
Optionally, sequentially forming a second channel structure and a first filling structure on the sidewall of the first functional layer and the surface of the first channel structure, where the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connection layer, includes: forming a second channel layer covering the side wall of the first protective layer, the first channel structure and the surface of the first insulating connection layer; forming a first filling layer covering the second channel layer; removing part of the first filling layer to enable the surface of the first filling layer to be lower than the surface of the first insulation connecting layer, and forming a first filling structure; and removing part of the second channel layer to enable the surface of the second channel layer to be lower than the first insulating connection layer, so as to form a second channel structure.
Optionally, the method further includes: and forming a first mask layer on the surface of the first insulating connection layer.
Optionally, forming a first groove in the first insulating connection layer, where a projection of the first groove on the substrate completely covers a projection of the first via on the substrate includes: removing the first mask layer; flattening the surface of the first insulating connection layer; and removing part of the first insulating connection layer, and forming a first groove penetrating through the first insulating connection layer in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate.
Optionally, sequentially forming a fourth channel structure and a second filling structure on the sidewall of the second functional layer and the bottom of the second through hole, where surfaces of the fourth channel structure and the second filling structure lower than a surface of the second insulating connection layer include: forming a fourth channel layer covering the side wall of the second protective layer, the bottom of the second through hole and the surface of the second insulating connecting layer; forming a second filling layer covering the fourth channel layer; removing part of the second filling layer to enable the surface of the second filling layer to be lower than the surface of the second insulating connecting layer, and forming a second filling structure; and removing two parts of the fourth channel layer on the surface of the second insulating connecting layer to form a fourth channel structure, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
A three-dimensional memory, comprising: the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; a first via hole penetrating through the first stack layer and the first insulating connection layer and extending into the substrate surface; a first channel structure formed on the substrate surface exposed by the first through hole; the first functional layer is formed on the side wall of the first through hole; a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer; a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate; a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure, the third channel structure protruding from the first functional layer in a radially outward direction of the first through hole; a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; a second via extending through the second stacked layer and the second insulating connection layer and into the third channel structure surface, a projection of the second via on the substrate at least partially overlapping a projection of the first via on the substrate; the second functional layer is formed on the side wall of the second through hole; a fourth channel structure and a second filling structure which are sequentially formed on the side wall of the second functional layer and the bottom surface of the second through hole, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure; and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
A method for forming a via hole structure in a three-dimensional memory, the three-dimensional memory comprising a first region, a second region and a third region arranged along a word line direction, wherein the first region is used for forming the via hole structure, and the third region is used for forming an insulating ring structure, the method comprising: providing a substrate, wherein a first stacking layer and a first insulating connecting layer are formed on the surface of the substrate, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in an interlaced mode; forming a first via hole completely penetrating the first stack layer and the first insulating connection layer and extending into the substrate surface in the first region, the second region, and the third region; forming a first channel structure on the surface of the substrate exposed by the first through hole; forming a first functional layer on the side wall of the first through hole; sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer; forming a first groove in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate; forming a third channel structure in the first groove, wherein the third channel structure is in contact with the second channel structure, and the third channel structure protrudes out of the first functional layer along the radial outward direction of the first through hole; sequentially forming a second stacked layer and a second insulating connecting layer on one side of the third channel structure, which is far away from the substrate, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; forming a second via hole completely penetrating through the second stacked layer and the second insulating connection layer and extending into the surface of the third channel structure in the first region, the second region, and the third region, a projection of the second via hole on the substrate at least partially overlapping a projection of the first via hole on the substrate; forming a second functional layer on the side wall of the second through hole; forming a fourth channel structure on the side wall of the second functional layer corresponding to the first area and the bottom of the second through hole, and forming a second filling structure in the second through hole corresponding to the first area, the second area and the third area, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure; and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
Optionally, forming a fourth channel structure on the sidewall of the second functional layer corresponding to the first area and the bottom of the second through hole, and forming a second filling structure in the second through hole corresponding to the first area, the second area, and the third area, where a surface of the fourth channel structure is higher than a surface of the second filling structure includes: forming a fourth channel layer covering the side wall of the second functional layer, the bottom of the second through hole and the surface of the second insulating connection layer in the first area, the second area and the second area; forming a third filling layer covering the fourth channel layer in the first region, the second region and the second region, the third filling layer having an air gap therein; forming a third mask layer on the surface of the third filling layer corresponding to the first area; removing the third filling layer in the second area and the third area by taking the third mask layer as a mask; removing the third mask layer; taking the part of the third filling layer, which is positioned in the first area, as a mask, and removing the fourth channel layer positioned in the second area and the third area; forming a fourth filling layer on the surface of the second functional layer positioned in the second area and the third area, wherein the filling performance of the fourth filling layer is better than that of the third filling layer; removing the third filling layer on the surface of the fourth channel layer in the first area; forming a second filling layer in the second through holes of the first area, the second area and the third area; removing part of the second filling layer to enable the surface of the second filling layer to be lower than that of the second insulating connection layer, and forming a second filling structure; and removing the part of the fourth channel layer, which is positioned on the surface of the second insulating connecting layer, to form a fourth channel structure, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
Optionally, forming a first functional layer on the sidewall of the first through hole includes: forming a first tunneling layer on the side wall of the first through hole and the surface of the first channel structure for generating charges; forming a first storage layer on the surface of the first tunneling layer for storing charges; forming a first blocking layer on the surface of the first storage layer, wherein the first blocking layer is used for blocking the charge in the first storage layer from flowing out; forming a first protective layer on the surface of the first barrier layer, wherein the first protective layer is used for protecting the first barrier layer from being damaged in a subsequent removing process; and removing the first protective layer, the first blocking layer, the first storage layer and the first tunneling layer to form a first functional layer.
Optionally, sequentially forming a second channel structure and a first filling structure on the sidewall of the first functional layer and the surface of the first channel structure, where the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connection layer, includes: forming a second channel layer covering the side wall of the first protective layer, the first channel structure and the surface of the first insulating connection layer; forming a first filling layer covering the second channel layer; removing part of the first filling layer to enable the surface of the first filling layer to be lower than the surface of the first insulation connecting layer, and forming a first filling structure; and removing part of the second channel layer to enable the surface of the second channel layer to be lower than the first insulating connection layer, so as to form a second channel structure.
A three-dimensional memory comprising a first region, a second region and a third region arranged along a word line direction, wherein the first region is used for forming a channel hole structure, the third region is used for forming an insulating ring structure, and the three-dimensional memory comprises the following components along a direction perpendicular to the surface of the three-dimensional memory: the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; a first via hole extending completely through the first stack layer and the first insulating connection layer and into the substrate surface at the first region, the second region, and the third region; forming a first channel structure on the surface of the substrate exposed by the first through hole; a first functional layer formed on a sidewall of the first via hole; a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer; a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate; a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure, the third channel structure protruding from the first functional layer in a radially outward direction of the first through hole; a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode; a second via hole completely penetrating the second stacked layer and the second insulating connection layer in the first region, the second region, and the third region and extending into a surface of the third channel structure, a projection of the second via hole on the substrate at least partially overlapping a projection of the first via hole on the substrate; a second functional layer formed on a sidewall of the second via hole; a fourth channel structure formed on the sidewall of the second functional layer corresponding to the first region and the bottom of the second through hole, and a second filling structure formed in the second through hole corresponding to the first region, the second region and the third region, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure; and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
Compared with the prior art, the technical scheme has the following advantages:
according to the method for forming the channel hole structure of the three-dimensional memory, the channel hole structure in the three-dimensional memory is formed through the first through hole and the second through hole twice through hole forming processes, so that the process difficulty and the cost of the channel hole structure are greatly reduced, the problems of high process difficulty and high cost caused by the fact that the depth-to-width ratio of the through holes is too large under the same caliber are solved, and meanwhile, the process difficulty and the cost of manufacturing the three-dimensional memory are also reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1-21 are cross-sectional views of steps of a method for forming a via structure in a three-dimensional memory according to an embodiment of the invention;
fig. 22-46 are cross-sectional views of steps of a method for forming a via structure in a three-dimensional memory according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
The embodiment of the invention provides a method for forming a channel hole structure in a three-dimensional memory, which comprises the following steps:
s101: as shown in fig. 1, a substrate 1 is provided, and a first stacked layer 2 and a first insulating connection layer 3 are formed on the surface of the substrate 1, wherein the first stacked layer 2 is composed of a plurality of oxide layers and nitride layers which are alternately stacked. Optionally, the sum of the numbers of the oxide layers and the nitride layers in the first stacked layer 2 is not less than 64, but the invention is not limited thereto, as the case may be.
Specifically, in an embodiment of the present invention, the first insulating connection layer 3 is a silicon oxide layer, but the present invention is not limited thereto, as long as the first insulating connection layer 3 and the nitride layer in the first stacked layer 2 are ensured to be different in material and have an insulating function.
It should be noted that, on the basis of the above embodiment, in an embodiment of the present invention, the method further includes:
forming a first mask layer 4 on the surface of the first insulating connection layer 3, wherein optionally, the first mask layer 4 includes a nitride layer on the surface of the first insulating connection layer 3 and an oxide layer on the surface of the nitride layer.
S102: continuing with fig. 1, a first via 5 is formed extending completely through the first stack layer 2 and the first insulating connection layer 3 and into the surface of the substrate 1.
Specifically, in one embodiment of the present invention, forming the first via hole 5 that completely penetrates the first stack layer 2 and the first insulating connection layer 3 and extends into the surface of the substrate 1 includes:
etching the first stacked layer 2 and the first insulating connection layer 3, and forming a first through hole 5 penetrating through the first stacked layer 2 and the first insulating connection layer 3 and extending into the surface of the substrate 1 in the first stacked layer 2 and the first insulating connection layer 3; the first through hole 5 is cleaned.
It should be noted that, when etching the first stacked layer 2 and the first insulating connection layer 3, wet etching may be selected, dry etching may also be selected, or a combination of them may be used.
It should be further noted that, when the first mask layer 4 is formed on the surface of the first insulating connection layer 3, etching of the first mask layer 4 is further included when the first through hole 5 is formed.
S103: as shown in fig. 2, a first channel structure 6 is formed on the surface of the substrate 1 exposed by the first via 5. Optionally, in an embodiment of the present invention, the first channel structure 6 is a silicon layer, and the forming process is a selective epitaxy process.
S104: and forming a first functional layer on the side wall of the first through hole 5.
Specifically, in an embodiment of the present invention, the forming of the first functional layer on the sidewall of the first through hole 5 includes:
as shown in fig. 3, a first tunneling layer 7 is formed on the sidewall of the first via 5 and the surface of the first channel structure 6 for generating charges, optionally, the first tunneling layer 7 is an oxide layer, and the forming process is a deposition process;
forming a first storage layer 8 on the surface of the first tunneling layer 7 for storing charges, wherein optionally, the first storage layer 8 is a nitride layer, and the forming process is a deposition process;
forming a first blocking layer 9 on the surface 8 of the first storage layer, for blocking the outflow of charges in the first storage layer 8, optionally, the first blocking layer 9 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 4, a first protective layer 10 is formed on the surface of the first barrier layer 9, and is used for protecting the first barrier layer 9 from being damaged in a subsequent removal process, optionally, the first protective layer 10 is an amorphous silicon layer, and the formation process is a deposition process;
as shown in fig. 4, removing portions of the first protection layer 10, the first blocking layer 9, the first storage layer 8, and the first tunneling layer 7 on the surface of the first channel structure 6 to form a first functional layer, and optionally, the removing process is an etching process and a cleaning process.
S105: and sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure 6, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer 3.
Specifically, in an embodiment of the present invention, sequentially forming a second channel structure and a first filling structure on the sidewall of the first functional layer and the surface of the first channel structure, where the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connection layer 3 includes:
as shown in fig. 5, a second channel layer 11 is formed to cover the sidewall of the first protection layer 10, the bottom of the first through hole 5, and the surface of the first insulating connection layer 3, optionally, the second channel layer 11 is an amorphous silicon layer, and the forming process is a deposition process;
as shown in fig. 6, a first filling layer 12 is formed to cover the second channel layer 11, optionally, the first filling layer 12 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 7, removing a portion of the first filling layer 12 to make the surface of the first filling layer 12 lower than the surface of the first insulating connection layer 3, so as to form a first filling structure, optionally, the removing process is an etching process;
as shown in fig. 8, removing a portion of the second channel layer 11 to make the surface of the second channel layer 11 lower than the first insulating connection layer 3, so as to form a second channel structure, optionally, the removing process is an etching process.
It should be noted that, in the embodiment of the present invention, the upper surface of the second via structure may be higher than the upper surface of the first stacked layer 2, or may be lower than the upper surface of the first stacked layer 2, which is not limited in the present invention, as long as the upper surface of the second via structure is not lower than the upper surface of the top oxide layer in the first stacked layer 2. Optionally, the upper surface of the second via structure is flush with the upper surface of the top oxide layer in the first stacked layer 2.
S106: a first groove is formed in the first insulating connection layer 3, and a projection of the first groove on the substrate 1 completely covers a projection of the first through hole on the substrate 1.
Specifically, in an embodiment of the present invention, forming a first groove in the first insulating connection layer 3, a projection of the first groove on the substrate 1 completely covering a projection of the first through hole on the substrate 1 includes:
and removing part of the first insulating connection layer 3, and forming a first groove penetrating through the first insulating connection layer 3 in the first insulating connection layer 3, wherein the projection of the first groove on the substrate 1 completely covers the projection of the first through hole on the substrate 1. Optionally, a projected area of the first groove on the substrate 1 is larger than a projected area of the first through hole on the substrate 1.
It should be noted that, when the first mask layer 4 is formed on the surface of the first insulating connection layer 3, forming a first groove in the first insulating connection layer 3, and a projection of the first groove on the substrate 1 completely covers a projection of the first through hole on the substrate 1 includes:
as shown in fig. 9, the first mask layer 4 is removed;
as shown in fig. 10, the surface of the first insulating connection layer 3 is planarized;
continuing with fig. 10, removing a portion of the first insulating connection layer 3, forming a first groove 13 penetrating through the first insulating connection layer 3 in the first insulating connection layer 3, wherein a projection of the first groove 13 on the substrate 1 completely covers a projection of the first through hole 5 on the substrate 1.
S107: as shown in fig. 11, a third channel structure 14 is formed in the first groove 13, the third channel structure 14 is in contact with the second channel structure, and the third channel structure 14 protrudes from the first functional layer along a radial direction of the first through hole. Optionally, the forming process of the third channel structure 14 is a deposition process.
S108: as shown in fig. 12, a second stacked layer 15 and a second insulating connection layer 16 are sequentially formed on a side of the third channel structure 14 away from the substrate 1, where the second stacked layer 15 is formed by a plurality of oxide layers and nitride layers stacked alternately. Optionally, the sum of the numbers of the oxide layer and the nitride layer in the second stacked layer 15 is not less than 64, but the present invention is not limited thereto, as the case may be.
Specifically, in an embodiment of the present invention, the second insulating connection layer 16 is a silicon oxide layer, but the present invention is not limited thereto, as long as the second insulating connection layer 16 and the nitride layer in the second stacked layer 15 are made of different materials and have an insulating function.
It should be noted that, on the basis of the above embodiment, in an embodiment of the present invention, the method further includes:
forming a second mask layer 17 on the surface of the second insulating connection layer 16, wherein optionally, the second mask layer 17 includes a nitride layer on the surface of the second insulating connection layer and an oxide layer on the surface of the nitride layer.
S109: continuing with fig. 13, a second via 18 is formed completely through the second stacked layer 15 and the second insulating connection layer 16 and extending into the surface of the third channel structure 14, the projection of the second via 18 on the substrate 1 at least partially overlapping the projection of the first via 5 on the substrate 1.
Specifically, in one embodiment of the present invention, forming the second via hole 18 completely penetrating through the second stacked layer 15 and the second insulating connection layer 16 and extending into the surface of the third channel structure 14 includes:
etching the second stacked layer 15 and the second insulating connection layer 16, and forming a second through hole 18 penetrating through the second stacked layer 15 and the second insulating connection layer 16 and extending into the surface of the third channel structure 14 in the second stacked layer 15 and the second insulating connection layer 16; the second through hole 18 is cleaned.
It should be noted that, in the embodiment of the present invention, the second through hole 18 may extend to the surface of the third channel structure 14, or may extend into the surface of the third channel structure 14, which is not limited in the present invention, as long as it is ensured that a subsequently formed fourth channel structure may directly contact with the third channel structure.
It should be further noted that, when etching the second stacked layer 15 and the second insulating connection layer 16, wet etching may be selected, dry etching may also be selected, or a combination thereof may also be used, which is not limited in the present invention, and is determined as the case may be.
On the basis of the above embodiment, in an embodiment of the present invention, when the second mask layer 17 is formed on the surface of the second insulating connection layer 16, etching the second mask layer 17 is further included when the second via hole 18 is formed. It should be noted that, in the embodiment of the present invention, the distance a between the boundary line of the second mask layer 17 on the side facing the second via hole 18 and the boundary line of the first mask layer 4 on the side facing the first via hole 5 is not more than 15nm at maximum.
S1010: a second functional layer is formed on the sidewall of the second via 18.
Specifically, in an embodiment of the present invention, forming the second functional layer on the second through-hole sidewall includes:
as shown in fig. 14, a second tunneling layer 19 is formed on the sidewall of the second via 18 and the surface of the second channel structure 14 for generating charges, optionally, the second tunneling layer 19 is an oxide layer, and the forming process is a deposition process;
forming a second storage layer 20 on the surface of the second tunneling layer 19 for storing charges, wherein optionally, the second storage layer 20 is a nitride layer, and the forming process is a deposition process;
forming a second blocking layer 21 on the surface of the second storage layer 20, for blocking the outflow of charges in the second storage layer 20, optionally, the second blocking layer 21 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 15, a second protection layer 22 is formed on the surface of the second barrier layer 21 to protect the second barrier layer 21 from being damaged in a subsequent removal process, optionally, the second protection layer 22 is an amorphous silicon layer, and the formation process is a deposition process;
as shown in fig. 15, removing portions of the second protection layer 22, the second blocking layer 21, the second storage layer 20, and the second tunneling layer 19 on the surface of the second channel structure 14 to form a second functional layer, and optionally, the removing process is an etching process and a cleaning process.
S1012: and sequentially forming a fourth channel structure and a second filling structure on the side wall of the second functional layer and the bottom of the second through hole, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
Specifically, in an embodiment of the present invention, sequentially forming a fourth channel structure and a second filling structure on the sidewall of the second functional layer and the surface of the third channel structure, where a surface of the fourth channel structure is higher than a surface of the second filling structure includes:
as shown in fig. 16, a fourth channel layer 23 is formed to cover the sidewall of the second passivation layer 22, the bottom of the second via 18, and the surface of the second insulating connection layer 3, optionally, the fourth channel layer 23 is an amorphous silicon layer, and the forming process is a deposition process;
as shown in fig. 17, a second filling layer 29 is formed to cover the fourth channel layer 23, optionally, the second filling layer 29 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 18, removing a portion of the second filling layer 29 to make the surface of the second filling layer 29 lower than the surface of the second insulating connection layer 3, so as to form a second filling structure, optionally, the removing process is an etching process;
as shown in fig. 19, a portion of the fourth channel layer 23 on the surface of the second insulating connection layer is removed to form a fourth channel structure, where the surface of the fourth channel structure is higher than the surface of the second filling structure, and optionally, the removing process is an etching process.
It should be noted that, in the embodiment of the present invention, an upper surface of the fourth channel structure may be higher than an upper surface of the second stacked layer, or may be lower than the upper surface of the second stacked layer, which is not limited in the present invention, as long as the upper surface of the fourth channel structure is not lower than an upper surface of a top oxide layer in the second stacked layer. Optionally, an upper surface of the fourth channel structure is flush with an upper surface of a top oxide layer in the second stacked layer.
S1013: and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
Specifically, in an embodiment of the present invention, when a second mask layer is formed on a surface of the second insulating connection layer, forming a fifth via structure in a second groove formed by the fourth via structure and the second filling structure, where the fifth via structure and the fourth via structure are in contact with each other includes:
as shown in fig. 20, a fifth channel structure is formed in the second groove formed by the fourth channel structure and the second filling structure;
removing the second mask layer;
as shown in fig. 21, the surface of the second insulating connection layer is planarized.
Correspondingly, an embodiment of the present invention further provides a three-dimensional memory formed by using the above forming method, where the three-dimensional memory includes:
the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a first via hole penetrating through the first stack layer and the first insulating connection layer and extending into the substrate surface;
a first channel structure formed on the substrate surface exposed by the first through hole;
the first functional layer is formed on the side wall of the first through hole;
a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure;
a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a second via extending through the second stacked layer and the second insulating connection layer and into the third channel structure surface, a projection of the second via on the substrate at least partially overlapping a projection of the first via on the substrate;
the second functional layer is formed on the side wall of the second through hole;
a fourth channel structure and a second filling structure which are sequentially formed on the side wall of the second functional layer and the bottom surface of the second through hole, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure;
and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
As can be seen from the above, in the method for forming a channel hole structure of a three-dimensional memory provided in the embodiment of the present invention, the channel hole structure in the three-dimensional memory is formed by two through hole forming processes of the first through hole and the second through hole, so that the process difficulty and the cost of the channel hole structure are greatly reduced, the problems of high process difficulty and high cost caused by an excessively large depth-to-width ratio of the through holes under the same aperture are solved, and the process difficulty and the cost of manufacturing the three-dimensional memory are also reduced.
In addition, another method for forming a via hole structure in a three-dimensional memory is further provided, where the three-dimensional memory includes a first region, a second region, and a third region arranged along a word line direction, where the first region is used to form the via hole structure, and the third region is used to form an insulating ring structure, and the method includes:
s201: as shown in fig. 22, a substrate 1 is provided, and a first stacked layer 2 and a first insulating connection layer 3 are formed on the surface of the substrate 1, wherein the first stacked layer 2 is composed of a plurality of oxide layers and nitride layers which are alternately stacked. Optionally, the sum of the numbers of the oxide layers and the nitride layers in the first stacked layer 2 is not less than 64, but the invention is not limited thereto, as the case may be.
Specifically, in an embodiment of the present invention, the first insulating connection layer 3 is a silicon oxide layer, but the present invention is not limited thereto, as long as the first insulating connection layer 3 and the nitride layer in the first stacked layer 2 are ensured to be different in material and have an insulating function.
It should be noted that, on the basis of the above embodiment, in an embodiment of the present invention, the method further includes:
forming a first mask layer 4 on the surface of the first insulating connection layer 3, wherein optionally, the first mask layer 4 includes a nitride layer on the surface of the first insulating connection layer 3 and an oxide layer on the surface of the nitride layer.
S202: as shown in fig. 22, a first through hole 5 is formed in the first region 100 (i.e., Channel hole), the second region 200 (i.e., SS dummy hole), and the third region 300 (i.e., TAC barrier) to extend completely through the first stack layer 2 and the first insulating connection layer 3 and to the surface of the substrate 1. It should be noted that, in the direction perpendicular to the surface of the substrate 1, the depth of the first through hole at the third region 300 is greater than the depth of the first through hole at the first region 100.
It should be further noted that, when the first mask layer 4 is formed on the surface of the first insulating connection layer 3, etching of the first mask layer 4 is further included when the first through hole is formed.
S203: as shown in fig. 23, a first channel structure 6 is formed on the surface of the substrate 1 exposed by the first via 5.
S204: and forming a first functional layer on the side wall of the first through hole 5.
Specifically, in one embodiment of the present invention, forming a first functional layer on the first via sidewall includes:
as shown in fig. 24, a first tunneling layer 7 is formed on the sidewall of the first via 5 and the surface of the first channel structure 6 for generating charges, optionally, the first tunneling layer 7 is an oxide layer, and the forming process is a deposition process;
forming a first storage layer 8 on the surface of the first tunneling layer 7 for storing charges, wherein optionally, the first storage layer 8 is a nitride layer, and the forming process is a deposition process;
forming a first blocking layer 9 on the surface of the first storage layer 8, for blocking the outflow of charges in the first storage layer 8, optionally, the first blocking layer 9 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 25, a first protective layer 10 is formed on the surface of the first barrier layer 9 to prevent the first barrier layer 9 from being damaged in a subsequent removal process, optionally, the first protective layer 10 is an amorphous silicon layer, and the formation process is a deposition process;
as shown in fig. 25, removing portions of the first protection layer 10, the first blocking layer 9, the first storage layer 8, and the first tunneling layer 7 on the surface of the first channel structure 6 to form a first functional layer, and optionally, the removing process is an etching process and a cleaning process.
S205: and sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer 3.
Specifically, in an embodiment of the present invention, sequentially forming a second channel structure and a first filling structure on the sidewall of the first functional layer and the surface of the first channel structure, where the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connection layer 3 includes:
as shown in fig. 26, forming a second channel layer 11 covering the sidewall of the first protection layer 10, the bottom of the first through hole 5, and the surface of the first insulating connection layer 3, optionally, the second channel layer 11 is an amorphous silicon layer, and the forming process is a deposition process;
as shown in fig. 27, forming a first filling layer 12 covering the second channel layer 11, optionally, the first filling layer 12 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 28, removing a portion of the first filling layer 12 to make the surface of the first filling layer 12 lower than the surface of the first insulating connection layer 3, so as to form a first filling structure, optionally, the removing process is an etching process;
as shown in fig. 29, removing a portion of the second channel layer 11 to make the surface of the second channel layer 11 lower than the first insulating connection layer 3, so as to form a second channel structure, and optionally, the removing process is an etching process.
It should be noted that, in the embodiment of the present invention, the upper surface of the second via structure may be higher than the upper surface of the first stacked layer 2, or may be lower than the upper surface of the first stacked layer 2, which is not limited in the present invention, as long as the upper surface of the second via structure is not lower than the upper surface of the top oxide layer in the first stacked layer 2. Optionally, the upper surface of the second via structure is flush with the upper surface of the top oxide layer in the first stacked layer 2.
S206: a first groove is formed in the first insulating connection layer 3, and a projection of the first groove on the substrate 1 completely covers a projection of the first through hole on the substrate 1.
Specifically, in an embodiment of the present invention, forming a first groove in the first insulating connection layer 3, a projection of the first groove on the substrate 1 completely covering a projection of the first through hole on the substrate 1 includes:
and removing part of the first insulating connection layer 3, and forming a first groove penetrating through the first insulating connection layer 3 in the first insulating connection layer 3, wherein the projection of the first groove on the substrate 1 completely covers the projection of the first through hole on the substrate 1. Optionally, a projected area of the first groove on the substrate 1 is larger than a projected area of the first through hole on the substrate 1.
In another embodiment of the present invention, when the first mask layer 4 is formed on the surface of the first insulating connection layer 3, forming a first groove in the first insulating connection layer 3, wherein a projection of the first groove on the substrate 1 completely covers a projection of the first through hole on the substrate 1 includes:
as shown in fig. 30, the first mask layer 4 is removed;
as shown in fig. 31, the surface of the first insulating connection layer 3 is planarized;
continuing with fig. 31, removing a portion of the first insulating connection layer 3, forming a first groove 13 penetrating through the first insulating connection layer 3 in the first insulating connection layer 3, wherein a projection of the first groove 13 on the substrate 1 completely covers a projection of the first through hole 5 on the substrate 1.
S207: as shown in fig. 32, a third channel structure 14 is formed in the first groove 13, and the third channel structure 14 is in contact with the second channel structure.
S208: as shown in fig. 33, a second stacked layer 15 and a second insulating connection layer 16 are sequentially formed on a side of the third channel structure 14 away from the substrate 1, where the second stacked layer 15 is formed by a plurality of oxide layers and nitride layers stacked alternately. Optionally, the sum of the numbers of the oxide layer and the nitride layer in the second stacked layer 15 is not less than 64, but the present invention is not limited thereto, as the case may be.
Specifically, in an embodiment of the present invention, the second insulating connection layer 16 is a silicon oxide layer, but the present invention is not limited thereto, as long as the second insulating connection layer and the nitride layer in the second stacked layer are made of different materials and have an insulating function.
It should be noted that, on the basis of the above embodiment, in an embodiment of the present invention, the method further includes:
forming a second mask layer 17 on the surface of the second insulating connection layer 16, wherein optionally, the second mask layer 17 includes a nitride layer on the surface of the second insulating connection layer and an oxide layer on the surface of the nitride layer.
S209: as shown in fig. 34, a second through hole 18 is formed in the first region, the second region and the third region, completely penetrating through the second stacked layer 15 and the second insulating connection layer 16, and extending into the surface of the third channel structure 14, and a projection of the second through hole 18 on the substrate 1 at least partially overlaps with a projection of the first through hole 5 on the substrate 1.
It should be noted that, during a specific process, the third channel structure of the third area may be completely penetrated by the second through hole, which is not limited in the present invention as long as it is ensured that the third channel structure of the first area is not completely penetrated by the second through hole.
Specifically, in one embodiment of the present invention, forming the second via hole that completely penetrates through the second stacked layer and the second insulating connection layer and extends into the third channel structure surface includes:
etching the second stacked layer and the second insulating connection layer, and forming a second through hole which penetrates through the second stacked layer and the second insulating connection layer and extends into the surface of the third channel structure in the second stacked layer and the second insulating connection layer; and cleaning the second hole.
It should be noted that, in the embodiment of the present invention, the second through hole may extend to the surface of the third channel structure, or may extend into the surface of the third channel structure, which is not limited in the present invention, as long as it is ensured that a subsequently formed fourth channel structure may directly contact with the third channel structure.
On the basis of the foregoing embodiment, in an embodiment of the present invention, when a second mask layer is formed on a surface of the second insulating connection layer, etching the second mask layer is further included when forming the second via hole. It should be noted that, in the embodiment of the present invention, a distance between a boundary line of the second mask layer on a side facing the second via hole and a boundary line of the first mask layer on a side facing the first via hole is not more than 15nm at maximum.
S2010: and forming a second functional layer on the side wall of the second through hole.
Specifically, in an embodiment of the present invention, forming the second functional layer on the second through-hole sidewall includes:
as shown in fig. 35, a second tunneling layer 19 is formed on the sidewall of the second via 18 and the surface of the second channel structure 14 for generating charges, optionally, the second tunneling layer 19 is an oxide layer, and the forming process is a deposition process;
forming a second storage layer 20 on the surface of the second tunneling layer 19 for storing charges, wherein optionally, the second storage layer 20 is a nitride layer, and the forming process is a deposition process;
forming a second blocking layer 21 on the surface of the second storage layer 20, for blocking the outflow of charges in the second storage layer 20, optionally, the second blocking layer 21 is an oxide layer, and the forming process is a deposition process;
as shown in fig. 36, a second protection layer 22 is formed on the surface of the second barrier layer 21 to protect the second barrier layer 21 from being damaged in the subsequent removal process, optionally, the second protection layer 22 is an amorphous silicon layer, and the formation process is a deposition process;
as shown in fig. 36, removing portions of the second protection layer 22, the second blocking layer 21, the second storage layer 20, and the second tunneling layer 19 on the surface of the second channel structure 14 to form a second functional layer, and optionally, the removing process is an etching process and a cleaning process.
S2011: and forming a fourth channel structure on the side wall of the second functional layer corresponding to the first area and the bottom of the second through hole, and forming a second filling structure in the second through hole corresponding to the first area, the second area and the third area, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
Specifically, in an embodiment of the present invention, forming a fourth channel structure in the sidewall of the second functional layer corresponding to the first area and the bottom of the second through hole, and forming a second filling structure in the second through hole corresponding to the first area, the second area, and the third area, wherein a surface of the fourth channel structure is higher than a surface of the second filling structure includes:
as shown in fig. 37, a fourth channel layer 23 is formed in the first region, the second region, and the second region so as to cover the second functional layer sidewall, the second via bottom, and the second insulating connection layer surface;
as shown in fig. 38, a third filling layer 24 covering the fourth channel layer 23 is formed in the first region, the second region, and the third filling layer 24 has an air gap therein;
as shown in fig. 39, a third mask layer 25 is formed on the surface of the third filling layer 24 corresponding to the first region;
removing the third filling layer 24 in the second region and the third region by using the third mask layer 25 as a mask;
as shown in fig. 40, the third mask layer 25 is removed;
removing the fourth channel layer 23 in the second region and the third region by using the portion of the third filling layer 24 in the first region as a mask;
as shown in fig. 41, a fourth filling layer 27 is formed on the surface of the second functional layer located in the second area and the third area, and the filling performance of the fourth filling layer 27 is better than that of the third filling layer 24, that is, in the same removing process, the removing rate of the fourth filling layer is less than that of the third filling layer;
as shown in fig. 42, the third filling layer 24 on the surface of the fourth channel layer 23 in the first region is removed;
as shown in fig. 43, a second filling layer 29 is formed in the second through holes of the first, second, and third areas;
as shown in fig. 44, removing a portion of the second filling-up layer 29 to make the surface of the second filling-up layer 29 lower than the surface of the second insulating connection layer 16, so as to form a second filling-up structure;
and removing the part of the fourth channel layer 23 on the surface of the second insulating connection layer 16 to form a fourth channel structure, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
S2012: and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
Specifically, in an embodiment of the present invention, when a second mask layer is formed on a surface of the second insulating connection layer, forming a fifth via structure in a second groove formed by the fourth via structure and the second filling structure includes:
as shown in fig. 45, a fifth channel structure 30 is formed in the second groove formed by the fourth channel structure and the second filling structure;
removing the second mask layer;
as shown in fig. 46, the surface of the second insulating connection layer 16 is planarized.
Correspondingly, an embodiment of the present invention further provides a three-dimensional memory, where the three-dimensional memory includes a first region, a second region, and a third region arranged along a word line direction, where the first region is used to form a via hole structure, and the third region is used to form an insulating ring structure, and the three-dimensional memory includes, along a direction perpendicular to a surface of the three-dimensional memory:
the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a first via hole located in the first region, the second region, and the third region, completely penetrating the first stack layer and the first insulating connection layer, and extending into the substrate surface;
forming a first channel structure on the surface of the substrate exposed by the first through hole;
a first functional layer formed on a sidewall of the first via hole;
a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure;
a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a second via hole completely penetrating the second stacked layer and the second insulating connection layer in the first region, the second region, and the third region and extending into a surface of the third channel structure, a projection of the second via hole on the substrate at least partially overlapping a projection of the first via hole on the substrate 1;
a second functional layer formed on a sidewall of the second via hole;
a fourth channel structure formed on the sidewall of the second functional layer corresponding to the first region and the bottom of the second through hole, and a second filling structure formed in the second through hole corresponding to the first region, the second region and the third region, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure;
and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
As can be seen from the above, in the method for forming a channel hole structure in a three-dimensional memory provided in the embodiment of the present invention, the channel hole structure in the three-dimensional memory is formed by two through hole forming processes of the first through hole and the second through hole, so that the process difficulty and the cost of the channel hole structure are greatly reduced, the problems of high process difficulty and high cost caused by an excessively large depth-to-width ratio of the through holes under the same aperture are solved, and the process difficulty and the cost of forming the three-dimensional memory are reduced.
In addition, according to the method for forming a via hole structure in a three-dimensional memory provided in the embodiment of the present invention, the fourth via structure exists only in the first region, but not in the first region, so that the fifth via structure is electrically connected to the first via structure in the first region, and the fifth via structure is electrically insulated from the first via structure in the third region, so that when the method is applied to a three-dimensional memory having an insulating ring, the via hole structure can be formed in the first region and the insulating ring structure can be formed in the third region at the same time, and the method is simple in process and low in cost.
In the description, each part is described in a progressive manner, each part is emphasized to be different from other parts, and the same and similar parts among the parts are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A method for forming a via hole structure in a three-dimensional memory, the method comprising:
providing a substrate, wherein a first stacking layer and a first insulating connecting layer are formed on the surface of the substrate, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in an interlaced mode;
forming a first via hole extending completely through the first stack layer and the first insulating connection layer and into the substrate surface;
forming a first channel structure on the surface of the substrate exposed by the first through hole;
forming a first functional layer on the side wall of the first through hole;
sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
forming a first groove in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
forming a third channel structure in the first groove, wherein the third channel structure is in contact with the second channel structure, and the third channel structure protrudes out of the first functional layer along the radial outward direction of the first through hole;
sequentially forming a second stacked layer and a second insulating connecting layer on one side of the third channel structure, which is far away from the substrate, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
forming a second via completely penetrating through the second stacked layer and the second insulating connection layer and extending into the third channel structure surface, a projection of the second via on the substrate at least partially overlapping a projection of the first via on the substrate;
forming a second functional layer on the side wall of the second through hole;
sequentially forming a fourth channel structure and a second filling structure on the side wall of the second functional layer and the bottom surface of the second through hole, wherein the surface of the second filling structure is lower than the surface of the fourth channel structure; and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
2. The method of forming as claimed in claim 1, wherein forming a first functional layer on the first via sidewall includes:
forming a first tunneling layer on the side wall of the first through hole and the surface of the first channel structure for generating charges;
forming a first storage layer on the surface of the first tunneling layer for storing charges;
forming a first blocking layer on the surface of the first storage layer, wherein the first blocking layer is used for blocking the charge in the first storage layer from flowing out;
forming a first protective layer on the surface of the first barrier layer, wherein the first protective layer is used for protecting the first barrier layer from being damaged in a subsequent removing process;
and removing the first protective layer, the first blocking layer, the first storage layer and the first tunneling layer to form a first functional layer.
3. The forming method according to claim 2, wherein forming a second channel structure and a first filling structure in sequence on the first functional layer side wall and the first channel structure surface, the surfaces of the second channel structure and the first filling structure being lower than the first insulating connection layer surface comprises:
forming a second channel layer covering the side wall of the first protective layer, the first channel structure and the surface of the first insulating connection layer;
forming a first filling layer covering the second channel layer;
removing part of the first filling layer to enable the surface of the first filling layer to be lower than the surface of the first insulation connecting layer, and forming a first filling structure;
and removing part of the second channel layer to enable the surface of the second channel layer to be lower than the first insulating connection layer, so as to form a second channel structure.
4. The method of forming as claimed in claim 1, further comprising: and forming a first mask layer on the surface of the first insulating connection layer.
5. The forming method according to claim 4, wherein forming a first groove in the first insulating connection layer, a projection of the first groove on the substrate completely covering a projection of the first via on the substrate comprises:
removing the first mask layer;
flattening the surface of the first insulating connection layer;
and removing part of the first insulating connection layer, and forming a first groove penetrating through the first insulating connection layer in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate.
6. The method of forming as claimed in claim 1, wherein forming the second functional layer on the second via sidewall includes:
forming a second tunneling layer on the side wall of the second through hole and the surface of the second channel structure, for generating charges;
forming a second storage layer on the surface of the second tunneling layer for storing charges;
forming a second blocking layer on the surface of the second storage layer, wherein the second blocking layer is used for blocking the charge in the second storage layer from flowing out;
forming a second protective layer on the surface of the second barrier layer, wherein the second protective layer is used for protecting the second barrier layer from being damaged in a subsequent removal process;
removing the second protective layer, the second blocking layer, the second storage layer and the second tunneling layer on the surface of the second channel structure to form a second functional layer;
sequentially forming a fourth channel structure and a second filling structure on the side wall of the second functional layer and the bottom of the second through hole, wherein the surfaces of the fourth channel structure and the second filling structure which are lower than the surface of the second insulating connecting layer comprise:
forming a fourth channel layer covering the side wall of the second protective layer, the bottom of the second through hole and the surface of the second insulating connecting layer;
forming a second filling layer covering the fourth channel layer;
removing part of the second filling layer to enable the surface of the second filling layer to be lower than the surface of the second insulating connecting layer, and forming a second filling structure;
and removing two parts of the fourth channel layer on the surface of the second insulating connecting layer to form a fourth channel structure, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
7. A three-dimensional memory, comprising:
the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a first via hole penetrating through the first stack layer and the first insulating connection layer and extending into the substrate surface;
a first channel structure formed on the substrate surface exposed by the first through hole;
the first functional layer is formed on the side wall of the first through hole;
a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure, the third channel structure protruding from the first functional layer in a radially outward direction of the first through hole;
a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a second via extending through the second stacked layer and the second insulating connection layer and into the third channel structure surface, a projection of the second via on the substrate at least partially overlapping a projection of the first via on the substrate;
the second functional layer is formed on the side wall of the second through hole;
a fourth channel structure and a second filling structure which are sequentially formed on the side wall of the second functional layer and the bottom surface of the second through hole, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure;
and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
8. A method for forming a via hole structure in a three-dimensional memory, the three-dimensional memory comprising a first region, a second region and a third region arranged along a word line direction, wherein the first region is used for forming the via hole structure, and the third region is used for forming an insulating ring structure, the method comprising:
providing a substrate, wherein a first stacking layer and a first insulating connecting layer are formed on the surface of the substrate, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in an interlaced mode;
forming a first via hole completely penetrating the first stack layer and the first insulating connection layer and extending into the substrate surface in the first region, the second region, and the third region;
forming a first channel structure on the surface of the substrate exposed by the first through hole;
forming a first functional layer on the side wall of the first through hole;
sequentially forming a second channel structure and a first filling structure on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
forming a first groove in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
forming a third channel structure in the first groove, wherein the third channel structure is in contact with the second channel structure, and the third channel structure protrudes out of the first functional layer along the radial outward direction of the first through hole;
sequentially forming a second stacked layer and a second insulating connecting layer on one side of the third channel structure, which is far away from the substrate, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
forming a second via hole completely penetrating through the second stacked layer and the second insulating connection layer and extending into the surface of the third channel structure in the first region, the second region, and the third region, a projection of the second via hole on the substrate at least partially overlapping a projection of the first via hole on the substrate;
forming a second functional layer on the side wall of the second through hole;
forming a fourth channel structure on the side wall of the second functional layer corresponding to the first area and the bottom of the second through hole, and forming a second filling structure in the second through hole corresponding to the first area, the second area and the third area, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure; and forming a fifth channel structure in a second groove formed by the fourth channel structure and the second filling structure, wherein the fifth channel structure is in contact with the fourth channel structure.
9. The forming method according to claim 8, wherein forming a fourth channel structure in the second functional layer side wall and the second through hole bottom corresponding to the first region, and forming a second filling structure in the second through hole corresponding to the first region, the second region, and the third region, a surface of the fourth channel structure being higher than a surface of the second filling structure includes:
forming a fourth channel layer covering the side wall of the second functional layer, the bottom of the second through hole and the surface of the second insulating connection layer in the first area, the second area and the second area;
forming a third filling layer covering the fourth channel layer in the first region, the second region and the second region, the third filling layer having an air gap therein;
forming a third mask layer on the surface of the third filling layer corresponding to the first area;
removing the third filling layer in the second area and the third area by taking the third mask layer as a mask;
removing the third mask layer;
taking the part of the third filling layer, which is positioned in the first area, as a mask, and removing the fourth channel layer positioned in the second area and the third area;
forming a fourth filling layer on the surface of the second functional layer positioned in the second area and the third area, wherein the filling performance of the fourth filling layer is better than that of the third filling layer;
removing the third filling layer on the surface of the fourth channel layer in the first area;
forming a second filling layer in the second through holes of the first area, the second area and the third area;
removing part of the second filling layer to enable the surface of the second filling layer to be lower than that of the second insulating connection layer, and forming a second filling structure;
and removing the part of the fourth channel layer, which is positioned on the surface of the second insulating connecting layer, to form a fourth channel structure, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure.
10. The method of forming as claimed in claim 8, wherein forming a first functional layer on the first via sidewall includes:
forming a first tunneling layer on the side wall of the first through hole and the surface of the first channel structure for generating charges;
forming a first storage layer on the surface of the first tunneling layer for storing charges;
forming a first blocking layer on the surface of the first storage layer, wherein the first blocking layer is used for blocking the charge in the first storage layer from flowing out;
forming a first protective layer on the surface of the first barrier layer, wherein the first protective layer is used for protecting the first barrier layer from being damaged in a subsequent removing process;
and removing the first protective layer, the first blocking layer, the first storage layer and the first tunneling layer to form a first functional layer.
11. The method of claim 10, wherein sequentially forming a second via structure and a first fill structure on the first functional layer sidewall and the first via structure surface, the second via structure and the first fill structure having surfaces lower than the first insulating connection layer surface comprises:
forming a second channel layer covering the side wall of the first protective layer, the first channel structure and the surface of the first insulating connection layer;
forming a first filling layer covering the second channel layer;
removing part of the first filling layer to enable the surface of the first filling layer to be lower than the surface of the first insulation connecting layer, and forming a first filling structure;
and removing part of the second channel layer to enable the surface of the second channel layer to be lower than the first insulating connection layer, so as to form a second channel structure.
12. A three-dimensional memory, comprising a first region, a second region and a third region arranged along a word line direction, wherein the first region is used for forming a channel hole structure, the third region is used for forming an insulating ring structure, and the three-dimensional memory comprises, along a direction perpendicular to the surface of the three-dimensional memory: the surface of the substrate is provided with a first stacking layer and a first insulating connecting layer, and the first stacking layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a first via hole extending completely through the first stack layer and the first insulating connection layer and into the substrate surface at the first region, the second region, and the third region;
forming a first channel structure on the surface of the substrate exposed by the first through hole;
a first functional layer formed on a sidewall of the first via hole;
a second channel structure and a first filling structure which are sequentially formed on the side wall of the first functional layer and the surface of the first channel structure, wherein the surfaces of the second channel structure and the first filling structure are lower than the surface of the first insulating connecting layer;
a first groove formed in the first insulating connection layer, wherein the projection of the first groove on the substrate completely covers the projection of the first through hole on the substrate;
a third channel structure formed in the first groove, the third channel structure being in contact with the second channel structure, the third channel structure protruding from the first functional layer in a radially outward direction of the first through hole;
a second stacked layer and a second insulating connecting layer which are sequentially formed on one side, away from the substrate, of the third channel structure, wherein the second stacked layer is composed of a plurality of oxide layers and nitride layers which are overlapped in a staggered mode;
a second via hole completely penetrating the second stacked layer and the second insulating connection layer in the first region, the second region, and the third region and extending into a surface of the third channel structure, a projection of the second via hole on the substrate at least partially overlapping a projection of the first via hole on the substrate;
a second functional layer formed on a sidewall of the second via hole;
a fourth channel structure formed on the sidewall of the second functional layer corresponding to the first region and the bottom of the second through hole, and a second filling structure formed in the second through hole corresponding to the first region, the second region and the third region, wherein the surface of the fourth channel structure is higher than the surface of the second filling structure;
and the fifth channel structure is formed in a second groove formed by the fourth channel structure and the second filling structure and is in contact with the fourth channel structure.
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