CN109003986A - Memory construction and forming method thereof - Google Patents
Memory construction and forming method thereof Download PDFInfo
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- CN109003986A CN109003986A CN201810890809.4A CN201810890809A CN109003986A CN 109003986 A CN109003986 A CN 109003986A CN 201810890809 A CN201810890809 A CN 201810890809A CN 109003986 A CN109003986 A CN 109003986A
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- 230000015654 memory Effects 0.000 title claims abstract description 59
- 238000010276 construction Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000003860 storage Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 148
- 230000006870 function Effects 0.000 claims description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229910021389 graphene Inorganic materials 0.000 claims description 14
- 239000002346 layers by function Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- -1 tin alkene Chemical class 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003197 catalytic effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 150000001336 alkenes Chemical class 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a kind of memory construction and forming method thereof, the memory construction includes: semiconductor substrate；Stacked structure in the semiconductor substrate, including the insulating layer and grid layer being stacked with, the material of the grid layer is two-dimentional conductive material；Through the channel structure of the storage stack structure to semiconductor substrate.The performance of the memory construction is improved.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of memory construction and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
In existing 3D NAND flash memory structure, control grid generallys use metal gates, is easy to expand there are metallic atom
Scattered problem, and the control grid resistance of the prior art is larger, leads to biggish RC retardation ratio, influences the performance of 3D nand flash memory.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of memory constructions and forming method thereof, can be improved and deposit
The performance of reservoir.
The present invention provides a kind of memory construction, comprising: semiconductor substrate；Stacking knot in the semiconductor substrate
Structure, including the insulating layer and grid layer being stacked with, the material of the grid layer is two-dimentional conductive material；Through the memory heap
Stack structure to semiconductor substrate channel structure.
Optionally, the grid layer includes the monoatomic layer of 1~10 layer of two-dimentional conductive material.
Optionally, the grid layer with a thickness of 0.3 nanometer to 3 nanometers.
Optionally, the work function of the grid layer is 4.4eV~5.2eV.
Optionally, the resistivity of the grid layer is less than the resistivity of tungsten.
Optionally, the material of the grid layer includes at least one of graphene and tin alkene.
Optionally, the channel structure includes the substrate epitaxial layer for being located at channel hole bottom, the function for covering channel hole side wall
Ergosphere and positioned at the function layer surface and fill the channel dielectric layer in full channel hole.
To solve the above-mentioned problems, a specific embodiment of the invention also provides a kind of forming method of memory construction,
It include: offer semiconductor substrate；Stacked structure is formed in the semiconductor substrate surface, the stacked structure includes being stacked with
Insulating layer and grid layer, the material of the grid layer is two-dimentional conductive material；Form the channel hole for running through the stacked structure；
The channel structure for running through the stacked structure is formed in the channel hole.
Optionally, the grid layer includes the monoatomic layer of 1~10 layer of two-dimentional conductive material.
Optionally, the grid layer with a thickness of 0.3 nanometer to 3 nanometers.
Optionally, using molecular beam epitaxy, chemical vapor deposition process, silicon carbide epitaxial growth method, metal catalytic extension
Growth method or atom layer deposition process form grid layer.
Optionally, the work function of the grid layer is 4.4eV~5.2eV.
Optionally, the resistivity of the grid layer is less than the resistivity of tungsten.
Optionally, the material of the grid layer includes at least one of graphene and tin alkene.
Optionally, the forming method of the channel structure includes: to form substrate epitaxial layer 301 in channel hole bottom；
Sidewall surfaces in the channel hole form functional layer；Channel Jie for filling the full channel hole is formed in the function layer surface
Matter layer.
In the forming method of memory construction of the invention, insulating layer and grid layer are directly formed in semiconductor substrate surface
Stacked structure, step can be saved the process.And the material of the grid layer is two-dimentional conductive material, resistivity is lower, can
RC retardation ratio is reduced, the programming time of memory can be shortened, improve the performance of memory.Also, the thickness of two-dimentional conductive material
It is lower, the thickness of stacked structure can be reduced, the density of memory cells of memory construction is improved.
Detailed description of the invention
Fig. 1 to Fig. 3 is the structural schematic diagram of the memory construction forming process of a specific embodiment of the invention.
Specific embodiment
The specific embodiment of memory construction provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
Fig. 1 to Fig. 3 is please referred to, is the structural schematic diagram of the storage organization forming process of the embodiment of the invention.
Referring to FIG. 1, providing semiconductor substrate 100, stacked structure 110, institute are formed on 100 surface of semiconductor substrate
Stating stacked structure 110 includes the insulating layer 111 and grid layer 112 being stacked with, and the material of the grid layer 112 is that two dimension is conductive
Material.
The semiconductor substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to device
Actual demand, can choose suitable semiconductor substrate 100, be not limited thereto.It is described partly to lead in the specific embodiment
Body substrate 100 is monocrystalline silicon wafer crystal.
Multilayer dielectric layer 111 and stacked gate layer 112, insulating layer 111 are sequentially formed on 100 surface of semiconductor substrate
Stacking is spaced apart from each other with grid layer 112.In the specific embodiment, 111 material of insulating layer is silica, specific at other
In embodiment, the material of the insulating layer 111 can also be other insulating dielectric materials such as silicon oxynitride.
The material of the grid layer 112 is two-dimentional conductive material.The electronics of two-dimentional conductive material conducts in two-dimensional surface,
Scattered power is low or without scattering, and resistivity is lower, as gate layer material, to reduce RC retardation ratio.Can using molecular beam epitaxy,
Chemical vapor deposition process, silicon carbide epitaxial growth method, metal catalytic epitaxial growth method or atom layer deposition process form described
Grid layer 112.The thickness of the grid layer 112 is excessive to will lead to electric conductivity decline.In a specific embodiment of the invention,
The grid layer 112 includes the monoatomic layer of 1~10 layer of two-dimentional conductive material.The thickness of the grid layer 112 can be
0.3 nanometer to 3 nanometers.
As the material of grid layer 112, the work function of the two dimension conductive material need to be met the requirements, the specific embodiment
In, the work function of the grid layer 112 is 4.4eV~5.2eV.It can be by adjusting the material and formation work of grid layer 112
Skill adjusts the work function of the grid layer 112.
The resistivity of the grid layer 112 is less than the resistivity of tungsten, compared with use 3-dimensional metal material is as grid, adopts
It uses two-dimentional conductive material that there is lower resistance as grid layer 112, can reduce RC retardation ratio, improve the programming effect of memory
Rate.Also, two-dimentional conductive material can successively be grown, and thickness is lowerly controllable, can reduce the thickness of stacked structure, raising is deposited
The density of memory cells of reservoir structures.
In the specific embodiment, the material of the grid layer 112 is graphene.With common metal gate material W phase
Resistivity than, graphene is less than W, and work function and W are close, can substitute metal material, as the material of grid layer 112,
And improve the performance of memory construction.And the atom of graphene is not easy to spread, without being additionally formed diffusion barrier layer, so as to
Step is saved the process, the thickness of grid layer is reduced.
In another specific embodiment, molecular beam epitaxy (MBE) can be used, it is directly heavy on 111 surface of insulating layer
The solid source carbon atom of product forms graphene layer.Preparation process needs ultrahigh vacuum, the insulating layer to reduce pollution, as epitaxial substrate
111 temperature ranges are 600 degrees Celsius to 1200 degrees Celsius.
In another specific embodiment, graphene layer can also be formed using chemical vapor deposition process.Specifically, with
Methane (CH4) it is used as presoma, using metallic substrates as deposition substrate, chemical vapor deposition process is used in metal substrate surface
It is formed after graphene layer, removes the metallic substrates, graphene layer is transferred to 111 surface of insulating layer.In other tools
In body embodiment, graphene layer can also be formed in the direct chemical vapor deposition in 111 surface of insulating layer.
In other specific embodiments, the material of the grid layer 112 can also be the two-dimentional conductive material such as tin alkene.
Referring to FIG. 2, forming the channel hole 200 for running through the stacked structure 110.
Patterned masking layer is formed on 110 surface of stacked structure, the graphic definition of the Patterned masking layer waits for shape
At channel hole 200 positions and dimensions, using the Patterned masking layer as exposure mask, be sequentially etched the stacked structure 110 to
Semiconductor substrate 100 forms the channel hole 200.
The insulating layer 111 and grid layer 112 can be sequentially etched with using plasma etching technics to the semiconductor
100 surface of substrate forms the channel hole 200.
Further include the edge for etching the stacked structure 100 before forming the channel hole 200, forms stepped area
(not shown).
Referring to FIG. 3, forming the channel structure 300 for running through the stacked structure 110 in the channel hole 200.
It forms the channel structure 300 to specifically include: forming substrate epitaxial layer 301 in 200 bottom of channel hole；Institute
The sidewall surfaces for stating channel hole 200 form functional layer 302；It is formed on 302 surface of functional layer and fills the full channel hole 200
Channel dielectric layer 303.
The material of the substrate epitaxial layer 301 is that polysilicon further includes adopting before forming the substrate epitaxial layer 301
Prerinse is carried out to 200 bottom of channel hole with dry or wet technique, to remove the impurity of 200 bottom of channel hole
Deng to improve the quality of substrate epitaxial layer 301.
The functional layer 302 further comprises the barrier layer stacked gradually, electric charge capture layer, tunnel layer and channel layer.
In the specific embodiment, the functional layer 302 is the composite layer of O-N-O-P (oxide-nitride-oxide-polysilicon)
Structure.
The material of the channel dielectric layer 303 can be the insulating dielectric materials such as silica, silicon oxynitride.
In the forming method of the memory construction of above-mentioned specific embodiment, insulation is directly formed in semiconductor substrate surface
The stacked structure of layer and grid layer, can save the process step.And the material of the grid layer is two-dimentional conductive material, resistance compared with
It is low, it can reduce RC retardation ratio, the programming time of memory can be shortened, improve the performance of memory.Also, two-dimentional conductive material
Thickness it is lower, the thickness of stacked structure can be reduced, improve the density of memory cells of memory construction.
A specific embodiment of the invention also provides a kind of memory construction.
Referring to FIG. 3, the structural schematic diagram of the memory construction for the embodiment of the invention.
The memory construction includes: semiconductor substrate 100；Stacked structure in the semiconductor substrate 100
110, the stacked structure includes the insulating layer 111 and grid layer 112 being stacked with；Through the stacked structure 110 to described
The channel structure of semiconductor substrate 100.
The semiconductor substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to device
Actual demand, can choose suitable semiconductor substrate 100, be not limited thereto.It is described partly to lead in the specific embodiment
Body substrate 100 is monocrystalline silicon wafer crystal.
In the specific embodiment, 111 material of insulating layer is silica, described in other specific embodiments
The material of insulating layer 111 can also be other insulating dielectric materials such as silicon oxynitride.
The material of the grid layer 112 is two-dimentional conductive material.The electronics of two-dimentional conductive material conducts in two-dimensional surface,
Scattered power is low or without scattering, and resistivity is lower, as gate layer material, to reduce RC retardation ratio.Chemical vapor deposition can be used
Product technique or atom layer deposition process form the grid layer 112.The thickness of the grid layer 112 is excessive to will lead to electric conductivity
Decline；The thickness of the grid layer 112 can not be too small, to avoid the lower problem of the deposition quality of grid layer 112.In this hair
In bright specific embodiment, the grid layer 112 includes the monoatomic layer of 1~10 layer of two-dimentional conductive material.The grid
The thickness of pole layer 112 can be 0.3 nanometer to 3 nanometers.
As the material of grid layer 112, the work function of the two dimension conductive material need to be met the requirements, the specific embodiment
In, the work function of the grid layer 112 is 4.4eV~5.2eV.It can be by adjusting the material and formation work of grid layer 112
Skill adjusts the work function of the grid layer 112.
The resistivity of the grid layer 112 is less than the resistivity of tungsten, compared with use 3-dimensional metal material is as grid, adopts
It uses two-dimentional conductive material that there is lower resistance as grid layer 112, can reduce RC retardation ratio, improve the programming effect of memory
Rate.Also, two-dimentional conductive material can successively be grown, and thickness is lowerly controllable, can be reduced the thickness of stacked structure 110, be mentioned
The density of memory cells of high memory construction.
In the specific embodiment, the material of the grid layer 112 is graphene.With common metal gate material W phase
Resistivity than, graphene is less than W, and work function and W are close, can substitute metal material, as the material of grid layer 112,
And improve the performance of memory construction.
In other specific embodiments, the material of the grid layer 112 can also be the two-dimentional conductive material such as tin alkene.
The channel structure includes the substrate epitaxial layer 301 and covering channel hole side wall for being formed in channel hole bottom
Functional layer 302 and positioned at 302 surface of functional layer and fill the channel dielectric layer 303 in full channel hole.The functional layer 302
It further comprise barrier layer, electric charge capture layer, tunnel layer and the channel layer stacked gradually from channel hole sidewall surfaces.This is specific
In embodiment, the functional layer 302 is the lamination layer structure of O-N-O-P (oxide-nitride-oxide-polysilicon).Institute
The material for stating channel dielectric layer 303 can be silica.
In the memory construction of above-mentioned specific embodiment, the material of grid layer is two-dimentional conductive material, and resistance is lower, energy
RC retardation ratio is enough reduced, the programming time of memory can be shortened, improve the performance of memory.Also, the thickness of two-dimentional conductive material
It spends lower, the thickness of stacked structure can be reduced, improve the density of memory cells of memory construction.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (15)
1. a kind of memory construction characterized by comprising
Semiconductor substrate；
Stacked structure in the semiconductor substrate, including the insulating layer and grid layer being stacked with, the grid layer
Material is two-dimentional conductive material；
Through the channel structure of the storage stack structure to semiconductor substrate.
2. memory construction according to claim 1, which is characterized in that the grid layer includes 1~10 layer of two dimension
The monoatomic layer of conductive material.
3. memory construction according to claim 1, which is characterized in that the grid layer is received with a thickness of 0.3 nanometer to 3
Rice.
4. memory construction according to claim 1, which is characterized in that the work function of the grid layer be 4.4eV~
5.2eV。
5. memory construction according to claim 1, which is characterized in that the resistivity of the grid layer is less than the resistance of tungsten
Rate.
6. memory construction according to claim 1, which is characterized in that the material of the grid layer includes graphene and tin
At least one of alkene.
7. memory construction according to claim 1, which is characterized in that the channel structure includes being located at channel hole bottom
Substrate epitaxial layer, cover the functional layer of channel hole side wall and positioned at the function layer surface and fill the channel in full channel hole
Dielectric layer.
8. a kind of forming method of memory construction characterized by comprising
Semiconductor substrate is provided；
Stacked structure is formed in the semiconductor substrate surface, the stacked structure includes the insulating layer and grid being stacked with
Layer, the material of the grid layer are two-dimentional conductive material；
Form the channel hole for running through the stacked structure；
The channel structure for running through the stacked structure is formed in the channel hole.
9. the forming method of memory construction according to claim 8, which is characterized in that the grid layer includes 1~10
The monoatomic layer of the layer two-dimentional conductive material.
10. the forming method of memory construction according to claim 8, which is characterized in that the grid layer with a thickness of
0.3 nanometer to 3 nanometers.
11. the forming method of memory construction according to claim 8, which is characterized in that use molecular beam epitaxy, chemistry
Gas-phase deposition, silicon carbide epitaxial growth method, metal catalytic epitaxial growth method or atom layer deposition process form grid layer.
12. the forming method of memory construction according to claim 8, which is characterized in that the work function of the grid layer
For 4.4eV~5.2eV.
13. the forming method of memory construction according to claim 8, which is characterized in that the resistivity of the grid layer
Less than the resistivity of tungsten.
14. the forming method of memory construction according to claim 8, which is characterized in that the material packet of the grid layer
Include at least one of graphene and tin alkene.
15. the forming method of memory construction according to claim 8, which is characterized in that the formation of the channel structure
Method includes: to form substrate epitaxial in channel hole bottom；Sidewall surfaces in the channel hole form functional layer；Described
Function layer surface forms the channel dielectric layer for filling the full channel hole.
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|---|---|---|---|
| CN201810890809.4A CN109003986A (en) | 2018-08-07 | 2018-08-07 | Memory construction and forming method thereof |
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| CN201810890809.4A CN109003986A (en) | 2018-08-07 | 2018-08-07 | Memory construction and forming method thereof |
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Family
ID=64596177
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Cited By (1)
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